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Code Issues Releases Wiki Activity

dt-bindings: Remove PicoXcell bindings

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PicoXcell has had nothing but treewide cleanups for at least the last 8
years and no signs of activity. The most recent activity is a yocto vendor
kernel based on v3.0 in 2015.

Cc: linux-crypto@vger.kernel.org
Acked-by: Jamie Iles <jamie@jamieiles.com>
Link: https://lore.kernel.org/r/20201210200315.2965567-5-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring 2020-12-10 14:03:15 -06:00
parent 18ce7f4fde
commit a217d8711d
4 changed files with 0 additions and 54 deletions
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24
Documentation/devicetree/bindings/arm/picoxcell.txt
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@ -1,24 +0,0 @@
Picochip picoXcell device tree bindings.
========================================
Required root node properties:
- compatible:
- "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
- "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
- "picochip,pc3x3" : picoXcell PC3X3 device based board.
- "picochip,pc3x2" : picoXcell PC3X2 device based board.
Timers required properties:
- compatible = "picochip,pc3x2-timer"
- interrupts : The single IRQ line for the timer.
- clock-freq : The frequency in HZ of the timer.
- reg : The register bank for the timer.
Note: two timers are required - one for the scheduler clock and one for the
event tick/NOHZ.
VIC required properties:
- compatible = "arm,pl192-vic".
- interrupt-controller.
- reg : The register bank for the device.
- #interrupt-cells : Must be 1.

21
Documentation/devicetree/bindings/crypto/picochip-spacc.txt
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@ -1,21 +0,0 @@
Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
Picochip picoXcell devices contain crypto offload engines that may be used for
IPSEC and femtocell layer 2 ciphering.
Required properties:
- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
- reg : Offset and length of the register set for this device
- interrupts : The interrupt line from the SPAcc.
- ref-clock : The input clock that drives the SPAcc.
Example SPAcc node:
spacc@10000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&ipsec_clk>, "ref";
};

2
Documentation/devicetree/bindings/net/macb.txt
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@ -7,8 +7,6 @@ Required properties:
Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
Use "cdns,np4-macb" for NP4 SoC devices.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
the Cadence GEM, or the generic form: "cdns,gem".
Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.

7
Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
View file

@ -38,13 +38,6 @@ properties:
clock-frequency: true
clock-freq:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: |
Has the same meaning as the 'clock-frequency' property - timer clock
frequency in HZ, but is defined only for the backwards compatibility
with the picoxcell platform.
additionalProperties: false
required: