mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-22 02:20:40 +00:00
MIPS: lantiq: dma: reset correct number of channel
[ Upstream commit 5ca9ce2ba4
]
Different SoCs have a different number of channels, e.g .:
* amazon-se has 10 channels,
* danube+ar9 have 20 channels,
* vr9 has 28 channels,
* ar10 has 24 channels.
We can read the ID register and, depending on the reported
number of channels, reset the appropriate number of channels.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
6a5b3f5dfb
commit
a244da2984
1 changed files with 6 additions and 5 deletions
|
@ -31,6 +31,7 @@
|
||||||
#define LTQ_DMA_PCTRL 0x44
|
#define LTQ_DMA_PCTRL 0x44
|
||||||
#define LTQ_DMA_IRNEN 0xf4
|
#define LTQ_DMA_IRNEN 0xf4
|
||||||
|
|
||||||
|
#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
|
||||||
#define DMA_DESCPT BIT(3) /* descriptor complete irq */
|
#define DMA_DESCPT BIT(3) /* descriptor complete irq */
|
||||||
#define DMA_TX BIT(8) /* TX channel direction */
|
#define DMA_TX BIT(8) /* TX channel direction */
|
||||||
#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
|
#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
|
||||||
|
@ -41,7 +42,6 @@
|
||||||
#define DMA_POLL BIT(31) /* turn on channel polling */
|
#define DMA_POLL BIT(31) /* turn on channel polling */
|
||||||
#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
|
#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
|
||||||
#define DMA_2W_BURST BIT(1) /* 2 word burst length */
|
#define DMA_2W_BURST BIT(1) /* 2 word burst length */
|
||||||
#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
|
|
||||||
#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
|
#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
|
||||||
#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
|
#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
|
||||||
|
|
||||||
|
@ -207,7 +207,7 @@ ltq_dma_init(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct clk *clk;
|
struct clk *clk;
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
unsigned id;
|
unsigned int id, nchannels;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
@ -229,17 +229,18 @@ ltq_dma_init(struct platform_device *pdev)
|
||||||
ltq_dma_w32(0, LTQ_DMA_IRNEN);
|
ltq_dma_w32(0, LTQ_DMA_IRNEN);
|
||||||
|
|
||||||
/* reset/configure each channel */
|
/* reset/configure each channel */
|
||||||
for (i = 0; i < DMA_MAX_CHANNEL; i++) {
|
id = ltq_dma_r32(LTQ_DMA_ID);
|
||||||
|
nchannels = ((id & DMA_ID_CHNR) >> 20);
|
||||||
|
for (i = 0; i < nchannels; i++) {
|
||||||
ltq_dma_w32(i, LTQ_DMA_CS);
|
ltq_dma_w32(i, LTQ_DMA_CS);
|
||||||
ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
|
ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
|
||||||
ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
|
ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
|
||||||
ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
|
ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
|
||||||
}
|
}
|
||||||
|
|
||||||
id = ltq_dma_r32(LTQ_DMA_ID);
|
|
||||||
dev_info(&pdev->dev,
|
dev_info(&pdev->dev,
|
||||||
"Init done - hw rev: %X, ports: %d, channels: %d\n",
|
"Init done - hw rev: %X, ports: %d, channels: %d\n",
|
||||||
id & 0x1f, (id >> 16) & 0xf, id >> 20);
|
id & 0x1f, (id >> 16) & 0xf, nchannels);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue