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ath5k: Update spur mitigation filter for turbo/half/quarter
* Add spur mitigation filter support for half/quarter and turbo. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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1 changed files with 32 additions and 21 deletions
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@ -1622,7 +1622,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
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spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
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spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
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/* XXX: Half/Quarter channels ?*/
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if (channel->hw_value & CHANNEL_TURBO)
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if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
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spur_detection_window *= 2;
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for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
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@ -1651,32 +1651,43 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
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* Calculate deltas:
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* spur_freq_sigma_delta -> spur_offset / sample_freq << 21
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* spur_delta_phase -> spur_offset / chip_freq << 11
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* Note: Both values have 100KHz resolution
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* Note: Both values have 100Hz resolution
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*/
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/* XXX: Half/Quarter rate channels ? */
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switch (channel->hw_value) {
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case CHANNEL_A:
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/* Both sample_freq and chip_freq are 40MHz */
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spur_delta_phase = (spur_offset << 17) / 25;
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spur_freq_sigma_delta = (spur_delta_phase >> 10);
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
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break;
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case CHANNEL_G:
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/* sample_freq -> 40MHz chip_freq -> 44MHz
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* (for b compatibility) */
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spur_freq_sigma_delta = (spur_offset << 8) / 55;
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spur_delta_phase = (spur_offset << 17) / 25;
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
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break;
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case CHANNEL_T:
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case CHANNEL_TG:
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switch (ah->ah_bwmode) {
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case AR5K_BWMODE_40MHZ:
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/* Both sample_freq and chip_freq are 80MHz */
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spur_delta_phase = (spur_offset << 16) / 25;
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spur_freq_sigma_delta = (spur_delta_phase >> 10);
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
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break;
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case AR5K_BWMODE_10MHZ:
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/* Both sample_freq and chip_freq are 20MHz (?) */
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spur_delta_phase = (spur_offset << 18) / 25;
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spur_freq_sigma_delta = (spur_delta_phase >> 10);
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
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case AR5K_BWMODE_5MHZ:
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/* Both sample_freq and chip_freq are 10MHz (?) */
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spur_delta_phase = (spur_offset << 19) / 25;
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spur_freq_sigma_delta = (spur_delta_phase >> 10);
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symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
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default:
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return;
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if (channel->hw_value == CHANNEL_A) {
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/* Both sample_freq and chip_freq are 40MHz */
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spur_delta_phase = (spur_offset << 17) / 25;
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spur_freq_sigma_delta =
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(spur_delta_phase >> 10);
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symbol_width =
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AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
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} else {
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/* sample_freq -> 40MHz chip_freq -> 44MHz
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* (for b compatibility) */
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spur_delta_phase = (spur_offset << 17) / 25;
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spur_freq_sigma_delta =
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(spur_offset << 8) / 55;
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symbol_width =
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AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
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}
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break;
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}
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/* Calculate pilot and magnitude masks */
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