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drm/amd/display: Fix bug use wrong pp interface
Used wrong pp interface, the original interface is exposed by dpm on SI and paritial CI. Pointed out by Francis David <david.francis@amd.com> v2: dal only need to set min_dcefclk and min_fclk to smu. so use display_clock_voltage_request interface, instand of update all display configuration. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 10 additions and 2 deletions
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@ -480,12 +480,20 @@ void pp_rv_set_display_requirement(struct pp_smu *pp,
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{
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struct dc_context *ctx = pp->ctx;
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struct amdgpu_device *adev = ctx->driver_context;
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void *pp_handle = adev->powerplay.pp_handle;
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const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
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struct pp_display_clock_request clock = {0};
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if (!pp_funcs || !pp_funcs->display_configuration_changed)
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if (!pp_funcs || !pp_funcs->display_clock_voltage_request)
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return;
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amdgpu_dpm_display_configuration_changed(adev);
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clock.clock_type = amd_pp_dcf_clock;
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clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;
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pp_funcs->display_clock_voltage_request(pp_handle, &clock);
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clock.clock_type = amd_pp_f_clock;
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clock.clock_freq_in_khz = req->hard_min_fclk_khz;
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pp_funcs->display_clock_voltage_request(pp_handle, &clock);
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}
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void pp_rv_set_wm_ranges(struct pp_smu *pp,
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