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RISC-V: fix sifive and thead section mismatches in errata

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When CONFIG_MODULES is set, __init_or_module becomes <empty>, but when
CONFIG_MODULES is not set, __init_or_module becomes __init.
In the latter case, it causes section mismatch warnings:

WARNING: modpost: vmlinux.o: section mismatch in reference: riscv_fill_cpu_mfr_info (section: .text) -> sifive_errata_patch_func (section: .init.text)
WARNING: modpost: vmlinux.o: section mismatch in reference: riscv_fill_cpu_mfr_info (section: .text) -> thead_errata_patch_func (section: .init.text)

Fixes: bb3f89487f ("RISC-V: hwprobe: Remove __init on probe_vendor_features()")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Evan Green  <evan@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230429155247.12131-1-rdunlap@infradead.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Randy Dunlap 2023-04-29 08:52:47 -07:00 committed by Palmer Dabbelt
parent 41cad8284d
commit a2a58b5ca1
No known key found for this signature in database
GPG key ID: 2E1319F35FBB1889
2 changed files with 6 additions and 8 deletions
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6
arch/riscv/errata/sifive/errata.c
View file

@ -82,10 +82,8 @@ static void __init_or_module warn_miss_errata(u32 miss_errata)
pr_warn("----------------------------------------------------------------\n");
}
void __init_or_module sifive_errata_patch_func(struct alt_entry *begin,
struct alt_entry *end,
unsigned long archid,
unsigned long impid,
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
unsigned int stage)
{
struct alt_entry *alt;

2
arch/riscv/errata/thead/errata.c
View file

@ -83,7 +83,7 @@ static u32 thead_errata_probe(unsigned int stage,
return cpu_req_errata;
}
void __init_or_module thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
unsigned long archid, unsigned long impid,
unsigned int stage)
{