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clk: qcom: camcc-sm8450: switch to parent_hws
Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103145515.1164020-6-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov
Bjorn Andersson
parent
17f0b48f8d
commit
a2a796c1d6
1 changed files with 162 additions and 162 deletions
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@ -95,8 +95,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -118,8 +118,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0_out_odd",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll0.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -166,8 +166,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll1_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll1.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll1.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -237,8 +237,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll3_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll3.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll3.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -285,8 +285,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll4_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll4.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll4.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -333,8 +333,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll5_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll5.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll5.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -381,8 +381,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll6_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll6.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll6.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -429,8 +429,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll7_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll7.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll7.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -477,8 +477,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll8_out_even",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_pll8.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll8.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1268,8 +1268,8 @@ static struct clk_branch cam_cc_gdsc_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_gdsc_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_xo_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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@ -1286,8 +1286,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_bps_ahb_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_slow_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1304,8 +1304,8 @@ static struct clk_branch cam_cc_bps_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_bps_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_bps_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_bps_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1322,8 +1322,8 @@ static struct clk_branch cam_cc_bps_fast_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_bps_fast_ahb_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_fast_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1340,8 +1340,8 @@ static struct clk_branch cam_cc_camnoc_axi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_camnoc_axi_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_camnoc_axi_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1358,8 +1358,8 @@ static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_camnoc_dcd_xo_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_xo_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1376,8 +1376,8 @@ static struct clk_branch cam_cc_cci_0_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cci_0_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_cci_0_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_cci_0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1394,8 +1394,8 @@ static struct clk_branch cam_cc_cci_1_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cci_1_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_cci_1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_cci_1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1412,8 +1412,8 @@ static struct clk_branch cam_cc_core_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_core_ahb_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_slow_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1430,8 +1430,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_ahb_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_slow_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1448,8 +1448,8 @@ static struct clk_branch cam_cc_cpas_bps_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_bps_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_bps_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_bps_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1466,8 +1466,8 @@ static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_fast_ahb_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_fast_ahb_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1484,8 +1484,8 @@ static struct clk_branch cam_cc_cpas_ife_0_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_ife_0_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_ife_0_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_ife_0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1502,8 +1502,8 @@ static struct clk_branch cam_cc_cpas_ife_1_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_ife_1_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_ife_1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_ife_1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1520,8 +1520,8 @@ static struct clk_branch cam_cc_cpas_ife_2_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_ife_2_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_ife_2_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_ife_2_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1538,8 +1538,8 @@ static struct clk_branch cam_cc_cpas_ife_lite_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_ife_lite_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_ife_lite_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1556,8 +1556,8 @@ static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_ipe_nps_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_ipe_nps_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1574,8 +1574,8 @@ static struct clk_branch cam_cc_cpas_sbi_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_sbi_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_ife_0_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_ife_0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1592,8 +1592,8 @@ static struct clk_branch cam_cc_cpas_sfe_0_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_sfe_0_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_sfe_0_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_sfe_0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1610,8 +1610,8 @@ static struct clk_branch cam_cc_cpas_sfe_1_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cpas_sfe_1_clk",
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.parent_data = &(const struct clk_parent_data) {
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.hw = &cam_cc_sfe_1_clk_src.clkr.hw,
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_sfe_1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -1628,8 +1628,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
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.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csi0phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csi0phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1646,8 +1646,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csi1phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csi1phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1664,8 +1664,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csi2phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csi2phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1682,8 +1682,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csi3phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csi3phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1700,8 +1700,8 @@ static struct clk_branch cam_cc_csi4phytimer_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csi4phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csi4phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csi4phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1718,8 +1718,8 @@ static struct clk_branch cam_cc_csi5phytimer_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csi5phytimer_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csi5phytimer_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csi5phytimer_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1736,8 +1736,8 @@ static struct clk_branch cam_cc_csid_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csid_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_csid_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1754,8 +1754,8 @@ static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csid_csiphy_rx_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1772,8 +1772,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csiphy0_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1790,8 +1790,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csiphy1_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1808,8 +1808,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csiphy2_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1826,8 +1826,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csiphy3_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1844,8 +1844,8 @@ static struct clk_branch cam_cc_csiphy4_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csiphy4_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1862,8 +1862,8 @@ static struct clk_branch cam_cc_csiphy5_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_csiphy5_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1880,8 +1880,8 @@ static struct clk_branch cam_cc_icp_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_icp_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1898,8 +1898,8 @@ static struct clk_branch cam_cc_icp_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_icp_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_icp_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_icp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1916,8 +1916,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1934,8 +1934,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_0_dsp_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1952,8 +1952,8 @@ static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_0_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1970,8 +1970,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_1_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1988,8 +1988,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_1_dsp_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2006,8 +2006,8 @@ static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_1_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2024,8 +2024,8 @@ static struct clk_branch cam_cc_ife_2_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_2_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2042,8 +2042,8 @@ static struct clk_branch cam_cc_ife_2_dsp_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_2_dsp_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2060,8 +2060,8 @@ static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_2_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2078,8 +2078,8 @@ static struct clk_branch cam_cc_ife_lite_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_lite_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2096,8 +2096,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_lite_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_lite_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2114,8 +2114,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_lite_cphy_rx_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2132,8 +2132,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ife_lite_csid_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2150,8 +2150,8 @@ static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ipe_nps_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2168,8 +2168,8 @@ static struct clk_branch cam_cc_ipe_nps_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ipe_nps_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ipe_nps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2186,8 +2186,8 @@ static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ipe_nps_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2204,8 +2204,8 @@ static struct clk_branch cam_cc_ipe_pps_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ipe_pps_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ipe_nps_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2222,8 +2222,8 @@ static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_ipe_pps_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2240,8 +2240,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_jpeg_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_jpeg_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_jpeg_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2258,8 +2258,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk0_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2276,8 +2276,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk1_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2294,8 +2294,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk2_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk2_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk2_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2312,8 +2312,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk3_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk3_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk3_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2330,8 +2330,8 @@ static struct clk_branch cam_cc_mclk4_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk4_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk4_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk4_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2348,8 +2348,8 @@ static struct clk_branch cam_cc_mclk5_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk5_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk5_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk5_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2366,8 +2366,8 @@ static struct clk_branch cam_cc_mclk6_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk6_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk6_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk6_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2384,8 +2384,8 @@ static struct clk_branch cam_cc_mclk7_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_mclk7_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_mclk7_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_mclk7_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2402,8 +2402,8 @@ static struct clk_branch cam_cc_qdss_debug_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_qdss_debug_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_qdss_debug_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_qdss_debug_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2420,8 +2420,8 @@ static struct clk_branch cam_cc_qdss_debug_xo_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_qdss_debug_xo_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_xo_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_xo_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2438,8 +2438,8 @@ static struct clk_branch cam_cc_sbi_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sbi_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2456,8 +2456,8 @@ static struct clk_branch cam_cc_sbi_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sbi_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_ife_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2474,8 +2474,8 @@ static struct clk_branch cam_cc_sfe_0_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sfe_0_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_sfe_0_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_sfe_0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2492,8 +2492,8 @@ static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sfe_0_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2510,8 +2510,8 @@ static struct clk_branch cam_cc_sfe_1_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sfe_1_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_sfe_1_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_sfe_1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2528,8 +2528,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sfe_1_fast_ahb_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -2546,8 +2546,8 @@ static struct clk_branch cam_cc_sleep_clk = {
|
|||
.enable_mask = BIT(0),
|
||||
.hw.init = &(const struct clk_init_data) {
|
||||
.name = "cam_cc_sleep_clk",
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.hw = &cam_cc_sleep_clk_src.clkr.hw,
|
||||
.parent_hws = (const struct clk_hw*[]) {
|
||||
&cam_cc_sleep_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
|
|||
Loading…
Reference in a new issue