EDAC/amd64: Drop dbam_to_cs() for Family 17h and later
The same function is used to calculate chip select size for all Zen-based family/models. Therefore, a family/model function pointer is not necessary. Drop the dbam_to_cs() function pointer for Family 17h and later systems. Also, move the Family 17h function to avoid a forward declaration. Rename it to indicate that the UMC Address Mask is used rather than the legacy DBAM value. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20230127170419.1824692-9-yazen.ghannam@amd.com
This commit is contained in:
Yazen Ghannam
Borislav Petkov (AMD)
parent
c0984666fd
commit
a2e59ab8e9
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@ -1424,6 +1424,84 @@ static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
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return cs_mode;
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}
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static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
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unsigned int cs_mode, int csrow_nr)
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{
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u32 addr_mask_orig, addr_mask_deinterleaved;
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u32 msb, weight, num_zero_bits;
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int cs_mask_nr = csrow_nr;
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int dimm, size = 0;
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/* No Chip Selects are enabled. */
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if (!cs_mode)
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return size;
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/* Requested size of an even CS but none are enabled. */
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if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
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return size;
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/* Requested size of an odd CS but none are enabled. */
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if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
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return size;
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/*
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* Family 17h introduced systems with one mask per DIMM,
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* and two Chip Selects per DIMM.
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*
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* CS0 and CS1 -> MASK0 / DIMM0
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* CS2 and CS3 -> MASK1 / DIMM1
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*
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* Family 19h Model 10h introduced systems with one mask per Chip Select,
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* and two Chip Selects per DIMM.
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*
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* CS0 -> MASK0 -> DIMM0
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* CS1 -> MASK1 -> DIMM0
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* CS2 -> MASK2 -> DIMM1
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* CS3 -> MASK3 -> DIMM1
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*
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* Keep the mask number equal to the Chip Select number for newer systems,
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* and shift the mask number for older systems.
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*/
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dimm = csrow_nr >> 1;
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if (!fam_type->flags.zn_regs_v2)
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cs_mask_nr >>= 1;
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/* Asymmetric dual-rank DIMM support. */
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if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
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addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
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else
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addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
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/*
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* The number of zero bits in the mask is equal to the number of bits
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* in a full mask minus the number of bits in the current mask.
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*
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* The MSB is the number of bits in the full mask because BIT[0] is
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* always 0.
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*
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* In the special 3 Rank interleaving case, a single bit is flipped
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* without swapping with the most significant bit. This can be handled
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* by keeping the MSB where it is and ignoring the single zero bit.
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*/
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msb = fls(addr_mask_orig) - 1;
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weight = hweight_long(addr_mask_orig);
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num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
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/* Take the number of zero bits off from the top of the mask. */
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addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1);
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edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
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edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig);
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edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);
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/* Register [31:1] = Address [39:9]. Size is in kBs here. */
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size = (addr_mask_deinterleaved >> 2) + 1;
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/* Return size in MBs. */
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return size >> 10;
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}
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static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
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{
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int dimm, size0, size1, cs0, cs1, cs_mode;
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@ -1436,8 +1514,8 @@ static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
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cs_mode = umc_get_cs_mode(dimm, ctrl, pvt);
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size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0);
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size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1);
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size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0);
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size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1);
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amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
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cs0, size0,
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@ -2139,84 +2217,6 @@ static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
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return ddr3_cs_size(cs_mode, false);
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}
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static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
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unsigned int cs_mode, int csrow_nr)
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{
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u32 addr_mask_orig, addr_mask_deinterleaved;
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u32 msb, weight, num_zero_bits;
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int cs_mask_nr = csrow_nr;
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int dimm, size = 0;
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/* No Chip Selects are enabled. */
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if (!cs_mode)
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return size;
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/* Requested size of an even CS but none are enabled. */
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if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
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return size;
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/* Requested size of an odd CS but none are enabled. */
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if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
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return size;
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/*
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* Family 17h introduced systems with one mask per DIMM,
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* and two Chip Selects per DIMM.
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*
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* CS0 and CS1 -> MASK0 / DIMM0
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* CS2 and CS3 -> MASK1 / DIMM1
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*
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* Family 19h Model 10h introduced systems with one mask per Chip Select,
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* and two Chip Selects per DIMM.
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*
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* CS0 -> MASK0 -> DIMM0
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* CS1 -> MASK1 -> DIMM0
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* CS2 -> MASK2 -> DIMM1
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* CS3 -> MASK3 -> DIMM1
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*
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* Keep the mask number equal to the Chip Select number for newer systems,
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* and shift the mask number for older systems.
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*/
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dimm = csrow_nr >> 1;
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if (!fam_type->flags.zn_regs_v2)
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cs_mask_nr >>= 1;
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/* Asymmetric dual-rank DIMM support. */
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if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
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addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
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else
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addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
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/*
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* The number of zero bits in the mask is equal to the number of bits
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* in a full mask minus the number of bits in the current mask.
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*
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* The MSB is the number of bits in the full mask because BIT[0] is
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* always 0.
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*
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* In the special 3 Rank interleaving case, a single bit is flipped
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* without swapping with the most significant bit. This can be handled
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* by keeping the MSB where it is and ignoring the single zero bit.
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*/
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msb = fls(addr_mask_orig) - 1;
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weight = hweight_long(addr_mask_orig);
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num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
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/* Take the number of zero bits off from the top of the mask. */
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addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1);
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edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
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edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig);
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edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);
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/* Register [31:1] = Address [39:9]. Size is in kBs here. */
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size = (addr_mask_deinterleaved >> 2) + 1;
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/* Return size in MBs. */
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return size >> 10;
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}
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static void read_dram_ctl_register(struct amd64_pvt *pvt)
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{
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@ -2813,59 +2813,35 @@ static struct amd64_family_type family_types[] = {
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[F17_CPUS] = {
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.ctl_name = "F17h",
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.max_mcs = 2,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F17_M10H_CPUS] = {
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.ctl_name = "F17h_M10h",
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.max_mcs = 2,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F17_M30H_CPUS] = {
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.ctl_name = "F17h_M30h",
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.max_mcs = 8,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F17_M60H_CPUS] = {
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.ctl_name = "F17h_M60h",
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.max_mcs = 2,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F17_M70H_CPUS] = {
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.ctl_name = "F17h_M70h",
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.max_mcs = 2,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F19_CPUS] = {
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.ctl_name = "F19h",
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.max_mcs = 8,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F19_M10H_CPUS] = {
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.ctl_name = "F19h_M10h",
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.max_mcs = 12,
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.flags.zn_regs_v2 = 1,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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[F19_M50H_CPUS] = {
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.ctl_name = "F19h_M50h",
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.max_mcs = 2,
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.ops = {
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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}
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},
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};
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@ -3414,7 +3390,7 @@ static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_or
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cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt);
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nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
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nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr);
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nr_pages <<= 20 - PAGE_SHIFT;
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edac_dbg(0, "csrow: %d, channel: %d, cs_mode %d\n",
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