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scsi: be2iscsi: Remove isr_lock and dead code
todo_mcc_cq is not needed as only MCC work is queued. todo_cq is not used at all. Rename functions to be consistent. Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Jitendra Bhivare
Martin K. Petersen
parent
1f5e847acb
commit
a309501619
3 changed files with 49 additions and 87 deletions
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@ -100,7 +100,7 @@ struct be_eq_obj {
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struct be_queue_info q;
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struct beiscsi_hba *phba;
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struct be_queue_info *cq;
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struct work_struct work_cqs; /* Work Item */
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struct work_struct mcc_work; /* Work Item */
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struct irq_poll iopoll;
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};
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@ -832,12 +832,11 @@ static void hwi_ring_eq_db(struct beiscsi_hba *phba,
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static irqreturn_t be_isr_mcc(int irq, void *dev_id)
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{
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struct beiscsi_hba *phba;
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struct be_eq_entry *eqe = NULL;
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struct be_eq_entry *eqe;
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struct be_queue_info *eq;
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struct be_queue_info *mcc;
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unsigned int num_eq_processed;
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unsigned int mcc_events;
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struct be_eq_obj *pbe_eq;
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unsigned long flags;
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pbe_eq = dev_id;
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eq = &pbe_eq->q;
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@ -845,27 +844,23 @@ static irqreturn_t be_isr_mcc(int irq, void *dev_id)
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mcc = &phba->ctrl.mcc_obj.cq;
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eqe = queue_tail_node(eq);
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num_eq_processed = 0;
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mcc_events = 0;
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while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
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& EQE_VALID_MASK) {
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if (((eqe->dw[offsetof(struct amap_eq_entry,
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resource_id) / 32] &
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EQE_RESID_MASK) >> 16) == mcc->id) {
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spin_lock_irqsave(&phba->isr_lock, flags);
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pbe_eq->todo_mcc_cq = true;
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spin_unlock_irqrestore(&phba->isr_lock, flags);
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mcc_events++;
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}
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AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
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queue_tail_inc(eq);
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eqe = queue_tail_node(eq);
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num_eq_processed++;
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}
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if (pbe_eq->todo_mcc_cq)
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queue_work(phba->wq, &pbe_eq->work_cqs);
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if (num_eq_processed)
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hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
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if (mcc_events) {
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queue_work(phba->wq, &pbe_eq->mcc_work);
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hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1);
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}
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return IRQ_HANDLED;
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}
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@ -884,7 +879,6 @@ static irqreturn_t be_isr_msix(int irq, void *dev_id)
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eq = &pbe_eq->q;
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phba = pbe_eq->phba;
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/* disable interrupt till iopoll completes */
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hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1);
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irq_poll_sched(&pbe_eq->iopoll);
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@ -902,14 +896,13 @@ static irqreturn_t be_isr(int irq, void *dev_id)
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struct beiscsi_hba *phba;
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struct hwi_controller *phwi_ctrlr;
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struct hwi_context_memory *phwi_context;
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struct be_eq_entry *eqe = NULL;
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struct be_eq_entry *eqe;
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struct be_queue_info *eq;
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struct be_queue_info *mcc;
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unsigned long flags, index;
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unsigned int num_mcceq_processed, num_ioeq_processed;
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unsigned int mcc_events, io_events;
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struct be_ctrl_info *ctrl;
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struct be_eq_obj *pbe_eq;
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int isr;
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int isr, rearm;
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phba = dev_id;
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ctrl = &phba->ctrl;
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@ -924,44 +917,35 @@ static irqreturn_t be_isr(int irq, void *dev_id)
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eq = &phwi_context->be_eq[0].q;
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mcc = &phba->ctrl.mcc_obj.cq;
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index = 0;
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eqe = queue_tail_node(eq);
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num_ioeq_processed = 0;
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num_mcceq_processed = 0;
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io_events = 0;
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mcc_events = 0;
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while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
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& EQE_VALID_MASK) {
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if (((eqe->dw[offsetof(struct amap_eq_entry,
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resource_id) / 32] &
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EQE_RESID_MASK) >> 16) == mcc->id) {
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spin_lock_irqsave(&phba->isr_lock, flags);
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pbe_eq->todo_mcc_cq = true;
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spin_unlock_irqrestore(&phba->isr_lock, flags);
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num_mcceq_processed++;
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} else {
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irq_poll_sched(&pbe_eq->iopoll);
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num_ioeq_processed++;
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}
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resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id)
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mcc_events++;
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else
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io_events++;
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AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
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queue_tail_inc(eq);
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eqe = queue_tail_node(eq);
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}
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if (num_ioeq_processed || num_mcceq_processed) {
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if (pbe_eq->todo_mcc_cq)
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queue_work(phba->wq, &pbe_eq->work_cqs);
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if ((num_mcceq_processed) && (!num_ioeq_processed))
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hwi_ring_eq_db(phba, eq->id, 0,
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(num_ioeq_processed +
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num_mcceq_processed) , 1, 1);
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else
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hwi_ring_eq_db(phba, eq->id, 0,
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(num_ioeq_processed +
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num_mcceq_processed), 0, 1);
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return IRQ_HANDLED;
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} else
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if (!io_events && !mcc_events)
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return IRQ_NONE;
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/* no need to rearm if interrupt is only for IOs */
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rearm = 0;
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if (mcc_events) {
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queue_work(phba->wq, &pbe_eq->mcc_work);
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/* rearm for MCCQ */
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rearm = 1;
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}
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if (io_events)
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irq_poll_sched(&pbe_eq->iopoll);
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hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1);
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return IRQ_HANDLED;
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}
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@ -2055,6 +2039,18 @@ void beiscsi_process_mcc_cq(struct beiscsi_hba *phba)
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hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1);
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}
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static void beiscsi_mcc_work(struct work_struct *work)
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{
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struct be_eq_obj *pbe_eq;
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struct beiscsi_hba *phba;
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pbe_eq = container_of(work, struct be_eq_obj, mcc_work);
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phba = pbe_eq->phba;
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beiscsi_process_mcc_cq(phba);
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/* rearm EQ for further interrupts */
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hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
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}
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/**
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* beiscsi_process_cq()- Process the Completion Queue
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* @pbe_eq: Event Q on which the Completion has come
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@ -2244,46 +2240,15 @@ unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget)
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return total;
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}
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void beiscsi_process_all_cqs(struct work_struct *work)
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{
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unsigned long flags;
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struct hwi_controller *phwi_ctrlr;
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struct hwi_context_memory *phwi_context;
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struct beiscsi_hba *phba;
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struct be_eq_obj *pbe_eq =
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container_of(work, struct be_eq_obj, work_cqs);
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phba = pbe_eq->phba;
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phwi_ctrlr = phba->phwi_ctrlr;
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phwi_context = phwi_ctrlr->phwi_ctxt;
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if (pbe_eq->todo_mcc_cq) {
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spin_lock_irqsave(&phba->isr_lock, flags);
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pbe_eq->todo_mcc_cq = false;
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spin_unlock_irqrestore(&phba->isr_lock, flags);
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beiscsi_process_mcc_cq(phba);
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}
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if (pbe_eq->todo_cq) {
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spin_lock_irqsave(&phba->isr_lock, flags);
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pbe_eq->todo_cq = false;
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spin_unlock_irqrestore(&phba->isr_lock, flags);
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beiscsi_process_cq(pbe_eq, BE2_MAX_NUM_CQ_PROC);
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}
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/* rearm EQ for further interrupts */
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hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
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}
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static int be_iopoll(struct irq_poll *iop, int budget)
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{
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unsigned int ret, num_eq_processed;
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unsigned int ret, io_events;
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struct beiscsi_hba *phba;
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struct be_eq_obj *pbe_eq;
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struct be_eq_entry *eqe = NULL;
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struct be_queue_info *eq;
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num_eq_processed = 0;
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io_events = 0;
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pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
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phba = pbe_eq->phba;
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eq = &pbe_eq->q;
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@ -2294,10 +2259,10 @@ static int be_iopoll(struct irq_poll *iop, int budget)
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AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
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queue_tail_inc(eq);
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eqe = queue_tail_node(eq);
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num_eq_processed++;
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io_events++;
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}
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hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
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hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1);
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ret = beiscsi_process_cq(pbe_eq, budget);
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pbe_eq->cq_count += ret;
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@ -5578,7 +5543,7 @@ static void beiscsi_eeh_resume(struct pci_dev *pdev)
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i = (phba->msix_enabled) ? i : 0;
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/* Work item for MCC handling */
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pbe_eq = &phwi_context->be_eq[i];
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INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
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INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
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ret = beiscsi_init_irqs(phba);
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if (ret < 0) {
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@ -5682,7 +5647,6 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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spin_lock_init(&phba->io_sgl_lock);
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spin_lock_init(&phba->mgmt_sgl_lock);
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spin_lock_init(&phba->isr_lock);
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spin_lock_init(&phba->async_pdu_lock);
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ret = mgmt_get_fw_config(&phba->ctrl, phba);
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if (ret != 0) {
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@ -5754,7 +5718,7 @@ static int beiscsi_dev_probe(struct pci_dev *pcidev,
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i = (phba->msix_enabled) ? i : 0;
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/* Work item for MCC handling */
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pbe_eq = &phwi_context->be_eq[i];
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INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
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INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work);
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ret = beiscsi_init_irqs(phba);
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if (ret < 0) {
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@ -378,7 +378,6 @@ struct beiscsi_hba {
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struct sgl_handle **eh_sgl_hndl_base;
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spinlock_t io_sgl_lock;
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spinlock_t mgmt_sgl_lock;
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spinlock_t isr_lock;
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spinlock_t async_pdu_lock;
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unsigned int age;
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struct list_head hba_queue;
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@ -845,7 +844,6 @@ struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
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void
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free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
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void beiscsi_process_all_cqs(struct work_struct *work);
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void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
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struct iscsi_task *task);
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