mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 05:48:40 +00:00
qxl, tegra, misc, amd, etnaviv fixes
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZzfQRAAoJEAx081l5xIa+LwcP/1OaYfNh1j8b+q5YFRhFXZbj 07mLvSw+HTS5+jSPlvV2meOLkabu3yawKk8PrdYRB684K6NWM0wzKwhZm8ZO6hrc px/Da3RV1o3a6Y91bh/Q94lJk0Oq9WSXyh4bVRlj2QnqtUN9vk+q3c2zssK7NWf6 1S9cyRVpObqR4qfa3V/2AnEbjoFWjDw44dSXRLquWaVfA+EDPgTpj1ZUGXPXluYo TEHlc2UvQBv7v2sFptcufpsM6LkqBXBz1Aca7We5iN6vKQqx7t63ih85fqaiZ9p9 ZpaB92l4tUMua2hOHI7sVj8OIBdwUE9x2e1AhtHRXP75OisVk+JMv+XbEFu7AHZH 1az9Qazt3neONM4R5sgFeXXP58uoysSoHBlFzqeHw9Pw8P2JQDqVNPlmpJGSh40x TVkmZZR3iqPNE2eUFiDhdArlTTU4417ZFSdWECyhH0IsTsNPj7PG2D2I1NonoqE4 qEX4qrnQpS6OUPIpHuIO/MhZ3lW/cO6ylneA7UwY6z0ocd4XT99zWpzaQxemu25U aSURa/P6J8KrscokDAkQGW2EA6YafLrBUtsbA/+eTgSLraDJiV2LOkJ3zkTSzZ67 lHXSbuv+B71RGRzZwK8ztF+DsgB0VSlw7ZnyAWXJp8cVup3z4f8xI2as41jAaEtA ODBAqwDECd7wtsVYfFrl =MHIa -----END PGP SIGNATURE----- Merge tag 'drm-fixes-for-v4.14-rc3' of git://people.freedesktop.org/~airlied/linux Pull drm fixes from Dave Airlie: "Regular fixes pull, some amdkfd, amdgpu, etnaviv, sun4i, qxl, tegra fixes. I've got an outstanding pull for i915 but it wasn't on an rc2 base so I wanted to ship these out first, I might get to it before rc3 or I might not" * tag 'drm-fixes-for-v4.14-rc3' of git://people.freedesktop.org/~airlied/linux: drm/tegra: trace: Fix path to include qxl: fix framebuffer unpinning drm/sun4i: cec: Enable back CEC-pin framework drm/amdkfd: Print event limit messages only once per process drm/amdkfd: Fix kernel-queue wrapping bugs drm/amdkfd: Fix incorrect destroy_mqd parameter drm/radeon: disable hard reset in hibernate for APUs drm/amdgpu: revert tile table update for oland etnaviv: fix gem object list corruption etnaviv: fix submit error path qxl: fix primary surface handling drm/amdkfd: check for null dev to avoid a null pointer dereference
This commit is contained in:
commit
a3583202e8
12 changed files with 246 additions and 31 deletions
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@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
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NUM_BANKS(ADDR_SURF_2_BANK);
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
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WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
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} else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) {
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} else if (adev->asic_type == CHIP_OLAND) {
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tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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TILE_SPLIT(split_equal_to_row_size) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
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tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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NUM_BANKS(ADDR_SURF_16_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
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tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
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NUM_BANKS(ADDR_SURF_8_BANK) |
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BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
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WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
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} else if (adev->asic_type == CHIP_HAINAN) {
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tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
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ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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@ -892,6 +892,8 @@ static int kfd_ioctl_get_tile_config(struct file *filep,
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int err = 0;
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dev = kfd_device_by_id(args->gpu_id);
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if (!dev)
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return -EINVAL;
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dev->kfd2kgd->get_tile_config(dev->kgd, &config);
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@ -292,7 +292,10 @@ static int create_signal_event(struct file *devkfd,
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struct kfd_event *ev)
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{
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if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) {
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pr_warn("Signal event wasn't created because limit was reached\n");
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if (!p->signal_event_limit_reached) {
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pr_warn("Signal event wasn't created because limit was reached\n");
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p->signal_event_limit_reached = true;
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}
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return -ENOMEM;
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}
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@ -184,7 +184,7 @@ static void uninitialize(struct kernel_queue *kq)
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if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
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kq->mqd->destroy_mqd(kq->mqd,
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kq->queue->mqd,
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false,
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KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
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QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
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kq->queue->pipe,
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kq->queue->queue);
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@ -210,6 +210,11 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
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uint32_t wptr, rptr;
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unsigned int *queue_address;
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/* When rptr == wptr, the buffer is empty.
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* When rptr == wptr + 1, the buffer is full.
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* It is always rptr that advances to the position of wptr, rather than
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* the opposite. So we can only use up to queue_size_dwords - 1 dwords.
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*/
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rptr = *kq->rptr_kernel;
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wptr = *kq->wptr_kernel;
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queue_address = (unsigned int *)kq->pq_kernel_addr;
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@ -219,11 +224,10 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
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pr_debug("wptr: %d\n", wptr);
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pr_debug("queue_address 0x%p\n", queue_address);
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available_size = (rptr - 1 - wptr + queue_size_dwords) %
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available_size = (rptr + queue_size_dwords - 1 - wptr) %
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queue_size_dwords;
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if (packet_size_in_dwords >= queue_size_dwords ||
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packet_size_in_dwords >= available_size) {
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if (packet_size_in_dwords > available_size) {
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/*
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* make sure calling functions know
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* acquire_packet_buffer() failed
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@ -233,6 +237,14 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
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}
|
||||
|
||||
if (wptr + packet_size_in_dwords >= queue_size_dwords) {
|
||||
/* make sure after rolling back to position 0, there is
|
||||
* still enough space.
|
||||
*/
|
||||
if (packet_size_in_dwords >= rptr) {
|
||||
*buffer_ptr = NULL;
|
||||
return -ENOMEM;
|
||||
}
|
||||
/* fill nops, roll back and start at position 0 */
|
||||
while (wptr > 0) {
|
||||
queue_address[wptr] = kq->nop_packet;
|
||||
wptr = (wptr + 1) % queue_size_dwords;
|
||||
|
|
|
@ -521,6 +521,7 @@ struct kfd_process {
|
|||
struct list_head signal_event_pages;
|
||||
u32 next_nonsignal_event_id;
|
||||
size_t signal_event_count;
|
||||
bool signal_event_limit_reached;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -551,12 +551,15 @@ static const struct etnaviv_gem_ops etnaviv_gem_shmem_ops = {
|
|||
void etnaviv_gem_free_object(struct drm_gem_object *obj)
|
||||
{
|
||||
struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);
|
||||
struct etnaviv_drm_private *priv = obj->dev->dev_private;
|
||||
struct etnaviv_vram_mapping *mapping, *tmp;
|
||||
|
||||
/* object should not be active */
|
||||
WARN_ON(is_active(etnaviv_obj));
|
||||
|
||||
mutex_lock(&priv->gem_lock);
|
||||
list_del(&etnaviv_obj->gem_node);
|
||||
mutex_unlock(&priv->gem_lock);
|
||||
|
||||
list_for_each_entry_safe(mapping, tmp, &etnaviv_obj->vram_list,
|
||||
obj_node) {
|
||||
|
|
|
@ -445,8 +445,10 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
|
|||
cmdbuf->user_size = ALIGN(args->stream_size, 8);
|
||||
|
||||
ret = etnaviv_gpu_submit(gpu, submit, cmdbuf);
|
||||
if (ret == 0)
|
||||
cmdbuf = NULL;
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
cmdbuf = NULL;
|
||||
|
||||
if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) {
|
||||
/*
|
||||
|
|
|
@ -509,23 +509,25 @@ static void qxl_primary_atomic_update(struct drm_plane *plane,
|
|||
.y2 = qfb->base.height
|
||||
};
|
||||
|
||||
if (!old_state->fb) {
|
||||
qxl_io_log(qdev,
|
||||
"create primary fb: %dx%d,%d,%d\n",
|
||||
bo->surf.width, bo->surf.height,
|
||||
bo->surf.stride, bo->surf.format);
|
||||
|
||||
qxl_io_create_primary(qdev, 0, bo);
|
||||
bo->is_primary = true;
|
||||
return;
|
||||
|
||||
} else {
|
||||
if (old_state->fb) {
|
||||
qfb_old = to_qxl_framebuffer(old_state->fb);
|
||||
bo_old = gem_to_qxl_bo(qfb_old->obj);
|
||||
} else {
|
||||
bo_old = NULL;
|
||||
}
|
||||
|
||||
if (bo == bo_old)
|
||||
return;
|
||||
|
||||
if (bo_old && bo_old->is_primary) {
|
||||
qxl_io_destroy_primary(qdev);
|
||||
bo_old->is_primary = false;
|
||||
}
|
||||
|
||||
bo->is_primary = true;
|
||||
if (!bo->is_primary) {
|
||||
qxl_io_create_primary(qdev, 0, bo);
|
||||
bo->is_primary = true;
|
||||
}
|
||||
qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1);
|
||||
}
|
||||
|
||||
|
@ -534,13 +536,15 @@ static void qxl_primary_atomic_disable(struct drm_plane *plane,
|
|||
{
|
||||
struct qxl_device *qdev = plane->dev->dev_private;
|
||||
|
||||
if (old_state->fb)
|
||||
{ struct qxl_framebuffer *qfb =
|
||||
if (old_state->fb) {
|
||||
struct qxl_framebuffer *qfb =
|
||||
to_qxl_framebuffer(old_state->fb);
|
||||
struct qxl_bo *bo = gem_to_qxl_bo(qfb->obj);
|
||||
|
||||
qxl_io_destroy_primary(qdev);
|
||||
bo->is_primary = false;
|
||||
if (bo->is_primary) {
|
||||
qxl_io_destroy_primary(qdev);
|
||||
bo->is_primary = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -698,14 +702,15 @@ static void qxl_plane_cleanup_fb(struct drm_plane *plane,
|
|||
struct drm_gem_object *obj;
|
||||
struct qxl_bo *user_bo;
|
||||
|
||||
if (!plane->state->fb) {
|
||||
/* we never executed prepare_fb, so there's nothing to
|
||||
if (!old_state->fb) {
|
||||
/*
|
||||
* we never executed prepare_fb, so there's nothing to
|
||||
* unpin.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
obj = to_qxl_framebuffer(plane->state->fb)->obj;
|
||||
obj = to_qxl_framebuffer(old_state->fb)->obj;
|
||||
user_bo = gem_to_qxl_bo(obj);
|
||||
qxl_bo_unpin(user_bo);
|
||||
}
|
||||
|
|
|
@ -1663,7 +1663,7 @@ int radeon_suspend_kms(struct drm_device *dev, bool suspend,
|
|||
radeon_agp_suspend(rdev);
|
||||
|
||||
pci_save_state(dev->pdev);
|
||||
if (freeze && rdev->family >= CHIP_CEDAR) {
|
||||
if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
|
||||
rdev->asic->asic_reset(rdev, true);
|
||||
pci_restore_state(dev->pdev);
|
||||
} else if (suspend) {
|
||||
|
|
|
@ -26,7 +26,7 @@ config DRM_SUN4I_HDMI_CEC
|
|||
bool "Allwinner A10 HDMI CEC Support"
|
||||
depends on DRM_SUN4I_HDMI
|
||||
select CEC_CORE
|
||||
depends on CEC_PIN
|
||||
select CEC_PIN
|
||||
help
|
||||
Choose this option if you have an Allwinner SoC with an HDMI
|
||||
controller and want to use CEC.
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
#include <drm/drm_connector.h>
|
||||
#include <drm/drm_encoder.h>
|
||||
|
||||
#include <media/cec.h>
|
||||
#include <media/cec-pin.h>
|
||||
|
||||
#define SUN4I_HDMI_CTRL_REG 0x004
|
||||
#define SUN4I_HDMI_CTRL_ENABLE BIT(31)
|
||||
|
|
|
@ -63,6 +63,6 @@ DEFINE_EVENT(register_access, sor_readl,
|
|||
|
||||
/* This part must be outside protection */
|
||||
#undef TRACE_INCLUDE_PATH
|
||||
#define TRACE_INCLUDE_PATH .
|
||||
#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/tegra
|
||||
#define TRACE_INCLUDE_FILE trace
|
||||
#include <trace/define_trace.h>
|
||||
|
|
Loading…
Reference in a new issue