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net: phy: bcm7xxx: define constants for our registers
Define constants for the various registers used in bcm7xxx_28nm_afe_config_init() to help clarify what this workaround is about. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 27 additions and 11 deletions
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@ -28,6 +28,22 @@
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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/* 28nm only register definitions */
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#define MISC_ADDR(base, channel) base, channel
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#define DSP_TAP10 MISC_ADDR(0x0a, 0)
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#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
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#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
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#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
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#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
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#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
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#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
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#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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#define CORE_EXPB0 0xb0
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static int bcm7445_config_init(struct phy_device *phydev)
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{
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int ret;
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@ -88,44 +104,44 @@ static void phy_write_misc(struct phy_device *phydev,
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static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
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{
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/* write AFE_RXCONFIG_0 */
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phy_write_misc(phydev, 0x38, 0x0000, 0xeb19);
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phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
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/* write AFE_RXCONFIG_1 */
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phy_write_misc(phydev, 0x38, 0x0001, 0x9a3f);
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phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
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/* write AFE_RX_LP_COUNTER */
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phy_write_misc(phydev, 0x38, 0x0003, 0x7fc7);
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phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc7);
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/* write AFE_HPF_TRIM_OTHERS */
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phy_write_misc(phydev, 0x3A, 0x0000, 0x000b);
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phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
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/* write AFTE_TX_CONFIG */
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phy_write_misc(phydev, 0x39, 0x0000, 0x0800);
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phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
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/* Increase VCO range to prevent unlocking problem of PLL at low
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* temp
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*/
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phy_write_misc(phydev, 0x0032, 0x0001, 0x0048);
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phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
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/* Change Ki to 011 */
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phy_write_misc(phydev, 0x0032, 0x0002, 0x021b);
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phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
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/* Disable loading of TVCO buffer to bandgap, set bandgap trim
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* to 111
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*/
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phy_write_misc(phydev, 0x0033, 0x0000, 0x0e20);
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phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
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/* Adjust bias current trim by -3 */
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phy_write_misc(phydev, 0x000a, 0x0000, 0x690b);
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phy_write_misc(phydev, DSP_TAP10, 0x690b);
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/* Switch to CORE_BASE1E */
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phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
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/* Reset R_CAL/RC_CAL Engine */
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phy_write_exp(phydev, 0x00b0, 0x0010);
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phy_write_exp(phydev, CORE_EXPB0, 0x0010);
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/* Disable Reset R_CAL/RC_CAL Engine */
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phy_write_exp(phydev, 0x00b0, 0x0000);
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phy_write_exp(phydev, CORE_EXPB0, 0x0000);
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return 0;
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}
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