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drm/amd/pm: update SMU13 header files for coming OD support

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Correct the data structures for OD feature support.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2023-04-11 11:25:52 +08:00 committed by Alex Deucher
parent 50cff45e27
commit a37d23f816
4 changed files with 34 additions and 45 deletions
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16
drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h
View file

@ -38,13 +38,12 @@
#define SMU_13_0_0_PP_THERMALCONTROLLER_NONE 0
#define SMU_13_0_0_PP_THERMALCONTROLLER_NAVI21 28
#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x81 // OverDrive 8 Table Version 0.2
#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8 Table Version 0.2
#define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00
enum SMU_13_0_0_ODFEATURE_CAP
{
SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_0_ODCAP_GFXCLK_CURVE,
SMU_13_0_0_ODCAP_UCLK_LIMITS,
SMU_13_0_0_ODCAP_POWER_LIMIT,
SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,
@ -59,13 +58,13 @@ enum SMU_13_0_0_ODFEATURE_CAP
SMU_13_0_0_ODCAP_FAN_CURVE,
SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
SMU_13_0_0_ODCAP_POWER_MODE,
SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET,
SMU_13_0_0_ODCAP_COUNT,
};
enum SMU_13_0_0_ODFEATURE_ID
{
SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_13_0_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_13_0_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature
SMU_13_0_0_ODFEATURE_UCLK_LIMITS = 1 << SMU_13_0_0_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_0_ODFEATURE_POWER_LIMIT = 1 << SMU_13_0_0_ODCAP_POWER_LIMIT, //Power Limit feature
SMU_13_0_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature
@ -80,6 +79,7 @@ enum SMU_13_0_0_ODFEATURE_ID
SMU_13_0_0_ODFEATURE_FAN_CURVE = 1 << SMU_13_0_0_ODCAP_FAN_CURVE, //Fan Curve feature
SMU_13_0_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature
SMU_13_0_0_ODFEATURE_POWER_MODE = 1 << SMU_13_0_0_ODCAP_POWER_MODE, //Optimized GPU Power Mode feature
SMU_13_0_0_ODFEATURE_PER_ZONE_GFX_VOLTAGE_OFFSET = 1 << SMU_13_0_0_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET, //Perzone voltage offset feature
SMU_13_0_0_ODFEATURE_COUNT = 16,
};
@ -89,10 +89,6 @@ enum SMU_13_0_0_ODSETTING_ID
{
SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_0_ODSETTING_GFXCLKFMIN,
SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_A,
SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_B,
SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_C,
SMU_13_0_0_ODSETTING_CUSTOM_CURVE_VFT_FMIN,
SMU_13_0_0_ODSETTING_UCLKFMIN,
SMU_13_0_0_ODSETTING_UCLKFMAX,
SMU_13_0_0_ODSETTING_POWERPERCENTAGE,
@ -117,6 +113,12 @@ enum SMU_13_0_0_ODSETTING_ID
SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5,
SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT,
SMU_13_0_0_ODSETTING_POWER_MODE,
SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1,
SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2,
SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3,
SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4,
SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5,
SMU_13_0_0_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6,
SMU_13_0_0_ODSETTING_COUNT,
};
#define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings

18
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
View file

@ -667,7 +667,14 @@ typedef enum {
#define PP_NUM_RTAVFS_PWL_ZONES 5
#define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0
#define PP_OD_FEATURE_PPT_BIT 2
#define PP_OD_FEATURE_FAN_CURVE_BIT 3
#define PP_OD_FEATURE_GFXCLK_BIT 7
#define PP_OD_FEATURE_UCLK_BIT 8
#define PP_OD_FEATURE_ZERO_FAN_BIT 9
#define PP_OD_FEATURE_TEMPERATURE_BIT 10
#define PP_OD_FEATURE_COUNT 13
// VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3
// Slope Q1.7, Offset Q1.2
@ -689,10 +696,8 @@ typedef struct {
//Voltage control
int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
uint16_t VddGfxVmax; // in mV
uint8_t IdlePwrSavingFeaturesCtrl;
uint8_t RuntimePwrSavingFeaturesCtrl;
uint32_t Reserved;
//Frequency changes
int16_t GfxclkFmin; // MHz
@ -729,10 +734,9 @@ typedef struct {
uint32_t FeatureCtrlMask;
int16_t VoltageOffsetPerZoneBoundary;
uint16_t VddGfxVmax; // in mV
uint16_t Reserved1;
uint8_t IdlePwrSavingFeaturesCtrl;
uint8_t RuntimePwrSavingFeaturesCtrl;
uint16_t Reserved2;
int16_t GfxclkFmin; // MHz
int16_t GfxclkFmax; // MHz

29
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h
View file

@ -683,18 +683,12 @@ typedef struct {
#define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0
#define PP_OD_FEATURE_VMAX_BIT 1
#define PP_OD_FEATURE_PPT_BIT 2
#define PP_OD_FEATURE_FAN_CURVE_BIT 3
#define PP_OD_FEATURE_FREQ_DETER_BIT 4
#define PP_OD_FEATURE_FULL_CTRL_BIT 5
#define PP_OD_FEATURE_TDC_BIT 6
#define PP_OD_FEATURE_GFXCLK_BIT 7
#define PP_OD_FEATURE_UCLK_BIT 8
#define PP_OD_FEATURE_ZERO_FAN_BIT 9
#define PP_OD_FEATURE_TEMPERATURE_BIT 10
#define PP_OD_FEATURE_POWER_FEATURE_CTRL_BIT 11
#define PP_OD_FEATURE_ASIC_TDC_BIT 12
#define PP_OD_FEATURE_COUNT 13
typedef enum {
@ -713,10 +707,8 @@ typedef struct {
//Voltage control
int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
uint16_t VddGfxVmax; // in mV
uint8_t IdlePwrSavingFeaturesCtrl;
uint8_t RuntimePwrSavingFeaturesCtrl;
uint32_t Reserved;
//Frequency changes
int16_t GfxclkFmin; // MHz
@ -741,12 +733,7 @@ typedef struct {
uint8_t MaxOpTemp;
uint8_t Padding[4];
uint16_t GfxVoltageFullCtrlMode;
uint16_t GfxclkFullCtrlMode;
uint16_t UclkFullCtrlMode;
int16_t AsicTdc;
uint32_t Spare[10];
uint32_t Spare[12];
uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround
} OverDriveTable_t;
@ -759,10 +746,9 @@ typedef struct {
uint32_t FeatureCtrlMask;
int16_t VoltageOffsetPerZoneBoundary;
uint16_t VddGfxVmax; // in mV
uint16_t Reserved1;
uint8_t IdlePwrSavingFeaturesCtrl;
uint8_t RuntimePwrSavingFeaturesCtrl;
uint16_t Reserved2;
int16_t GfxclkFmin; // MHz
int16_t GfxclkFmax; // MHz
@ -785,12 +771,7 @@ typedef struct {
uint8_t MaxOpTemp;
uint8_t Padding[4];
uint16_t GfxVoltageFullCtrlMode;
uint16_t GfxclkFullCtrlMode;
uint16_t UclkFullCtrlMode;
int16_t AsicTdc;
uint32_t Spare[10];
uint32_t Spare[12];
} OverDriveLimits_t;

16
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
View file

@ -38,13 +38,12 @@
#define SMU_13_0_7_PP_THERMALCONTROLLER_NONE 0
#define SMU_13_0_7_PP_THERMALCONTROLLER_NAVI21 28
#define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x81 // OverDrive 8 Table Version 0.2
#define SMU_13_0_7_PP_OVERDRIVE_VERSION 0x83 // OverDrive 8 Table Version 0.2
#define SMU_13_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00
enum SMU_13_0_7_ODFEATURE_CAP
{
SMU_13_0_7_ODCAP_GFXCLK_LIMITS = 0,
SMU_13_0_7_ODCAP_GFXCLK_CURVE,
SMU_13_0_7_ODCAP_UCLK_LIMITS,
SMU_13_0_7_ODCAP_POWER_LIMIT,
SMU_13_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
@ -59,13 +58,13 @@ enum SMU_13_0_7_ODFEATURE_CAP
SMU_13_0_7_ODCAP_FAN_CURVE,
SMU_13_0_7_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
SMU_13_0_7_ODCAP_POWER_MODE,
SMU_13_0_7_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET,
SMU_13_0_7_ODCAP_COUNT,
};
enum SMU_13_0_7_ODFEATURE_ID
{
SMU_13_0_7_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_13_0_7_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
SMU_13_0_7_ODFEATURE_GFXCLK_CURVE = 1 << SMU_13_0_7_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature
SMU_13_0_7_ODFEATURE_UCLK_LIMITS = 1 << SMU_13_0_7_ODCAP_UCLK_LIMITS, //UCLK Limit feature
SMU_13_0_7_ODFEATURE_POWER_LIMIT = 1 << SMU_13_0_7_ODCAP_POWER_LIMIT, //Power Limit feature
SMU_13_0_7_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature
@ -80,6 +79,7 @@ enum SMU_13_0_7_ODFEATURE_ID
SMU_13_0_7_ODFEATURE_FAN_CURVE = 1 << SMU_13_0_7_ODCAP_FAN_CURVE, //Fan Curve feature
SMU_13_0_7_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_7_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature
SMU_13_0_7_ODFEATURE_POWER_MODE = 1 << SMU_13_0_7_ODCAP_POWER_MODE, //Optimized GPU Power Mode feature
SMU_13_0_7_ODFEATURE_PER_ZONE_GFX_VOLTAGE_OFFSET = 1 << SMU_13_0_7_ODCAP_PER_ZONE_GFX_VOLTAGE_OFFSET, //Perzone voltage offset feature
SMU_13_0_7_ODFEATURE_COUNT = 16,
};
@ -89,10 +89,6 @@ enum SMU_13_0_7_ODSETTING_ID
{
SMU_13_0_7_ODSETTING_GFXCLKFMAX = 0,
SMU_13_0_7_ODSETTING_GFXCLKFMIN,
SMU_13_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_A,
SMU_13_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_B,
SMU_13_0_7_ODSETTING_CUSTOM_GFX_VF_CURVE_C,
SMU_13_0_7_ODSETTING_CUSTOM_CURVE_VFT_FMIN,
SMU_13_0_7_ODSETTING_UCLKFMIN,
SMU_13_0_7_ODSETTING_UCLKFMAX,
SMU_13_0_7_ODSETTING_POWERPERCENTAGE,
@ -117,6 +113,12 @@ enum SMU_13_0_7_ODSETTING_ID
SMU_13_0_7_ODSETTING_FAN_CURVE_SPEED_5,
SMU_13_0_7_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT,
SMU_13_0_7_ODSETTING_POWER_MODE,
SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_1,
SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_2,
SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_3,
SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_4,
SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_5,
SMU_13_0_7_ODSETTING_PER_ZONE_GFX_VOLTAGE_OFFSET_POINT_6,
SMU_13_0_7_ODSETTING_COUNT,
};
#define SMU_13_0_7_MAX_ODSETTING 64 //Maximum Number of ODSettings