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RISC-V: Use WRITE_ONCE instead of direct access

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The secondary harts spin on couple of per cpu variables until both of
these are non-zero so it's not necessary to have any ordering here.
However, WRITE_ONCE should be used to avoid tearing.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Atish Patra 2018-10-02 12:15:03 -07:00 committed by Palmer Dabbelt
parent 46373cb442
commit a37d56fc40
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GPG key ID: EF4CA1502CCBAB41
1 changed files with 3 additions and 2 deletions
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5
arch/riscv/kernel/smpboot.c
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@ -81,8 +81,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
* the spinning harts that they can continue the boot process.
*/
smp_mb();
__cpu_up_stack_pointer[cpu] = task_stack_page(tidle) + THREAD_SIZE;
__cpu_up_task_pointer[cpu] = tidle;
WRITE_ONCE(__cpu_up_stack_pointer[cpu],
task_stack_page(tidle) + THREAD_SIZE);
WRITE_ONCE(__cpu_up_task_pointer[cpu], tidle);
while (!cpu_online(cpu))
cpu_relax();