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PCI: fu740: Force 2.5GT/s for initial device probe
The fu740 PCIe core does not probe any devices on the SiFive Unmatched board without this fix (or having U-Boot explicitly start the PCIe via either boot-script or user command). The fix is to start the link at 2.5GT/s speeds and once the link is up then change the maximum speed back to the default. The U-Boot driver claims to set the link-speed to 2.5GT/s to get the probe to work (and U-Boot does print link up at 2.5GT/s) in the following code: https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/pci/pcie_dw_sifive.c?id=v2022.01#L271 Link: https://lore.kernel.org/r/20220318152430.526320-1-ben.dooks@codethink.co.uk Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
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1 changed files with 50 additions and 1 deletions
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@ -181,10 +181,59 @@ static int fu740_pcie_start_link(struct dw_pcie *pci)
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{
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struct device *dev = pci->dev;
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struct fu740_pcie *afp = dev_get_drvdata(dev);
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u8 cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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int ret;
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u32 orig, tmp;
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/*
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* Force 2.5GT/s when starting the link, due to some devices not
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* probing at higher speeds. This happens with the PCIe switch
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* on the Unmatched board when U-Boot has not initialised the PCIe.
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* The fix in U-Boot is to force 2.5GT/s, which then gets cleared
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* by the soft reset done by this driver.
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*/
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dev_dbg(dev, "cap_exp at %x\n", cap_exp);
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dw_pcie_dbi_ro_wr_en(pci);
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tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
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orig = tmp & PCI_EXP_LNKCAP_SLS;
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tmp &= ~PCI_EXP_LNKCAP_SLS;
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tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
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dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
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/* Enable LTSSM */
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writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
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return 0;
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ret = dw_pcie_wait_for_link(pci);
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if (ret) {
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dev_err(dev, "error: link did not start\n");
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goto err;
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}
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tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
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if ((tmp & PCI_EXP_LNKCAP_SLS) != orig) {
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dev_dbg(dev, "changing speed back to original\n");
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tmp &= ~PCI_EXP_LNKCAP_SLS;
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tmp |= orig;
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dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
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tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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tmp |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
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ret = dw_pcie_wait_for_link(pci);
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if (ret) {
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dev_err(dev, "error: link did not start at new speed\n");
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goto err;
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}
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}
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ret = 0;
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err:
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WARN_ON(ret); /* we assume that errors will be very rare */
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dw_pcie_dbi_ro_wr_dis(pci);
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return ret;
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}
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static int fu740_pcie_host_init(struct pcie_port *pp)
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