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PCI: fu740: Force 2.5GT/s for initial device probe

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The fu740 PCIe core does not probe any devices on the SiFive Unmatched
board without this fix (or having U-Boot explicitly start the PCIe via
either boot-script or user command). The fix is to start the link at
2.5GT/s speeds and once the link is up then change the maximum speed back
to the default.

The U-Boot driver claims to set the link-speed to 2.5GT/s to get the probe
to work (and U-Boot does print link up at 2.5GT/s) in the following code:
https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/pci/pcie_dw_sifive.c?id=v2022.01#L271

Link: https://lore.kernel.org/r/20220318152430.526320-1-ben.dooks@codethink.co.uk
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Ben Dooks 2022-03-18 15:24:30 +00:00 committed by Bjorn Helgaas
parent cf18fce4ed
commit a382c757ec
1 changed files with 50 additions and 1 deletions
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51
drivers/pci/controller/dwc/pcie-fu740.c
View file

@ -181,10 +181,59 @@ static int fu740_pcie_start_link(struct dw_pcie *pci)
{
struct device *dev = pci->dev;
struct fu740_pcie *afp = dev_get_drvdata(dev);
u8 cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
int ret;
u32 orig, tmp;
/*
* Force 2.5GT/s when starting the link, due to some devices not
* probing at higher speeds. This happens with the PCIe switch
* on the Unmatched board when U-Boot has not initialised the PCIe.
* The fix in U-Boot is to force 2.5GT/s, which then gets cleared
* by the soft reset done by this driver.
*/
dev_dbg(dev, "cap_exp at %x\n", cap_exp);
dw_pcie_dbi_ro_wr_en(pci);
tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
orig = tmp & PCI_EXP_LNKCAP_SLS;
tmp &= ~PCI_EXP_LNKCAP_SLS;
tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
/* Enable LTSSM */
writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
return 0;
ret = dw_pcie_wait_for_link(pci);
if (ret) {
dev_err(dev, "error: link did not start\n");
goto err;
}
tmp = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCAP);
if ((tmp & PCI_EXP_LNKCAP_SLS) != orig) {
dev_dbg(dev, "changing speed back to original\n");
tmp &= ~PCI_EXP_LNKCAP_SLS;
tmp |= orig;
dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp);
tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
tmp |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
ret = dw_pcie_wait_for_link(pci);
if (ret) {
dev_err(dev, "error: link did not start at new speed\n");
goto err;
}
}
ret = 0;
err:
WARN_ON(ret); /* we assume that errors will be very rare */
dw_pcie_dbi_ro_wr_dis(pci);
return ret;
}
static int fu740_pcie_host_init(struct pcie_port *pp)