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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
Merge branch 'topic/ppc-kvm' into next
Merge some powerpc KVM patches we are keeping in a topic branch just in case anyone else needs to merge them.
This commit is contained in:
commit
a38cb41719
7 changed files with 109 additions and 39 deletions
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@ -258,6 +258,8 @@ extern long kvmppc_hv_get_dirty_log_hpt(struct kvm *kvm,
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extern void kvmppc_harvest_vpa_dirty(struct kvmppc_vpa *vpa,
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struct kvm_memory_slot *memslot,
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unsigned long *map);
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extern unsigned long kvmppc_filter_lpcr_hv(struct kvm *kvm,
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unsigned long lpcr);
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extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr,
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unsigned long mask);
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extern void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr);
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@ -767,8 +767,7 @@ long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn);
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long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu);
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long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va);
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unsigned long pte_index, unsigned long avpn);
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long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index);
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long kvmppc_h_clear_ref(struct kvm_vcpu *vcpu, unsigned long flags,
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@ -2503,8 +2503,6 @@ EXC_VIRT_NONE(0x5100, 0x100)
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INT_DEFINE_BEGIN(cbe_system_error)
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IVEC=0x1200
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IHSRR=1
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IKVM_SKIP=1
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IKVM_REAL=1
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INT_DEFINE_END(cbe_system_error)
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EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
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@ -2524,11 +2522,16 @@ EXC_REAL_NONE(0x1200, 0x100)
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EXC_VIRT_NONE(0x5200, 0x100)
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#endif
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/**
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* Interrupt 0x1300 - Instruction Address Breakpoint Interrupt.
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* This has been removed from the ISA before 2.01, which is the earliest
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* 64-bit BookS ISA supported, however the G5 / 970 implements this
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* interrupt with a non-architected feature available through the support
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* processor interface.
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*/
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INT_DEFINE_BEGIN(instruction_breakpoint)
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IVEC=0x1300
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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IKVM_SKIP=1
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IKVM_REAL=1
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#endif
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INT_DEFINE_END(instruction_breakpoint)
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@ -2674,8 +2677,6 @@ EXC_COMMON_BEGIN(denorm_exception_common)
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INT_DEFINE_BEGIN(cbe_maintenance)
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IVEC=0x1600
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IHSRR=1
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IKVM_SKIP=1
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IKVM_REAL=1
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INT_DEFINE_END(cbe_maintenance)
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EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
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@ -2727,8 +2728,6 @@ EXC_COMMON_BEGIN(altivec_assist_common)
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INT_DEFINE_BEGIN(cbe_thermal)
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IVEC=0x1800
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IHSRR=1
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IKVM_SKIP=1
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IKVM_REAL=1
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INT_DEFINE_END(cbe_thermal)
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EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
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@ -803,7 +803,10 @@ static int kvmppc_h_set_mode(struct kvm_vcpu *vcpu, unsigned long mflags,
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vcpu->arch.dawrx1 = value2;
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return H_SUCCESS;
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case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
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/* KVM does not support mflags=2 (AIL=2) */
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/*
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* KVM does not support mflags=2 (AIL=2) and AIL=1 is reserved.
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* Keep this in synch with kvmppc_filter_guest_lpcr_hv.
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*/
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if (mflags != 0 && mflags != 3)
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return H_UNSUPPORTED_FLAG_START;
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return H_TOO_HARD;
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@ -1635,6 +1638,41 @@ static int kvm_arch_vcpu_ioctl_set_sregs_hv(struct kvm_vcpu *vcpu,
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return 0;
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}
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/*
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* Enforce limits on guest LPCR values based on hardware availability,
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* guest configuration, and possibly hypervisor support and security
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* concerns.
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*/
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unsigned long kvmppc_filter_lpcr_hv(struct kvm *kvm, unsigned long lpcr)
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{
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/* LPCR_TC only applies to HPT guests */
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if (kvm_is_radix(kvm))
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lpcr &= ~LPCR_TC;
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/* On POWER8 and above, userspace can modify AIL */
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if (!cpu_has_feature(CPU_FTR_ARCH_207S))
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lpcr &= ~LPCR_AIL;
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if ((lpcr & LPCR_AIL) != LPCR_AIL_3)
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lpcr &= ~LPCR_AIL; /* LPCR[AIL]=1/2 is disallowed */
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/*
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* On POWER9, allow userspace to enable large decrementer for the
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* guest, whether or not the host has it enabled.
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*/
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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lpcr &= ~LPCR_LD;
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return lpcr;
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}
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static void verify_lpcr(struct kvm *kvm, unsigned long lpcr)
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{
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if (lpcr != kvmppc_filter_lpcr_hv(kvm, lpcr)) {
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WARN_ONCE(1, "lpcr 0x%lx differs from filtered 0x%lx\n",
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lpcr, kvmppc_filter_lpcr_hv(kvm, lpcr));
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}
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}
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static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr,
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bool preserve_top32)
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{
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@ -1643,6 +1681,23 @@ static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr,
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u64 mask;
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spin_lock(&vc->lock);
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/*
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* Userspace can only modify
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* DPFD (default prefetch depth), ILE (interrupt little-endian),
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* TC (translation control), AIL (alternate interrupt location),
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* LD (large decrementer).
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* These are subject to restrictions from kvmppc_filter_lcpr_hv().
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*/
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mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD;
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/* Broken 32-bit version of LPCR must not clear top bits */
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if (preserve_top32)
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mask &= 0xFFFFFFFF;
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new_lpcr = kvmppc_filter_lpcr_hv(kvm,
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(vc->lpcr & ~mask) | (new_lpcr & mask));
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/*
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* If ILE (interrupt little-endian) has changed, update the
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* MSR_LE bit in the intr_msr for each vcpu in this vcore.
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@ -1661,25 +1716,8 @@ static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr,
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}
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}
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/*
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* Userspace can only modify DPFD (default prefetch depth),
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* ILE (interrupt little-endian) and TC (translation control).
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* On POWER8 and POWER9 userspace can also modify AIL (alt. interrupt loc.).
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*/
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mask = LPCR_DPFD | LPCR_ILE | LPCR_TC;
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if (cpu_has_feature(CPU_FTR_ARCH_207S))
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mask |= LPCR_AIL;
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/*
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* On POWER9, allow userspace to enable large decrementer for the
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* guest, whether or not the host has it enabled.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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mask |= LPCR_LD;
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vc->lpcr = new_lpcr;
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/* Broken 32-bit version of LPCR must not clear top bits */
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if (preserve_top32)
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mask &= 0xFFFFFFFF;
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vc->lpcr = (vc->lpcr & ~mask) | (new_lpcr & mask);
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spin_unlock(&vc->lock);
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}
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@ -3728,7 +3766,10 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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vcpu->arch.dec_expires = dec + tb;
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vcpu->cpu = -1;
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vcpu->arch.thread_cpu = -1;
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/* Save guest CTRL register, set runlatch to 1 */
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vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
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if (!(vcpu->arch.ctrl & 1))
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mtspr(SPRN_CTRLT, vcpu->arch.ctrl | 1);
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vcpu->arch.iamr = mfspr(SPRN_IAMR);
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vcpu->arch.pspb = mfspr(SPRN_PSPB);
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@ -3749,7 +3790,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
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mtspr(SPRN_DSCR, host_dscr);
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mtspr(SPRN_TIDR, host_tidr);
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mtspr(SPRN_IAMR, host_iamr);
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mtspr(SPRN_PSPB, 0);
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if (host_amr != vcpu->arch.amr)
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mtspr(SPRN_AMR, host_amr);
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@ -4641,8 +4681,10 @@ void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr, unsigned long mask)
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struct kvmppc_vcore *vc = kvm->arch.vcores[i];
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if (!vc)
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continue;
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spin_lock(&vc->lock);
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vc->lpcr = (vc->lpcr & ~mask) | lpcr;
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verify_lpcr(kvm, vc->lpcr);
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spin_unlock(&vc->lock);
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if (++cores_done >= kvm->arch.online_vcores)
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break;
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@ -4970,6 +5012,7 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
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kvmppc_setup_partition_table(kvm);
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}
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verify_lpcr(kvm, lpcr);
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kvm->arch.lpcr = lpcr;
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/* Initialization for future HPT resizes */
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@ -5369,8 +5412,10 @@ static unsigned int default_hcall_list[] = {
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H_READ,
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H_PROTECT,
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H_BULK_REMOVE,
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#ifdef CONFIG_SPAPR_TCE_IOMMU
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H_GET_TCE,
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H_PUT_TCE,
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#endif
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H_SET_DABR,
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H_SET_XDABR,
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H_CEDE,
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@ -662,6 +662,9 @@ static void kvmppc_end_cede(struct kvm_vcpu *vcpu)
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void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr)
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{
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/* Guest must always run with ME enabled, HV disabled. */
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msr = (msr | MSR_ME) & ~MSR_HV;
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/*
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* Check for illegal transactional state bit combination
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* and if we find it, force the TS field to a safe state.
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@ -132,8 +132,33 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
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}
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}
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/*
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* This can result in some L0 HV register state being leaked to an L1
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* hypervisor when the hv_guest_state is copied back to the guest after
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* being modified here.
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*
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* There is no known problem with such a leak, and in many cases these
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* register settings could be derived by the guest by observing behaviour
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* and timing, interrupts, etc., but it is an issue to consider.
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*/
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static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
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{
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struct kvmppc_vcore *vc = vcpu->arch.vcore;
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u64 mask;
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/*
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* Don't let L1 change LPCR bits for the L2 except these:
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*/
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mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD |
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LPCR_LPES | LPCR_MER;
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/*
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* Additional filtering is required depending on hardware
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* and configuration.
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*/
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hr->lpcr = kvmppc_filter_lpcr_hv(vcpu->kvm,
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(vc->lpcr & ~mask) | (hr->lpcr & mask));
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/*
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* Don't let L1 enable features for L2 which we've disabled for L1,
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* but preserve the interrupt cause field.
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@ -271,8 +296,6 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
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u64 hv_ptr, regs_ptr;
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u64 hdec_exp;
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s64 delta_purr, delta_spurr, delta_ic, delta_vtb;
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u64 mask;
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unsigned long lpcr;
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if (vcpu->kvm->arch.l1_ptcr == 0)
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return H_NOT_AVAILABLE;
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@ -320,10 +343,10 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
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vcpu->arch.nested = l2;
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vcpu->arch.nested_vcpu_id = l2_hv.vcpu_token;
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vcpu->arch.regs = l2_regs;
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vcpu->arch.shregs.msr = vcpu->arch.regs.msr;
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mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD |
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LPCR_LPES | LPCR_MER;
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lpcr = (vc->lpcr & ~mask) | (l2_hv.lpcr & mask);
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/* Guest must always run with ME enabled, HV disabled. */
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vcpu->arch.shregs.msr = (vcpu->arch.regs.msr | MSR_ME) & ~MSR_HV;
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sanitise_hv_regs(vcpu, &l2_hv);
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restore_hv_regs(vcpu, &l2_hv);
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@ -335,7 +358,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
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r = RESUME_HOST;
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break;
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}
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r = kvmhv_run_single_vcpu(vcpu, hdec_exp, lpcr);
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r = kvmhv_run_single_vcpu(vcpu, hdec_exp, l2_hv.lpcr);
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} while (is_kvmppc_resume_guest(r));
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/* save L2 state for return */
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@ -673,8 +673,7 @@ long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
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}
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long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va)
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unsigned long pte_index, unsigned long avpn)
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{
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struct kvm *kvm = vcpu->kvm;
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__be64 *hpte;
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