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powerpc: Add POWER10 architected mode
PVR value of 0x0F000006 means we are arch v3.1 compliant (i.e. POWER10). This is used by phyp and kvm when booting as a pseries guest to detect the presence of new P10 features and to enable the appropriate hwcap and facility bits. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> [mpe: Fall through to __init_FSCR rather than duplicating it, drop hack to set current->thread.fscr now that is handled elsewhere.] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200521014341.29095-8-alistair@popple.id.au
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87939d50e5
commit
a3ea40d5c7
6 changed files with 65 additions and 6 deletions
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@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
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#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
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CPU_FTR_P9_TM_HV_ASSIST | \
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CPU_FTR_P9_TM_XER_SO_BUG)
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#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_SAO | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
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CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
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CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
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CPU_FTR_ARCH_31)
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#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
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#define CPU_FTRS_POSSIBLE \
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(CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
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CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
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CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
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#else
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#define CPU_FTRS_POSSIBLE \
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(CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
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CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
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CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
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CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
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CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
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CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
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#endif /* CONFIG_CPU_LITTLE_ENDIAN */
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#endif
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#else
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@ -122,6 +122,7 @@
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#define MMU_FTRS_POWER7 MMU_FTRS_POWER6
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#define MMU_FTRS_POWER8 MMU_FTRS_POWER6
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#define MMU_FTRS_POWER9 MMU_FTRS_POWER6
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#define MMU_FTRS_POWER10 MMU_FTRS_POWER6
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#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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MMU_FTR_CI_LARGE_PAGE
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#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
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@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
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#define OV1_PPC_2_07 0x01 /* set if we support PowerPC 2.07 */
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#define OV1_PPC_3_00 0x80 /* set if we support PowerPC 3.00 */
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#define OV1_PPC_3_1 0x40 /* set if we support PowerPC 3.1 */
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/* Option vector 2: Open Firmware options supported */
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#define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */
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@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
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mtlr r11
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blr
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_GLOBAL(__setup_cpu_power10)
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mflr r11
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bl __init_FSCR_power10
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b 1f
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_GLOBAL(__setup_cpu_power9)
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mflr r11
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bl __init_FSCR
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bl __init_PMU
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1: bl __init_PMU
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bl __init_hvmode_206
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mtlr r11
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beqlr
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@ -116,10 +121,15 @@ _GLOBAL(__setup_cpu_power9)
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power10)
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mflr r11
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bl __init_FSCR_power10
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b 1f
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_GLOBAL(__restore_cpu_power9)
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mflr r11
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bl __init_FSCR
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bl __init_PMU
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1: bl __init_PMU
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mfmsr r3
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rldicl. r0,r3,4,63
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mtlr r11
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@ -182,6 +192,12 @@ __init_LPCR_ISA300:
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isync
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blr
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__init_FSCR_power10:
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mfspr r3, SPRN_FSCR
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ori r3, r3, FSCR_PREFIX
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mtspr SPRN_FSCR, r3
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// fall through
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__init_FSCR:
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mfspr r3,SPRN_FSCR
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ori r3,r3,FSCR_TAR|FSCR_EBB
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@ -70,6 +70,8 @@ extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
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extern void __restore_cpu_power8(void);
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extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
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extern void __restore_cpu_power9(void);
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extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
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extern void __restore_cpu_power10(void);
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extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
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extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
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extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
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@ -119,6 +121,10 @@ extern void __restore_cpu_e6500(void);
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PPC_FEATURE2_ARCH_3_00 | \
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PPC_FEATURE2_HAS_IEEE128 | \
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PPC_FEATURE2_DARN )
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#define COMMON_USER_POWER10 COMMON_USER_POWER9
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#define COMMON_USER2_POWER10 (COMMON_USER2_POWER9 | \
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PPC_FEATURE2_ARCH_3_1 | \
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PPC_FEATURE2_MMA)
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#ifdef CONFIG_PPC_BOOK3E_64
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#define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
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@ -367,6 +373,22 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_restore = __restore_cpu_power9,
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.platform = "power9",
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},
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{ /* 3.1-compliant processor, i.e. Power10 "architected" mode */
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.pvr_mask = 0xffffffff,
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.pvr_value = 0x0f000006,
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.cpu_name = "POWER10 (architected)",
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.cpu_features = CPU_FTRS_POWER10,
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.cpu_user_features = COMMON_USER_POWER10,
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.cpu_user_features2 = COMMON_USER2_POWER10,
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.mmu_features = MMU_FTRS_POWER10,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.oprofile_type = PPC_OPROFILE_INVALID,
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.oprofile_cpu_type = "ppc64/ibm-compat-v1",
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.cpu_setup = __setup_cpu_power10,
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.cpu_restore = __restore_cpu_power10,
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.platform = "power10",
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},
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{ /* Power7 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x003f0000,
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@ -920,7 +920,7 @@ struct option_vector6 {
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} __packed;
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struct ibm_arch_vec {
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struct { u32 mask, val; } pvrs[12];
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struct { u32 mask, val; } pvrs[14];
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u8 num_vectors;
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@ -973,6 +973,14 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
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.mask = cpu_to_be32(0xffff0000), /* POWER9 */
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.val = cpu_to_be32(0x004e0000),
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},
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{
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.mask = cpu_to_be32(0xffff0000), /* POWER10 */
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.val = cpu_to_be32(0x00800000),
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},
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{
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.mask = cpu_to_be32(0xffffffff), /* all 3.1-compliant */
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.val = cpu_to_be32(0x0f000006),
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},
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{
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.mask = cpu_to_be32(0xffffffff), /* all 3.00-compliant */
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.val = cpu_to_be32(0x0f000005),
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@ -1002,7 +1010,7 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
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.byte1 = 0,
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.arch_versions = OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
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OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
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.arch_versions3 = OV1_PPC_3_00,
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.arch_versions3 = OV1_PPC_3_00 | OV1_PPC_3_1,
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},
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.vec2_len = VECTOR_LENGTH(sizeof(struct option_vector2)),
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