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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ARM: imx: add common clock support for pllv3
This PLL is found on i.MX6 SoCs Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
parent
a547b816a8
commit
a3f6b9dbf2
3 changed files with 433 additions and 1 deletions
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@ -11,7 +11,7 @@ obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-i
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obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
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obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o
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obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o
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# Support for CMOS sensor interface
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obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
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419
arch/arm/mach-imx/clk-pllv3.c
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419
arch/arm/mach-imx/clk-pllv3.c
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@ -0,0 +1,419 @@
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2012 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/err.h>
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#include "clk.h"
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#define PLL_NUM_OFFSET 0x10
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#define PLL_DENOM_OFFSET 0x20
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_ENABLE (0x1 << 13)
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#define BM_PLL_BYPASS (0x1 << 16)
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#define BM_PLL_LOCK (0x1 << 31)
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/**
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* struct clk_pllv3 - IMX PLL clock version 3
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* @clk_hw: clock source
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* @base: base address of PLL registers
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* @powerup_set: set POWER bit to power up the PLL
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* @gate_mask: mask of gate bits
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* @div_mask: mask of divider bits
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*
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* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
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* is actually a multiplier, and always sits at bit 0.
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*/
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struct clk_pllv3 {
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struct clk_hw hw;
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void __iomem *base;
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bool powerup_set;
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u32 gate_mask;
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u32 div_mask;
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};
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#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
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static int clk_pllv3_prepare(struct clk_hw *hw)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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u32 val;
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val = readl_relaxed(pll->base);
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val &= ~BM_PLL_BYPASS;
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if (pll->powerup_set)
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val |= BM_PLL_POWER;
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else
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val &= ~BM_PLL_POWER;
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writel_relaxed(val, pll->base);
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/* Wait for PLL to lock */
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while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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return 0;
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}
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static void clk_pllv3_unprepare(struct clk_hw *hw)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 val;
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val = readl_relaxed(pll->base);
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val |= BM_PLL_BYPASS;
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if (pll->powerup_set)
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val &= ~BM_PLL_POWER;
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else
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val |= BM_PLL_POWER;
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writel_relaxed(val, pll->base);
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}
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static int clk_pllv3_enable(struct clk_hw *hw)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 val;
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val = readl_relaxed(pll->base);
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val |= pll->gate_mask;
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writel_relaxed(val, pll->base);
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return 0;
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}
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static void clk_pllv3_disable(struct clk_hw *hw)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 val;
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val = readl_relaxed(pll->base);
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val &= ~pll->gate_mask;
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writel_relaxed(val, pll->base);
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}
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static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 div = readl_relaxed(pll->base) & pll->div_mask;
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return (div == 1) ? parent_rate * 22 : parent_rate * 20;
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}
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static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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return (rate >= parent_rate * 22) ? parent_rate * 22 :
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parent_rate * 20;
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}
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static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 val, div;
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if (rate == parent_rate * 22)
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div = 1;
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else if (rate == parent_rate * 20)
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div = 0;
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else
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return -EINVAL;
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val = readl_relaxed(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel_relaxed(val, pll->base);
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return 0;
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}
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static const struct clk_ops clk_pllv3_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_recalc_rate,
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.round_rate = clk_pllv3_round_rate,
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.set_rate = clk_pllv3_set_rate,
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};
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static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 div = readl_relaxed(pll->base) & pll->div_mask;
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return parent_rate * div / 2;
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}
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static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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unsigned long min_rate = parent_rate * 54 / 2;
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unsigned long max_rate = parent_rate * 108 / 2;
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u32 div;
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if (rate > max_rate)
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rate = max_rate;
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else if (rate < min_rate)
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rate = min_rate;
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div = rate * 2 / parent_rate;
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return parent_rate * div / 2;
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}
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static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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unsigned long min_rate = parent_rate * 54 / 2;
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unsigned long max_rate = parent_rate * 108 / 2;
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u32 val, div;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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div = rate * 2 / parent_rate;
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val = readl_relaxed(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel_relaxed(val, pll->base);
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return 0;
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}
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static const struct clk_ops clk_pllv3_sys_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_sys_recalc_rate,
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.round_rate = clk_pllv3_sys_round_rate,
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.set_rate = clk_pllv3_sys_set_rate,
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};
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static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
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u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
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u32 div = readl_relaxed(pll->base) & pll->div_mask;
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return (parent_rate * div) + ((parent_rate / mfd) * mfn);
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}
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static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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unsigned long min_rate = parent_rate * 27;
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unsigned long max_rate = parent_rate * 54;
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u32 div;
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u32 mfn, mfd = 1000000;
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s64 temp64;
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if (rate > max_rate)
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rate = max_rate;
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else if (rate < min_rate)
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rate = min_rate;
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div = rate / parent_rate;
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temp64 = (u64) (rate - div * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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return parent_rate * div + parent_rate / mfd * mfn;
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}
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static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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unsigned long min_rate = parent_rate * 27;
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unsigned long max_rate = parent_rate * 54;
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u32 val, div;
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u32 mfn, mfd = 1000000;
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s64 temp64;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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div = rate / parent_rate;
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temp64 = (u64) (rate - div * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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val = readl_relaxed(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel_relaxed(val, pll->base);
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writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
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writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
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return 0;
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}
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static const struct clk_ops clk_pllv3_av_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_av_recalc_rate,
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.round_rate = clk_pllv3_av_round_rate,
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.set_rate = clk_pllv3_av_set_rate,
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};
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static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 div = readl_relaxed(pll->base) & pll->div_mask;
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switch (div) {
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case 0:
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return 25000000;
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case 1:
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return 50000000;
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case 2:
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return 100000000;
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case 3:
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return 125000000;
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}
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return 0;
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}
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static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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if (rate >= 125000000)
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rate = 125000000;
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else if (rate >= 100000000)
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rate = 100000000;
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else if (rate >= 50000000)
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rate = 50000000;
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else
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rate = 25000000;
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return rate;
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}
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static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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u32 val, div;
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switch (rate) {
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case 25000000:
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div = 0;
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break;
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case 50000000:
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div = 1;
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break;
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case 100000000:
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div = 2;
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break;
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case 125000000:
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div = 3;
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break;
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default:
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return -EINVAL;
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}
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val = readl_relaxed(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel_relaxed(val, pll->base);
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return 0;
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}
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static const struct clk_ops clk_pllv3_enet_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_enet_recalc_rate,
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.round_rate = clk_pllv3_enet_round_rate,
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.set_rate = clk_pllv3_enet_set_rate,
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};
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static const struct clk_ops clk_pllv3_mlb_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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u32 gate_mask, u32 div_mask)
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{
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struct clk_pllv3 *pll;
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const struct clk_ops *ops;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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switch (type) {
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case IMX_PLLV3_SYS:
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ops = &clk_pllv3_sys_ops;
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break;
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case IMX_PLLV3_USB:
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ops = &clk_pllv3_ops;
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pll->powerup_set = true;
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break;
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case IMX_PLLV3_AV:
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ops = &clk_pllv3_av_ops;
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break;
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case IMX_PLLV3_ENET:
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ops = &clk_pllv3_enet_ops;
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break;
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case IMX_PLLV3_MLB:
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ops = &clk_pllv3_mlb_ops;
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break;
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default:
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ops = &clk_pllv3_ops;
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}
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pll->base = base;
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pll->gate_mask = gate_mask;
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pll->div_mask = div_mask;
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init.name = name;
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init.ops = ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll->hw.init = &init;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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@ -11,6 +11,19 @@ struct clk *imx_clk_pllv1(const char *name, const char *parent,
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struct clk *imx_clk_pllv2(const char *name, const char *parent,
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void __iomem *base);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_USB,
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IMX_PLLV3_AV,
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IMX_PLLV3_ENET,
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IMX_PLLV3_MLB,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 gate_mask,
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u32 div_mask);
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static inline struct clk *imx_clk_fixed(const char *name, int rate)
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{
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return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
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