mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 02:39:48 +00:00
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3030/2: fix permission check in the obscur cmpxchg syscall [ARM] nommu: rename compressed/head.S symbols to a new style [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h [ARM] Move read of processor ID out of lookup_processor_type() [ARM] Fix typo in tlbflush.h [ARM] noMMU: removes TLB codes in nommu mode [ARM] noMMU: block sys_fork in nommu mode [ARM] 3399/1: Fix link problem when CONFIG_PRINTK is disabled [ARM] 3398/1: Fix the VFP registers loading/storing base address [ARM] 3397/1: AT91RM9200 Header update [ARM] 3385/1: Battery support for sharp zaurus sl-5500 (collie) [ARM] SMP: don't set cpu_*_map in smp_prepare_boot_cpu include/linux/clk.h is betraying its ARM origins [ARM] Move enable_irq and disable_irq to assembler.h [ARM] 3391/1: use PLAT8250_DEV_PLATFORM{,1} for platform device id instead of 0/1
This commit is contained in:
commit
a41622eaa9
37 changed files with 596 additions and 167 deletions
|
@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
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str r1, [r0]
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mov pc, lr
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__armv4_cache_on:
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__armv4_mmu_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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@ -367,24 +367,24 @@ __armv4_cache_on:
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x0030
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bl __common_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mov pc, r12
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__arm6_cache_on:
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__arm6_mmu_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov r0, #0x30
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bl __common_cache_on
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bl __common_mmu_cache_on
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mov r0, #0
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov pc, r12
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__common_cache_on:
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__common_mmu_cache_on:
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#ifndef DEBUG
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orr r0, r0, #0x000d @ Write buffer, mmu
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#endif
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@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types
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proc_types:
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.word 0x41560600 @ ARM6/610
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.word 0xffffffe0
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b __arm6_cache_off @ works, but slow
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b __arm6_cache_off
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b __arm6_mmu_cache_off @ works, but slow
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b __arm6_mmu_cache_off
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mov pc, lr
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@ b __arm6_cache_on @ untested
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@ b __arm6_cache_off
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@ b __armv3_cache_flush
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@ b __arm6_mmu_cache_on @ untested
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@ b __arm6_mmu_cache_off
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@ b __armv3_mmu_cache_flush
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.word 0x00000000 @ old ARM ID
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.word 0x0000f000
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@ -486,14 +486,14 @@ proc_types:
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.word 0x41007000 @ ARM7/710
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.word 0xfff8fe00
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b __arm7_cache_off
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b __arm7_cache_off
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b __arm7_mmu_cache_off
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b __arm7_mmu_cache_off
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mov pc, lr
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.word 0x41807200 @ ARM720T (writethrough)
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.word 0xffffff00
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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mov pc, lr
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.word 0x00007000 @ ARM7 IDs
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@ -506,41 +506,41 @@ proc_types:
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.word 0x4401a100 @ sa110 / sa1100
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.word 0xffffffe0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x6901b110 @ sa1110
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.word 0xfffffff0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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@ These match on the architecture ID
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.word 0x00020000 @ ARMv4T
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00050000 @ ARMv5TE
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00060000 @ ARMv5TEJ
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv4_mmu_cache_flush
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.word 0x00070000 @ ARMv6
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.word 0x000f0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv6_cache_flush
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b __armv4_mmu_cache_on
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b __armv4_mmu_cache_off
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b __armv6_mmu_cache_flush
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.word 0 @ unrecognised type
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.word 0
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@ -562,7 +562,7 @@ proc_types:
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cache_off: mov r3, #12 @ cache_off function
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b call_cache_fn
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__armv4_cache_off:
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__armv4_mmu_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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@ -571,15 +571,15 @@ __armv4_cache_off:
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mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
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mov pc, lr
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__arm6_cache_off:
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__arm6_mmu_cache_off:
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mov r0, #0x00000030 @ ARM6 control reg.
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b __armv3_cache_off
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b __armv3_mmu_cache_off
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__arm7_cache_off:
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__arm7_mmu_cache_off:
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mov r0, #0x00000070 @ ARM7 control reg.
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b __armv3_cache_off
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b __armv3_mmu_cache_off
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__armv3_cache_off:
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__armv3_mmu_cache_off:
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mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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@ -601,7 +601,7 @@ cache_clean_flush:
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mov r3, #16
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b call_cache_fn
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__armv6_cache_flush:
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__armv6_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
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@ -609,7 +609,7 @@ __armv6_cache_flush:
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv4_cache_flush:
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__armv4_mmu_cache_flush:
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r11, #32 @ default: 32 byte line size
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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@ -637,7 +637,7 @@ no_cache_id:
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv3_cache_flush:
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__armv3_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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|
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@ -37,24 +37,6 @@
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#endif
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.endm
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#if __LINUX_ARM_ARCH__ >= 6
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.macro disable_irq
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cpsid i
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.endm
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.macro enable_irq
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cpsie i
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.endm
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#else
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.macro disable_irq
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msr cpsr_c, #PSR_I_BIT | SVC_MODE
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.endm
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.macro enable_irq
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msr cpsr_c, #SVC_MODE
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.endm
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#endif
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.macro get_thread_info, rd
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mov \rd, sp, lsr #13
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mov \rd, \rd, lsl #13
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|
|
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@ -81,6 +81,7 @@
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ENTRY(stext)
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
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@ and irqs disabled
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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@ -155,6 +156,7 @@ ENTRY(secondary_startup)
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* as it has already been validated by the primary processor.
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*/
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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|
@ -449,19 +451,19 @@ __error:
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* (and therefore, we are not in the correct address space). We have to
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* calculate the offset.
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*
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* r9 = cpuid
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* Returns:
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* r3, r4, r6 corrupted
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* r5 = proc_info pointer in physical address space
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* r9 = cpuid
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* r9 = cpuid (preserved)
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*/
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.type __lookup_processor_type, %function
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__lookup_processor_type:
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adr r3, 3f
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ldmda r3, {r5, r6, r9}
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sub r3, r3, r9 @ get offset between virt&phys
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ldmda r3, {r5 - r7}
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sub r3, r3, r7 @ get offset between virt&phys
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add r5, r5, r3 @ convert virt addresses to
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add r6, r6, r3 @ physical address space
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mrc p15, 0, r9, c0, c0 @ get processor id
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1: ldmia r5, {r3, r4} @ value, mask
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and r4, r4, r9 @ mask wanted bits
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teq r3, r4
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|
@ -476,10 +478,11 @@ __lookup_processor_type:
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* This provides a C-API version of the above function.
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*/
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ENTRY(lookup_processor_type)
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stmfd sp!, {r4 - r6, r9, lr}
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stmfd sp!, {r4 - r7, r9, lr}
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mov r9, r0
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bl __lookup_processor_type
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mov r0, r5
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ldmfd sp!, {r4 - r6, r9, pc}
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ldmfd sp!, {r4 - r7, r9, pc}
|
||||
|
||||
/*
|
||||
* Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
|
||||
|
|
|
@ -278,7 +278,7 @@ int cpu_architecture(void)
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|||
* These functions re-use the assembly code in head.S, which
|
||||
* already provide the required functionality.
|
||||
*/
|
||||
extern struct proc_info_list *lookup_processor_type(void);
|
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extern struct proc_info_list *lookup_processor_type(unsigned int);
|
||||
extern struct machine_desc *lookup_machine_type(unsigned int);
|
||||
|
||||
static void __init setup_processor(void)
|
||||
|
@ -290,7 +290,7 @@ static void __init setup_processor(void)
|
|||
* types. The linker builds this table for us from the
|
||||
* entries in arch/arm/mm/proc-*.S
|
||||
*/
|
||||
list = lookup_processor_type();
|
||||
list = lookup_processor_type(processor_id);
|
||||
if (!list) {
|
||||
printk("CPU configuration botched (ID %08x), unable "
|
||||
"to continue.\n", processor_id);
|
||||
|
|
|
@ -337,9 +337,6 @@ void __init smp_prepare_boot_cpu(void)
|
|||
unsigned int cpu = smp_processor_id();
|
||||
|
||||
per_cpu(cpu_data, cpu).idle = current;
|
||||
|
||||
cpu_set(cpu, cpu_present_map);
|
||||
cpu_set(cpu, cpu_online_map);
|
||||
}
|
||||
|
||||
static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)
|
||||
|
|
|
@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third,
|
|||
*/
|
||||
asmlinkage int sys_fork(struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_MMU
|
||||
return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
|
||||
#else
|
||||
/* can not support in nommu mode */
|
||||
return(-EINVAL);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Clone a task - this clones the calling program thread.
|
||||
|
|
|
@ -506,7 +506,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
|
|||
if (!pmd_present(*pmd))
|
||||
goto bad_access;
|
||||
pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
|
||||
if (!pte_present(*pte) || !pte_write(*pte)) {
|
||||
if (!pte_present(*pte) || !pte_dirty(*pte)) {
|
||||
pte_unmap_unlock(pte, ptl);
|
||||
goto bad_access;
|
||||
}
|
||||
|
|
|
@ -29,7 +29,7 @@ ENTRY(__backtrace)
|
|||
|
||||
ENTRY(c_backtrace)
|
||||
|
||||
#ifndef CONFIG_FRAME_POINTER
|
||||
#if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK)
|
||||
mov pc, lr
|
||||
#else
|
||||
|
||||
|
|
|
@ -103,7 +103,7 @@ static struct plat_serial8250_port iop33x_uart1_data[] = {
|
|||
|
||||
static struct platform_device iop33x_uart0 = {
|
||||
.name = "serial8250",
|
||||
.id = 0,
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev.platform_data = iop33x_uart0_data,
|
||||
.num_resources = 2,
|
||||
.resource = iop33x_uart0_resources,
|
||||
|
@ -111,7 +111,7 @@ static struct platform_device iop33x_uart0 = {
|
|||
|
||||
static struct platform_device iop33x_uart1 = {
|
||||
.name = "serial8250",
|
||||
.id = 1,
|
||||
.id = PLAT8250_DEV_PLATFORM1,
|
||||
.dev.platform_data = iop33x_uart1_data,
|
||||
.num_resources = 2,
|
||||
.resource = iop33x_uart1_resources,
|
||||
|
|
|
@ -167,7 +167,7 @@ void __init omap_serial_init()
|
|||
|
||||
static struct platform_device serial_device = {
|
||||
.name = "serial8250",
|
||||
.id = 0,
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = serial_platform_data,
|
||||
},
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <asm/irq.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
|
|
278
arch/arm/mach-sa1100/collie_pm.c
Normal file
278
arch/arm/mach-sa1100/collie_pm.c
Normal file
|
@ -0,0 +1,278 @@
|
|||
/*
|
||||
* Based on spitz_pm.c and sharp code.
|
||||
*
|
||||
* Copyright (C) 2001 SHARP
|
||||
* Copyright 2005 Pavel Machek <pavel@suse.cz>
|
||||
*
|
||||
* Distribute under GPLv2.
|
||||
*
|
||||
* Li-ion batteries are angry beasts, and they like to explode. This driver is not finished,
|
||||
* and sometimes charges them when it should not. If it makes angry lithium to come your way...
|
||||
* ...well, you have been warned.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/stat.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/hardware/scoop.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/arch/collie.h>
|
||||
#include <asm/mach/sharpsl_param.h>
|
||||
#include <asm/hardware/sharpsl_pm.h>
|
||||
|
||||
#include "../drivers/mfd/ucb1x00.h"
|
||||
|
||||
static struct ucb1x00 *ucb;
|
||||
static int ad_revise;
|
||||
|
||||
#define ADCtoPower(x) ((330 * x * 2) / 1024)
|
||||
|
||||
static void collie_charger_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (sharpsl_param.adadj != -1) {
|
||||
ad_revise = sharpsl_param.adadj;
|
||||
}
|
||||
|
||||
/* Register interrupt handler. */
|
||||
if ((err = request_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr, SA_INTERRUPT,
|
||||
"ACIN", sharpsl_ac_isr))) {
|
||||
printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_AC_IN);
|
||||
return;
|
||||
}
|
||||
if ((err = request_irq(COLLIE_IRQ_GPIO_CO, sharpsl_chrg_full_isr, SA_INTERRUPT,
|
||||
"CO", sharpsl_chrg_full_isr))) {
|
||||
free_irq(COLLIE_IRQ_GPIO_AC_IN, sharpsl_ac_isr);
|
||||
printk("Could not get irq %d.\n", COLLIE_IRQ_GPIO_CO);
|
||||
return;
|
||||
}
|
||||
|
||||
ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON |
|
||||
COLLIE_TC35143_GPIO_BBAT_ON);
|
||||
return;
|
||||
}
|
||||
|
||||
static void collie_measure_temp(int on)
|
||||
{
|
||||
if (on)
|
||||
ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
|
||||
else
|
||||
ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
|
||||
}
|
||||
|
||||
static void collie_charge(int on)
|
||||
{
|
||||
if (on) {
|
||||
printk("Should start charger\n");
|
||||
} else {
|
||||
printk("Should stop charger\n");
|
||||
}
|
||||
#ifdef I_AM_SURE
|
||||
|
||||
/* Zaurus seems to contain LTC1731 ; it should know when to
|
||||
* stop charging itself, so setting charge on should be
|
||||
* relatively harmless (as long as it is not done too often).
|
||||
*/
|
||||
#define CF_BUF_CTRL_BASE 0xF0800000
|
||||
#define SCOOP_REG(adr) (*(volatile unsigned short*)(CF_BUF_CTRL_BASE+(adr)))
|
||||
#define SCOOP_REG_GPWR SCOOP_REG(SCOOP_GPWR)
|
||||
|
||||
if (on) {
|
||||
set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
|
||||
} else {
|
||||
reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void collie_discharge(int on)
|
||||
{
|
||||
}
|
||||
|
||||
static void collie_discharge1(int on)
|
||||
{
|
||||
}
|
||||
|
||||
static void collie_presuspend(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void collie_postsuspend(void)
|
||||
{
|
||||
}
|
||||
|
||||
static int collie_should_wakeup(unsigned int resume_on_alarm)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long collie_charger_wakeup(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int collie_read_backup_battery(void)
|
||||
{
|
||||
int voltage;
|
||||
|
||||
ucb1x00_adc_enable(ucb);
|
||||
|
||||
/* Gives 75..130 */
|
||||
ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_BBAT_ON, 0);
|
||||
voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
|
||||
|
||||
ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
|
||||
ucb1x00_adc_disable(ucb);
|
||||
|
||||
printk("Backup battery = %d(%d)\n", ADCtoPower(voltage), voltage);
|
||||
|
||||
return ADCtoPower(voltage);
|
||||
}
|
||||
|
||||
int collie_read_main_battery(void)
|
||||
{
|
||||
int voltage, voltage_rev, voltage_volts;
|
||||
|
||||
ucb1x00_adc_enable(ucb);
|
||||
ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_BBAT_ON);
|
||||
ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_MBAT_ON, 0);
|
||||
/* gives values 160..255 with battery removed... and
|
||||
145..255 with battery inserted. (on AC), goes as low as
|
||||
80 on DC. */
|
||||
voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD1, UCB_SYNC);
|
||||
|
||||
ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON);
|
||||
ucb1x00_adc_disable(ucb);
|
||||
|
||||
voltage_rev = voltage + ((ad_revise * voltage) / 652);
|
||||
voltage_volts = ADCtoPower(voltage_rev);
|
||||
|
||||
printk("Main battery = %d(%d)\n", voltage_volts, voltage);
|
||||
|
||||
if (voltage != -1)
|
||||
return voltage_volts;
|
||||
else
|
||||
return voltage;
|
||||
}
|
||||
|
||||
int collie_read_temp(void)
|
||||
{
|
||||
int voltage;
|
||||
|
||||
/* According to Sharp, temp must be > 973, main battery must be < 465,
|
||||
FIXME: sharpsl_pm.c has both conditions negated? FIXME: values
|
||||
are way out of range? */
|
||||
|
||||
ucb1x00_adc_enable(ucb);
|
||||
ucb1x00_io_write(ucb, COLLIE_TC35143_GPIO_TMP_ON, 0);
|
||||
/* >1010 = battery removed, 460 = 22C ?, higer = lower temp ? */
|
||||
voltage = ucb1x00_adc_read(ucb, UCB_ADC_INP_AD0, UCB_SYNC);
|
||||
ucb1x00_io_write(ucb, 0, COLLIE_TC35143_GPIO_TMP_ON);
|
||||
ucb1x00_adc_disable(ucb);
|
||||
|
||||
printk("Battery temp = %d\n", voltage);
|
||||
return voltage;
|
||||
}
|
||||
|
||||
static unsigned long read_devdata(int which)
|
||||
{
|
||||
switch (which) {
|
||||
case SHARPSL_BATT_VOLT:
|
||||
return collie_read_main_battery();
|
||||
case SHARPSL_BATT_TEMP:
|
||||
return collie_read_temp();
|
||||
case SHARPSL_ACIN_VOLT:
|
||||
return 0x1;
|
||||
case SHARPSL_STATUS_ACIN: {
|
||||
int ret = GPLR & COLLIE_GPIO_AC_IN;
|
||||
printk("AC status = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
case SHARPSL_STATUS_FATAL: {
|
||||
int ret = GPLR & COLLIE_GPIO_MAIN_BAT_LOW;
|
||||
printk("Fatal bat = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
default:
|
||||
return ~0;
|
||||
}
|
||||
}
|
||||
|
||||
struct battery_thresh collie_battery_levels[] = {
|
||||
{ 368, 100},
|
||||
{ 358, 25},
|
||||
{ 356, 5},
|
||||
{ 0, 0},
|
||||
};
|
||||
|
||||
struct sharpsl_charger_machinfo collie_pm_machinfo = {
|
||||
.init = collie_charger_init,
|
||||
.read_devdata = read_devdata,
|
||||
.discharge = collie_discharge,
|
||||
.discharge1 = collie_discharge1,
|
||||
.charge = collie_charge,
|
||||
.measure_temp = collie_measure_temp,
|
||||
.presuspend = collie_presuspend,
|
||||
.postsuspend = collie_postsuspend,
|
||||
.charger_wakeup = collie_charger_wakeup,
|
||||
.should_wakeup = collie_should_wakeup,
|
||||
.bat_levels = 3,
|
||||
.bat_levels_noac = collie_battery_levels,
|
||||
.bat_levels_acin = collie_battery_levels,
|
||||
.status_high_acin = 368,
|
||||
.status_low_acin = 358,
|
||||
.status_high_noac = 368,
|
||||
.status_low_noac = 358,
|
||||
};
|
||||
|
||||
static int __init collie_pm_ucb_add(struct ucb1x00_dev *pdev)
|
||||
{
|
||||
sharpsl_pm.machinfo = &collie_pm_machinfo;
|
||||
ucb = pdev->ucb;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ucb1x00_driver collie_pm_ucb_driver = {
|
||||
.add = collie_pm_ucb_add,
|
||||
};
|
||||
|
||||
static struct platform_device *collie_pm_device;
|
||||
|
||||
static int __init collie_pm_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
collie_pm_device = platform_device_alloc("sharpsl-pm", -1);
|
||||
if (!collie_pm_device)
|
||||
return -ENOMEM;
|
||||
|
||||
collie_pm_device->dev.platform_data = &collie_pm_machinfo;
|
||||
ret = platform_device_add(collie_pm_device);
|
||||
|
||||
if (ret)
|
||||
platform_device_put(collie_pm_device);
|
||||
|
||||
if (!ret)
|
||||
ret = ucb1x00_register_driver(&collie_pm_ucb_driver);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit collie_pm_exit(void)
|
||||
{
|
||||
ucb1x00_unregister_driver(&collie_pm_ucb_driver);
|
||||
platform_device_unregister(collie_pm_device);
|
||||
}
|
||||
|
||||
module_init(collie_pm_init);
|
||||
module_exit(collie_pm_exit);
|
|
@ -266,12 +266,18 @@ config CPU_32v6K
|
|||
# This defines the compiler instruction set which depends on the machine type.
|
||||
config CPU_32v3
|
||||
bool
|
||||
select TLS_REG_EMUL if SMP
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
|
||||
config CPU_32v4
|
||||
bool
|
||||
select TLS_REG_EMUL if SMP
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
|
||||
config CPU_32v5
|
||||
bool
|
||||
select TLS_REG_EMUL if SMP
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
|
||||
config CPU_32v6
|
||||
bool
|
||||
|
@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE
|
|||
|
||||
config TLS_REG_EMUL
|
||||
bool
|
||||
default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
|
||||
help
|
||||
An SMP system using a pre-ARMv6 processor (there are apparently
|
||||
a few prototypes like that in existence) and therefore access to
|
||||
|
@ -436,7 +441,6 @@ config HAS_TLS_REG
|
|||
|
||||
config NEEDS_SYSCALL_FOR_CMPXCHG
|
||||
bool
|
||||
default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
|
||||
help
|
||||
SMP on a pre-ARMv6 processor? Well OK then.
|
||||
Forget about fast user space cmpxchg support.
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/page.h>
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/page.h>
|
||||
|
|
|
@ -51,6 +51,7 @@
|
|||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/page.h>
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/config.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/page.h>
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
/*
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <asm/asm-offsets.h>
|
||||
#include <asm/hardware/arm_scu.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#include "proc-macros.S"
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <asm/assembler.h>
|
||||
#include <asm/procinfo.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include "proc-macros.S"
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/vfpmacros.h>
|
||||
|
||||
.globl do_vfp
|
||||
|
|
|
@ -102,7 +102,6 @@ vfp_support_entry:
|
|||
VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading
|
||||
@ nonexistant reg on rev0
|
||||
VFPFSTMIA r4 @ save the working registers
|
||||
add r4, r4, #8*16+4
|
||||
stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
|
||||
@ and point r4 at the word at the
|
||||
@ start of the register dump
|
||||
|
@ -111,10 +110,9 @@ no_old_VFP_process:
|
|||
DBGSTR1 "load state %p", r10
|
||||
str r10, [r3] @ update the last_VFP_context pointer
|
||||
@ Load the saved state back into the VFP
|
||||
add r4, r10, #8*16+4
|
||||
ldmia r4, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
|
||||
VFPFLDMIA r10 @ reload the working registers while
|
||||
@ FPEXC is in a safe state
|
||||
ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
|
||||
tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write?
|
||||
VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing
|
||||
@ nonexistant reg on rev0
|
||||
|
|
|
@ -172,6 +172,7 @@
|
|||
#define AT91_PMC_MDIV_4 (3 << 8)
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
|
||||
|
||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
||||
|
@ -286,8 +287,32 @@
|
|||
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
|
||||
|
||||
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
|
||||
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
|
||||
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
|
||||
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
|
||||
#define AT91_MC_ABTSZ_BYTE (0 << 8)
|
||||
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
|
||||
#define AT91_MC_ABTSZ_WORD (2 << 8)
|
||||
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
|
||||
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
|
||||
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
|
||||
#define AT91_MC_ABTTYP_FETCH (2 << 10)
|
||||
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
|
||||
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
|
||||
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
|
||||
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
|
||||
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
|
||||
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
|
||||
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
|
||||
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
|
||||
|
||||
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
|
||||
|
||||
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
|
||||
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
|
||||
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
|
||||
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
|
||||
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
|
||||
|
||||
/* External Bus Interface (EBI) registers */
|
||||
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
|
||||
|
@ -309,8 +334,10 @@
|
|||
/* Static Memory Controller (SMC) registers */
|
||||
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
|
||||
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
|
||||
#define AT91_SMC_NWS_(x) ((x) << 0)
|
||||
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
|
||||
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
|
||||
#define AT91_SMC_TDF_(x) ((x) << 8)
|
||||
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
|
||||
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
|
||||
#define AT91_SMC_DBW_16 (1 << 13)
|
||||
|
@ -322,7 +349,78 @@
|
|||
#define AT91_SMC_ACSS_2 (2 << 16)
|
||||
#define AT91_SMC_ACSS_3 (3 << 16)
|
||||
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
|
||||
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
|
||||
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
|
||||
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
|
||||
|
||||
/* SDRAM Controller registers */
|
||||
#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
|
||||
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
|
||||
#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
|
||||
#define AT91_SDRAMC_MODE_NOP (1 << 0)
|
||||
#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
|
||||
#define AT91_SDRAMC_MODE_LMR (3 << 0)
|
||||
#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
|
||||
#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
|
||||
#define AT91_SDRAMC_DBW_32 (0 << 4)
|
||||
#define AT91_SDRAMC_DBW_16 (1 << 4)
|
||||
|
||||
#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
|
||||
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
|
||||
|
||||
#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
|
||||
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
|
||||
#define AT91_SDRAMC_NC_8 (0 << 0)
|
||||
#define AT91_SDRAMC_NC_9 (1 << 0)
|
||||
#define AT91_SDRAMC_NC_10 (2 << 0)
|
||||
#define AT91_SDRAMC_NC_11 (3 << 0)
|
||||
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
|
||||
#define AT91_SDRAMC_NR_11 (0 << 2)
|
||||
#define AT91_SDRAMC_NR_12 (1 << 2)
|
||||
#define AT91_SDRAMC_NR_13 (2 << 2)
|
||||
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
|
||||
#define AT91_SDRAMC_NB_2 (0 << 4)
|
||||
#define AT91_SDRAMC_NB_4 (1 << 4)
|
||||
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
|
||||
#define AT91_SDRAMC_CAS_2 (2 << 5)
|
||||
#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
|
||||
#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
|
||||
#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
|
||||
#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
|
||||
#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
|
||||
#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
|
||||
|
||||
#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
|
||||
#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
|
||||
#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
|
||||
#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
|
||||
#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
|
||||
#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
|
||||
|
||||
/* Burst Flash Controller register */
|
||||
#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
|
||||
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
|
||||
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
|
||||
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
|
||||
#define AT91_BFC_BFCOM_BURST (2 << 0)
|
||||
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
|
||||
#define AT91_BFC_BFCC_MCK (1 << 2)
|
||||
#define AT91_BFC_BFCC_DIV2 (2 << 2)
|
||||
#define AT91_BFC_BFCC_DIV4 (3 << 2)
|
||||
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
|
||||
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
|
||||
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
|
||||
#define AT91_BFC_PAGES_16 (1 << 8)
|
||||
#define AT91_BFC_PAGES_32 (2 << 8)
|
||||
#define AT91_BFC_PAGES_64 (3 << 8)
|
||||
#define AT91_BFC_PAGES_128 (4 << 8)
|
||||
#define AT91_BFC_PAGES_256 (5 << 8)
|
||||
#define AT91_BFC_PAGES_512 (6 << 8)
|
||||
#define AT91_BFC_PAGES_1024 (7 << 8)
|
||||
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
|
||||
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
|
||||
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
|
||||
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
|
||||
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -79,17 +79,34 @@
|
|||
#define RETINSTR(instr, regs...)\
|
||||
instr regs
|
||||
|
||||
/*
|
||||
* Enable and disable interrupts
|
||||
*/
|
||||
#if __LINUX_ARM_ARCH__ >= 6
|
||||
.macro disable_irq
|
||||
cpsid i
|
||||
.endm
|
||||
|
||||
.macro enable_irq
|
||||
cpsie i
|
||||
.endm
|
||||
#else
|
||||
.macro disable_irq
|
||||
msr cpsr_c, #PSR_I_BIT | SVC_MODE
|
||||
.endm
|
||||
|
||||
.macro enable_irq
|
||||
msr cpsr_c, #SVC_MODE
|
||||
.endm
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Save the current IRQ state and disable IRQs. Note that this macro
|
||||
* assumes FIQs are enabled, and that the processor is in SVC mode.
|
||||
*/
|
||||
.macro save_and_disable_irqs, oldcpsr
|
||||
mrs \oldcpsr, cpsr
|
||||
#if __LINUX_ARM_ARCH__ >= 6
|
||||
cpsid i
|
||||
#else
|
||||
msr cpsr_c, #PSR_I_BIT | MODE_SVC
|
||||
#endif
|
||||
disable_irq
|
||||
.endm
|
||||
|
||||
/*
|
||||
|
|
|
@ -10,10 +10,15 @@
|
|||
#ifndef _ASMARM_PGALLOC_H
|
||||
#define _ASMARM_PGALLOC_H
|
||||
|
||||
#include <asm/domain.h>
|
||||
#include <asm/pgtable-hwdef.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
|
||||
#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
|
||||
|
||||
/*
|
||||
* Since we have only two-level page tables, these are trivial
|
||||
*/
|
||||
|
|
88
include/asm-arm/pgtable-hwdef.h
Normal file
88
include/asm-arm/pgtable-hwdef.h
Normal file
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* linux/include/asm-arm/pgtable-hwdef.h
|
||||
*
|
||||
* Copyright (C) 1995-2002 Russell King
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef _ASMARM_PGTABLE_HWDEF_H
|
||||
#define _ASMARM_PGTABLE_HWDEF_H
|
||||
|
||||
/*
|
||||
* Hardware page table definitions.
|
||||
*
|
||||
* + Level 1 descriptor (PMD)
|
||||
* - common
|
||||
*/
|
||||
#define PMD_TYPE_MASK (3 << 0)
|
||||
#define PMD_TYPE_FAULT (0 << 0)
|
||||
#define PMD_TYPE_TABLE (1 << 0)
|
||||
#define PMD_TYPE_SECT (2 << 0)
|
||||
#define PMD_BIT4 (1 << 4)
|
||||
#define PMD_DOMAIN(x) ((x) << 5)
|
||||
#define PMD_PROTECTION (1 << 9) /* v5 */
|
||||
/*
|
||||
* - section
|
||||
*/
|
||||
#define PMD_SECT_BUFFERABLE (1 << 2)
|
||||
#define PMD_SECT_CACHEABLE (1 << 3)
|
||||
#define PMD_SECT_AP_WRITE (1 << 10)
|
||||
#define PMD_SECT_AP_READ (1 << 11)
|
||||
#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
|
||||
#define PMD_SECT_APX (1 << 15) /* v6 */
|
||||
#define PMD_SECT_S (1 << 16) /* v6 */
|
||||
#define PMD_SECT_nG (1 << 17) /* v6 */
|
||||
#define PMD_SECT_SUPER (1 << 18) /* v6 */
|
||||
|
||||
#define PMD_SECT_UNCACHED (0)
|
||||
#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
|
||||
|
||||
/*
|
||||
* - coarse table (not used)
|
||||
*/
|
||||
|
||||
/*
|
||||
* + Level 2 descriptor (PTE)
|
||||
* - common
|
||||
*/
|
||||
#define PTE_TYPE_MASK (3 << 0)
|
||||
#define PTE_TYPE_FAULT (0 << 0)
|
||||
#define PTE_TYPE_LARGE (1 << 0)
|
||||
#define PTE_TYPE_SMALL (2 << 0)
|
||||
#define PTE_TYPE_EXT (3 << 0) /* v5 */
|
||||
#define PTE_BUFFERABLE (1 << 2)
|
||||
#define PTE_CACHEABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* - extended small page/tiny page
|
||||
*/
|
||||
#define PTE_EXT_XN (1 << 0) /* v6 */
|
||||
#define PTE_EXT_AP_MASK (3 << 4)
|
||||
#define PTE_EXT_AP0 (1 << 4)
|
||||
#define PTE_EXT_AP1 (2 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRO (0 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
|
||||
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
|
||||
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
|
||||
#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
|
||||
#define PTE_EXT_APX (1 << 9) /* v6 */
|
||||
#define PTE_EXT_SHARED (1 << 10) /* v6 */
|
||||
#define PTE_EXT_NG (1 << 11) /* v6 */
|
||||
|
||||
/*
|
||||
* - small page
|
||||
*/
|
||||
#define PTE_SMALL_AP_MASK (0xff << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
|
||||
#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
|
||||
#define PTE_SMALL_AP_URW_SRW (0xff << 4)
|
||||
|
||||
#endif
|
|
@ -136,81 +136,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
|||
#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
|
||||
#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
|
||||
|
||||
/*
|
||||
* Hardware page table definitions.
|
||||
*
|
||||
* + Level 1 descriptor (PMD)
|
||||
* - common
|
||||
*/
|
||||
#define PMD_TYPE_MASK (3 << 0)
|
||||
#define PMD_TYPE_FAULT (0 << 0)
|
||||
#define PMD_TYPE_TABLE (1 << 0)
|
||||
#define PMD_TYPE_SECT (2 << 0)
|
||||
#define PMD_BIT4 (1 << 4)
|
||||
#define PMD_DOMAIN(x) ((x) << 5)
|
||||
#define PMD_PROTECTION (1 << 9) /* v5 */
|
||||
/*
|
||||
* - section
|
||||
*/
|
||||
#define PMD_SECT_BUFFERABLE (1 << 2)
|
||||
#define PMD_SECT_CACHEABLE (1 << 3)
|
||||
#define PMD_SECT_AP_WRITE (1 << 10)
|
||||
#define PMD_SECT_AP_READ (1 << 11)
|
||||
#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
|
||||
#define PMD_SECT_APX (1 << 15) /* v6 */
|
||||
#define PMD_SECT_S (1 << 16) /* v6 */
|
||||
#define PMD_SECT_nG (1 << 17) /* v6 */
|
||||
#define PMD_SECT_SUPER (1 << 18) /* v6 */
|
||||
|
||||
#define PMD_SECT_UNCACHED (0)
|
||||
#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
|
||||
#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
||||
#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
|
||||
|
||||
/*
|
||||
* - coarse table (not used)
|
||||
*/
|
||||
|
||||
/*
|
||||
* + Level 2 descriptor (PTE)
|
||||
* - common
|
||||
*/
|
||||
#define PTE_TYPE_MASK (3 << 0)
|
||||
#define PTE_TYPE_FAULT (0 << 0)
|
||||
#define PTE_TYPE_LARGE (1 << 0)
|
||||
#define PTE_TYPE_SMALL (2 << 0)
|
||||
#define PTE_TYPE_EXT (3 << 0) /* v5 */
|
||||
#define PTE_BUFFERABLE (1 << 2)
|
||||
#define PTE_CACHEABLE (1 << 3)
|
||||
|
||||
/*
|
||||
* - extended small page/tiny page
|
||||
*/
|
||||
#define PTE_EXT_XN (1 << 0) /* v6 */
|
||||
#define PTE_EXT_AP_MASK (3 << 4)
|
||||
#define PTE_EXT_AP0 (1 << 4)
|
||||
#define PTE_EXT_AP1 (2 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRO (0 << 4)
|
||||
#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
|
||||
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
|
||||
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
|
||||
#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
|
||||
#define PTE_EXT_APX (1 << 9) /* v6 */
|
||||
#define PTE_EXT_SHARED (1 << 10) /* v6 */
|
||||
#define PTE_EXT_NG (1 << 11) /* v6 */
|
||||
|
||||
/*
|
||||
* - small page
|
||||
*/
|
||||
#define PTE_SMALL_AP_MASK (0xff << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
|
||||
#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
|
||||
#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
|
||||
#define PTE_SMALL_AP_URW_SRW (0xff << 4)
|
||||
|
||||
/*
|
||||
* "Linux" PTE definitions.
|
||||
*
|
||||
|
@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/domain.h>
|
||||
|
||||
#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
|
||||
#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
|
||||
|
||||
/*
|
||||
* The following macros handle the cache and bufferable bits...
|
||||
*/
|
||||
|
|
|
@ -19,6 +19,14 @@
|
|||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
|
||||
#include <linux/pagemap.h>
|
||||
#include <asm-generic/tlb.h>
|
||||
|
||||
#else /* !CONFIG_MMU */
|
||||
|
||||
#include <asm/pgalloc.h>
|
||||
|
||||
/*
|
||||
|
@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
|
|||
|
||||
#define tlb_migrate_finish(mm) do { } while (0)
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
#endif
|
||||
|
|
|
@ -11,6 +11,13 @@
|
|||
#define _ASMARM_TLBFLUSH_H
|
||||
|
||||
#include <linux/config.h>
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
|
||||
#define tlb_flush(tlb) ((void) tlb)
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
#include <asm/glue.h>
|
||||
|
||||
#define TLB_V3_PAGE (1 << 0)
|
||||
|
@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte
|
|||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
#endif
|
||||
|
|
|
@ -8,8 +8,8 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef ASMARM_CLOCK_H
|
||||
#define ASMARM_CLOCK_H
|
||||
#ifndef __LINUX_CLK_H
|
||||
#define __LINUX_CLK_H
|
||||
|
||||
struct device;
|
||||
|
||||
|
|
Loading…
Reference in a new issue