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perf/x86/intel: Add Crestmont PMU
The Grand Ridge and Sierra Forest are successors to Snow Ridge. They both have Crestmont core. From the core PMU's perspective, they are similar to the e-core of MTL. The only difference is the LBR event logging feature, which will be implemented in the following patches. Create a non-hybrid PMU setup for Grand Ridge and Sierra Forest. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lore.kernel.org/r/20230522113040.2329924-1-kan.liang@linux.intel.com
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535445621a
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3 changed files with 60 additions and 3 deletions
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@ -2129,6 +2129,17 @@ static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
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EVENT_EXTRA_END
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};
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EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
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EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
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static struct attribute *cmt_events_attrs[] = {
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EVENT_PTR(td_fe_bound_tnt),
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EVENT_PTR(td_retiring_cmt),
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EVENT_PTR(td_bad_spec_cmt),
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EVENT_PTR(td_be_bound_tnt),
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NULL
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};
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static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
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@ -4840,6 +4851,8 @@ PMU_FORMAT_ATTR(ldlat, "config1:0-15");
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PMU_FORMAT_ATTR(frontend, "config1:0-23");
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PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
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static struct attribute *intel_arch3_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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@ -4870,6 +4883,13 @@ static struct attribute *slm_format_attr[] = {
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NULL
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};
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static struct attribute *cmt_format_attr[] = {
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&format_attr_offcore_rsp.attr,
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&format_attr_ldlat.attr,
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&format_attr_snoop_rsp.attr,
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NULL
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};
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static struct attribute *skl_format_attr[] = {
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&format_attr_frontend.attr,
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NULL,
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@ -5649,7 +5669,6 @@ static struct attribute *adl_hybrid_extra_attr[] = {
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NULL
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};
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PMU_FORMAT_ATTR_SHOW(snoop_rsp, "config1:0-63");
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FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small);
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static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
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@ -6197,6 +6216,37 @@ __init int intel_pmu_init(void)
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name = "gracemont";
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break;
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case INTEL_FAM6_ATOM_CRESTMONT:
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case INTEL_FAM6_ATOM_CRESTMONT_X:
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x86_pmu.mid_ack = true;
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memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
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sizeof(hw_cache_extra_regs));
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hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
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x86_pmu.event_constraints = intel_slm_event_constraints;
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x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints;
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x86_pmu.extra_regs = intel_cmt_extra_regs;
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x86_pmu.pebs_aliases = NULL;
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x86_pmu.pebs_prec_dist = true;
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x86_pmu.lbr_pt_coexist = true;
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x86_pmu.pebs_block = true;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
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intel_pmu_pebs_data_source_cmt();
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x86_pmu.pebs_latency_data = mtl_latency_data_small;
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x86_pmu.get_event_constraints = cmt_get_event_constraints;
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x86_pmu.limit_period = spr_limit_period;
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td_attr = cmt_events_attrs;
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mem_attr = grt_mem_attrs;
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extra_attr = cmt_format_attr;
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pr_cont("Crestmont events, ");
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name = "crestmont";
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break;
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case INTEL_FAM6_WESTMERE:
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case INTEL_FAM6_WESTMERE_EP:
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case INTEL_FAM6_WESTMERE_EX:
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@ -144,7 +144,7 @@ void __init intel_pmu_pebs_data_source_adl(void)
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__intel_pmu_pebs_data_source_grt(data_source);
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}
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static void __init intel_pmu_pebs_data_source_cmt(u64 *data_source)
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static void __init __intel_pmu_pebs_data_source_cmt(u64 *data_source)
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{
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data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
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data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
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@ -164,7 +164,12 @@ void __init intel_pmu_pebs_data_source_mtl(void)
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data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
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memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
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intel_pmu_pebs_data_source_cmt(data_source);
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__intel_pmu_pebs_data_source_cmt(data_source);
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}
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void __init intel_pmu_pebs_data_source_cmt(void)
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{
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__intel_pmu_pebs_data_source_cmt(pebs_data_source);
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}
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static u64 precise_store_data(u64 status)
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@ -1606,6 +1606,8 @@ void intel_pmu_pebs_data_source_grt(void);
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void intel_pmu_pebs_data_source_mtl(void);
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void intel_pmu_pebs_data_source_cmt(void);
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int intel_pmu_setup_lbr_filter(struct perf_event *event);
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void intel_pt_interrupt(void);
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