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clk: at91: add sam9x60 PLL driver
The PLLs on the sam9x60 (PLLA and USB PLL) use a different register set and programming model than the previous SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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3 changed files with 337 additions and 0 deletions
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@ -14,6 +14,7 @@ obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
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obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
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obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
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obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
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obj-$(CONFIG_HAVE_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
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obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o
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obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
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obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
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330
drivers/clk/at91/clk-sam9x60-pll.c
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330
drivers/clk/at91/clk-sam9x60-pll.c
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@ -0,0 +1,330 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Microchip Technology Inc.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define PMC_PLL_CTRL0 0xc
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#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
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#define PMC_PLL_CTRL0_ENPLL BIT(28)
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#define PMC_PLL_CTRL0_ENPLLCK BIT(29)
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#define PMC_PLL_CTRL0_ENLOCK BIT(31)
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#define PMC_PLL_CTRL1 0x10
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#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
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#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
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#define PMC_PLL_ACR 0x18
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#define PMC_PLL_ACR_DEFAULT 0x1b040010UL
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#define PMC_PLL_ACR_UTMIVR BIT(12)
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#define PMC_PLL_ACR_UTMIBG BIT(13)
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#define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24)
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#define PMC_PLL_UPDT 0x1c
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#define PMC_PLL_UPDT_UPDATE BIT(8)
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#define PMC_PLL_ISR0 0xec
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#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
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#define UPLL_DIV 2
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#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
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#define PLL_MAX_ID 1
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struct sam9x60_pll {
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struct clk_hw hw;
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struct regmap *regmap;
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spinlock_t *lock;
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const struct clk_pll_characteristics *characteristics;
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u32 frac;
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u8 id;
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u8 div;
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u16 mul;
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};
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#define to_sam9x60_pll(hw) container_of(hw, struct sam9x60_pll, hw)
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static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
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{
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unsigned int status;
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regmap_read(regmap, PMC_PLL_ISR0, &status);
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return !!(status & BIT(id));
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}
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static int sam9x60_pll_prepare(struct clk_hw *hw)
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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struct regmap *regmap = pll->regmap;
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unsigned long flags;
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u8 div;
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u16 mul;
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u32 val;
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spin_lock_irqsave(pll->lock, flags);
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regmap_write(regmap, PMC_PLL_UPDT, pll->id);
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regmap_read(regmap, PMC_PLL_CTRL0, &val);
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div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
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regmap_read(regmap, PMC_PLL_CTRL1, &val);
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mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
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if (sam9x60_pll_ready(regmap, pll->id) &&
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(div == pll->div && mul == pll->mul)) {
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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/* Recommended value for PMC_PLL_ACR */
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val = PMC_PLL_ACR_DEFAULT;
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regmap_write(regmap, PMC_PLL_ACR, val);
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regmap_write(regmap, PMC_PLL_CTRL1,
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FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
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if (pll->characteristics->upll) {
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/* Enable the UTMI internal bandgap */
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val |= PMC_PLL_ACR_UTMIBG;
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regmap_write(regmap, PMC_PLL_ACR, val);
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udelay(10);
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/* Enable the UTMI internal regulator */
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val |= PMC_PLL_ACR_UTMIVR;
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regmap_write(regmap, PMC_PLL_ACR, val);
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udelay(10);
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}
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regmap_update_bits(regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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regmap_write(regmap, PMC_PLL_CTRL0,
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PMC_PLL_CTRL0_ENLOCK | PMC_PLL_CTRL0_ENPLL |
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PMC_PLL_CTRL0_ENPLLCK | pll->div);
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regmap_update_bits(regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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while (!sam9x60_pll_ready(regmap, pll->id))
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cpu_relax();
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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static int sam9x60_pll_is_prepared(struct clk_hw *hw)
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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return sam9x60_pll_ready(pll->regmap, pll->id);
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}
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static void sam9x60_pll_unprepare(struct clk_hw *hw)
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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unsigned long flags;
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spin_lock_irqsave(pll->lock, flags);
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regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id);
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regmap_update_bits(pll->regmap, PMC_PLL_CTRL0,
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PMC_PLL_CTRL0_ENPLLCK, 0);
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regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, PMC_PLL_CTRL0_ENPLL, 0);
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if (pll->characteristics->upll)
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regmap_update_bits(pll->regmap, PMC_PLL_ACR,
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PMC_PLL_ACR_UTMIBG | PMC_PLL_ACR_UTMIVR, 0);
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regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
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PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static unsigned long sam9x60_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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return (parent_rate * (pll->mul + 1)) / (pll->div + 1);
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}
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static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
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unsigned long rate,
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unsigned long parent_rate,
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bool update)
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{
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const struct clk_pll_characteristics *characteristics =
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pll->characteristics;
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unsigned long bestremainder = ULONG_MAX;
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unsigned long maxdiv, mindiv, tmpdiv;
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long bestrate = -ERANGE;
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unsigned long bestdiv = 0;
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unsigned long bestmul = 0;
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unsigned long bestfrac = 0;
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if (rate < characteristics->output[0].min ||
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rate > characteristics->output[0].max)
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return -ERANGE;
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if (!pll->characteristics->upll) {
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mindiv = parent_rate / rate;
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if (mindiv < 2)
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mindiv = 2;
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maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX, rate);
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if (maxdiv > PLL_DIV_MAX)
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maxdiv = PLL_DIV_MAX;
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} else {
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mindiv = maxdiv = UPLL_DIV;
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}
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for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
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unsigned long remainder;
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unsigned long tmprate;
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unsigned long tmpmul;
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unsigned long tmpfrac = 0;
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/*
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* Calculate the multiplier associated with the current
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* divider that provide the closest rate to the requested one.
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*/
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tmpmul = mult_frac(rate, tmpdiv, parent_rate);
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tmprate = mult_frac(parent_rate, tmpmul, tmpdiv);
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remainder = rate - tmprate;
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if (remainder) {
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tmpfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * tmpdiv * (1 << 22),
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parent_rate);
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tmprate += DIV_ROUND_CLOSEST_ULL((u64)tmpfrac * parent_rate,
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tmpdiv * (1 << 22));
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if (tmprate > rate)
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remainder = tmprate - rate;
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else
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remainder = rate - tmprate;
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}
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/*
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* Compare the remainder with the best remainder found until
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* now and elect a new best multiplier/divider pair if the
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* current remainder is smaller than the best one.
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*/
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if (remainder < bestremainder) {
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bestremainder = remainder;
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bestdiv = tmpdiv;
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bestmul = tmpmul;
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bestrate = tmprate;
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bestfrac = tmpfrac;
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}
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/* We've found a perfect match! */
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if (!remainder)
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break;
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}
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/* Check if bestrate is a valid output rate */
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if (bestrate < characteristics->output[0].min &&
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bestrate > characteristics->output[0].max)
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return -ERANGE;
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if (update) {
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pll->div = bestdiv - 1;
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pll->mul = bestmul - 1;
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pll->frac = bestfrac;
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}
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return bestrate;
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}
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static long sam9x60_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false);
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}
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static int sam9x60_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true);
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}
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static const struct clk_ops pll_ops = {
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.prepare = sam9x60_pll_prepare,
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.unprepare = sam9x60_pll_unprepare,
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.is_prepared = sam9x60_pll_is_prepared,
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.recalc_rate = sam9x60_pll_recalc_rate,
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.round_rate = sam9x60_pll_round_rate,
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.set_rate = sam9x60_pll_set_rate,
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};
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struct clk_hw * __init
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sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics)
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{
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struct sam9x60_pll *pll;
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struct clk_hw *hw;
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struct clk_init_data init;
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unsigned int pllr;
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int ret;
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if (id > PLL_MAX_ID)
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return ERR_PTR(-EINVAL);
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &pll_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_SET_RATE_GATE;
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pll->id = id;
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pll->hw.init = &init;
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pll->characteristics = characteristics;
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pll->regmap = regmap;
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pll->lock = lock;
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regmap_write(regmap, PMC_PLL_UPDT, id);
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regmap_read(regmap, PMC_PLL_CTRL0, &pllr);
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pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr);
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regmap_read(regmap, PMC_PLL_CTRL1, &pllr);
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pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr);
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hw = &pll->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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@ -69,6 +69,7 @@ struct clk_pll_characteristics {
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struct clk_range *output;
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u16 *icpll;
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u8 *out;
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u8 upll : 1;
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};
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struct clk_programmable_layout {
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@ -169,6 +170,11 @@ struct clk_hw * __init
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at91_clk_register_plldiv(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics);
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struct clk_hw * __init
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at91_clk_register_programmable(struct regmap *regmap, const char *name,
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const char **parent_names, u8 num_parents, u8 id,
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