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[media] rc: sunxi-cir: Add support for the larger fifo found on sun5i and sun6i
Add support for the larger fifo found on sun5i and sun6i, having a separate compatible for the ir found on sun5i & sun6i also is useful if we ever want to add ir transmit support, because the sun5i & sun6i version do not have transmit support. Note this commits also adds checking for the end-of-packet interrupt flag (which was already enabled), as the fifo-data-available interrupt flag only gets set when the trigger-level is exceeded. So far we've been getting away with not doing this because of the low trigger-level, but this is something which we should have done since day one. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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parent
44f8af6846
commit
a4bca4c7ad
2 changed files with 13 additions and 10 deletions
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@ -1,7 +1,7 @@
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Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
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Required properties:
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- compatible : should be "allwinner,sun4i-a10-ir";
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- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
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- clocks : list of clock specifiers, corresponding to
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entries in clock-names property;
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- clock-names : should contain "apb" and "ir" entries;
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@ -56,12 +56,12 @@
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#define REG_RXINT_RAI_EN BIT(4)
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/* Rx FIFO available byte level */
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#define REG_RXINT_RAL(val) (((val) << 8) & (GENMASK(11, 8)))
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#define REG_RXINT_RAL(val) ((val) << 8)
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/* Rx Interrupt Status */
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#define SUNXI_IR_RXSTA_REG 0x30
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/* RX FIFO Get Available Counter */
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#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (GENMASK(5, 0)))
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#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
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/* Clear all interrupt status value */
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#define REG_RXSTA_CLEARALL 0xff
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@ -72,10 +72,6 @@
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/* CIR_REG register idle threshold */
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#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
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/* Hardware supported fifo size */
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#define SUNXI_IR_FIFO_SIZE 16
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/* How many messages in FIFO trigger IRQ */
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#define TRIGGER_LEVEL 8
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/* Required frequency for IR0 or IR1 clock in CIR mode */
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#define SUNXI_IR_BASE_CLK 8000000
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/* Frequency after IR internal divider */
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@ -94,6 +90,7 @@ struct sunxi_ir {
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struct rc_dev *rc;
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void __iomem *base;
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int irq;
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int fifo_size;
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struct clk *clk;
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struct clk *apb_clk;
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struct reset_control *rst;
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@ -115,11 +112,11 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
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/* clean all pending statuses */
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writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
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if (status & REG_RXINT_RAI_EN) {
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if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
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/* How many messages in fifo */
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rc = REG_RXSTA_GET_AC(status);
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/* Sanity check */
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rc = rc > SUNXI_IR_FIFO_SIZE ? SUNXI_IR_FIFO_SIZE : rc;
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rc = rc > ir->fifo_size ? ir->fifo_size : rc;
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/* If we have data */
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for (cnt = 0; cnt < rc; cnt++) {
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/* for each bit in fifo */
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@ -156,6 +153,11 @@ static int sunxi_ir_probe(struct platform_device *pdev)
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if (!ir)
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return -ENOMEM;
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if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
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ir->fifo_size = 64;
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else
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ir->fifo_size = 16;
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/* Clock */
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ir->apb_clk = devm_clk_get(dev, "apb");
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if (IS_ERR(ir->apb_clk)) {
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@ -271,7 +273,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
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* level
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*/
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writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
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REG_RXINT_RAI_EN | REG_RXINT_RAL(TRIGGER_LEVEL - 1),
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REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
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ir->base + SUNXI_IR_RXINT_REG);
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/* Enable IR Module */
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@ -319,6 +321,7 @@ static int sunxi_ir_remove(struct platform_device *pdev)
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static const struct of_device_id sunxi_ir_match[] = {
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{ .compatible = "allwinner,sun4i-a10-ir", },
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{ .compatible = "allwinner,sun5i-a13-ir", },
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{},
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};
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