drm/i915: rename/remove CNL registers
Remove registers that are not used anymore due to CNL removal and rename those that are. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-25-lucas.demarchi@intel.com
This commit is contained in:
Lucas De Marchi
parent
5dae69a9fd
commit
a4d082fc19
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@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
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/*
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* CNL/ICL Port/COMBO-PHY Registers
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* ICL Port/COMBO-PHY Registers
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*/
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#define _ICL_COMBOPHY_A 0x162000
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#define _ICL_COMBOPHY_B 0x6C000
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@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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_RKL_COMBOPHY_D, \
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_ADL_COMBOPHY_E)
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/* CNL/ICL Port CL_DW registers */
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/* ICL Port CL_DW registers */
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#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
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4 * (dw))
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#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
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#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
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#define CL_POWER_DOWN_ENABLE (1 << 4)
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#define SUS_CLOCK_CONFIG (3 << 0)
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@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
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#define ICL_LANE_ENABLE_AUX (1 << 0)
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/* CNL/ICL Port COMP_DW registers */
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/* ICL Port COMP_DW registers */
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#define _ICL_PORT_COMP 0x100
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#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
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_ICL_PORT_COMP + 4 * (dw))
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#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
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#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
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#define COMP_INIT (1 << 31)
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#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
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#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
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#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
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#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
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#define PROCESS_INFO_DOT_0 (0 << 26)
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#define PROCESS_INFO_DOT_1 (1 << 26)
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@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
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#define IREFGEN (1 << 24)
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#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
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#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
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#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
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#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
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/* CNL/ICL Port PCS registers */
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#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
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#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
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#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
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#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
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#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
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#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
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#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
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#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
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#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
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#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
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#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
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_CNL_PORT_PCS_DW1_GRP_AE, \
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_CNL_PORT_PCS_DW1_GRP_B, \
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_CNL_PORT_PCS_DW1_GRP_C, \
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_CNL_PORT_PCS_DW1_GRP_D, \
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_CNL_PORT_PCS_DW1_GRP_AE, \
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_CNL_PORT_PCS_DW1_GRP_F))
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#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
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_CNL_PORT_PCS_DW1_LN0_AE, \
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_CNL_PORT_PCS_DW1_LN0_B, \
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_CNL_PORT_PCS_DW1_LN0_C, \
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_CNL_PORT_PCS_DW1_LN0_D, \
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_CNL_PORT_PCS_DW1_LN0_AE, \
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_CNL_PORT_PCS_DW1_LN0_F))
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/* ICL Port PCS registers */
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#define _ICL_PORT_PCS_AUX 0x300
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#define _ICL_PORT_PCS_GRP 0x600
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#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
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@ -1998,34 +1967,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define LATENCY_OPTIM_MASK (0x3 << 2)
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#define LATENCY_OPTIM_VAL(x) ((x) << 2)
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/* CNL/ICL Port TX registers */
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#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
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#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
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#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
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#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
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#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
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#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
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#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
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#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
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#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
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#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
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#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
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_CNL_PORT_TX_AE_GRP_OFFSET, \
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_CNL_PORT_TX_B_GRP_OFFSET, \
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_CNL_PORT_TX_B_GRP_OFFSET, \
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_CNL_PORT_TX_D_GRP_OFFSET, \
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_CNL_PORT_TX_AE_GRP_OFFSET, \
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_CNL_PORT_TX_F_GRP_OFFSET) + \
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4 * (dw))
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#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
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_CNL_PORT_TX_AE_LN0_OFFSET, \
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_CNL_PORT_TX_B_LN0_OFFSET, \
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_CNL_PORT_TX_B_LN0_OFFSET, \
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_CNL_PORT_TX_D_LN0_OFFSET, \
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_CNL_PORT_TX_AE_LN0_OFFSET, \
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_CNL_PORT_TX_F_LN0_OFFSET) + \
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4 * (dw))
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/* ICL Port TX registers */
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#define _ICL_PORT_TX_AUX 0x380
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#define _ICL_PORT_TX_GRP 0x680
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#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
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@ -2037,8 +1979,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
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_ICL_PORT_TX_LN(ln) + 4 * (dw))
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#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
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#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
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#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
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#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
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#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
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@ -2051,13 +1991,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define RCOMP_SCALAR(x) ((x) << 0)
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#define RCOMP_SCALAR_MASK (0xFF << 0)
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#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
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#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
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#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
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#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
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((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
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_CNL_PORT_TX_DW4_LN0_AE)))
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#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
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#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
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#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
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@ -2070,8 +2003,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define CURSOR_COEFF(x) ((x) << 0)
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#define CURSOR_COEFF_MASK (0x3F << 0)
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#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
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#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
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#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
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#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
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#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
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@ -2083,8 +2014,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define RTERM_SELECT(x) ((x) << 3)
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#define RTERM_SELECT_MASK (0x7 << 3)
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#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
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#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
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#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
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#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
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#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
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@ -8191,7 +8120,6 @@ enum {
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#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
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#define CHICKEN_MISC_2 _MMIO(0x42084)
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#define CNL_COMP_PWR_DOWN (1 << 23)
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#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
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#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
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#define GLK_CL2_PWR_DOWN (1 << 12)
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@ -8231,7 +8159,7 @@ enum {
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[TRANSCODER_D] = _CHICKEN_TRANS_D))
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#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
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#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
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#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK and CNL+ */
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#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
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#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
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#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
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#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
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@ -8298,7 +8226,6 @@ enum {
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#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
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#define ICL_DELAY_PMRSP (1 << 22)
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#define MASK_WAKEMEM (1 << 13)
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#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
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#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
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#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
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@ -8319,10 +8246,9 @@ enum {
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#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
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#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
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#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
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#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
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#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
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#define SKL_DSSM _MMIO(0x51004)
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#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
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#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
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#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
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#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
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@ -8421,7 +8347,6 @@ enum {
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/* GEN8 chicken */
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#define HDC_CHICKEN0 _MMIO(0x7300)
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#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
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#define ICL_HDC_MODE _MMIO(0xE5F4)
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#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15)
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#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14)
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@ -9602,7 +9527,6 @@ enum {
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#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
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#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
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#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
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#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4)
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#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
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#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
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@ -9783,15 +9707,12 @@ enum {
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/* HSW/BDW power well */
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#define HSW_PW_CTL_IDX_GLOBAL 15
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/* SKL/BXT/GLK/CNL power wells */
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/* SKL/BXT/GLK power wells */
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#define SKL_PW_CTL_IDX_PW_2 15
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#define SKL_PW_CTL_IDX_PW_1 14
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#define CNL_PW_CTL_IDX_AUX_F 12
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#define CNL_PW_CTL_IDX_AUX_D 11
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#define GLK_PW_CTL_IDX_AUX_C 10
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#define GLK_PW_CTL_IDX_AUX_B 9
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#define GLK_PW_CTL_IDX_AUX_A 8
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#define CNL_PW_CTL_IDX_DDI_F 6
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#define SKL_PW_CTL_IDX_DDI_D 4
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#define SKL_PW_CTL_IDX_DDI_C 3
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#define SKL_PW_CTL_IDX_DDI_B 2
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@ -10189,11 +10110,11 @@ enum skl_power_gate {
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#define TRANS_DDI_BPC_10 (1 << 20)
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#define TRANS_DDI_BPC_6 (2 << 20)
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#define TRANS_DDI_BPC_12 (3 << 20)
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#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */
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#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
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#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
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#define TRANS_DDI_PVSYNC (1 << 17)
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#define TRANS_DDI_PHSYNC (1 << 16)
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#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */
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#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
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#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
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#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
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#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
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@ -10552,17 +10473,6 @@ enum skl_power_gate {
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#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
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#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
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/*
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* CNL Clocks
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*/
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#define DPCLKA_CFGCR0 _MMIO(0x6C200)
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#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
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(port) + 10))
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#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
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(port) * 2)
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#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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/* ICL Clocks */
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#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
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#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
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@ -10800,60 +10710,52 @@ enum skl_power_gate {
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_MG_PLL_TDC_COLDST_BIAS_PORT1, \
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_MG_PLL_TDC_COLDST_BIAS_PORT2)
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#define _CNL_DPLL0_CFGCR0 0x6C000
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#define _CNL_DPLL1_CFGCR0 0x6C080
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#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
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#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
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#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
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#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
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#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
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#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
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#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
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#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
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#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
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#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
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#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
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#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
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#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
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#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
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#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
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#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
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#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
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#define _CNL_DPLL0_CFGCR1 0x6C004
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#define _CNL_DPLL1_CFGCR1 0x6C084
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#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
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#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
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#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
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#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
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#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
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#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
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#define DPLL_CFGCR1_KDIV_SHIFT (6)
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#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
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#define DPLL_CFGCR1_KDIV_1 (1 << 6)
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#define DPLL_CFGCR1_KDIV_2 (2 << 6)
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#define DPLL_CFGCR1_KDIV_3 (4 << 6)
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#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
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||||
#define DPLL_CFGCR1_PDIV_SHIFT (2)
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#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
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||||
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
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#define DPLL_CFGCR1_PDIV_3 (2 << 2)
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#define DPLL_CFGCR1_PDIV_5 (4 << 2)
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#define DPLL_CFGCR1_PDIV_7 (8 << 2)
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||||
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
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||||
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
|
||||
#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
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||||
#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
|
||||
|
||||
#define _ICL_DPLL0_CFGCR0 0x164000
|
||||
#define _ICL_DPLL1_CFGCR0 0x164080
|
||||
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
|
||||
_ICL_DPLL1_CFGCR0)
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||||
#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
|
||||
#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
|
||||
#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
|
||||
#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
|
||||
#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
|
||||
#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
|
||||
|
||||
#define _ICL_DPLL0_CFGCR1 0x164004
|
||||
#define _ICL_DPLL1_CFGCR1 0x164084
|
||||
#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
|
||||
_ICL_DPLL1_CFGCR1)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
|
||||
#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
|
||||
#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
|
||||
#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
|
||||
#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_SHIFT (6)
|
||||
#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
|
||||
#define DPLL_CFGCR1_KDIV_1 (1 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_2 (2 << 6)
|
||||
#define DPLL_CFGCR1_KDIV_3 (4 << 6)
|
||||
#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
|
||||
#define DPLL_CFGCR1_PDIV_SHIFT (2)
|
||||
#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
|
||||
#define DPLL_CFGCR1_PDIV_2 (1 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_3 (2 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_5 (4 << 2)
|
||||
#define DPLL_CFGCR1_PDIV_7 (8 << 2)
|
||||
#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
|
||||
#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
|
||||
#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
|
||||
|
||||
#define _TGL_DPLL0_CFGCR0 0x164284
|
||||
#define _TGL_DPLL1_CFGCR0 0x16428C
|
||||
|
|
|
|||
|
|
@ -367,7 +367,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
|
|||
info->display.has_dmc = 0;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 10 &&
|
||||
(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
|
||||
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
|
||||
info->display.has_dsc = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue