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synced 2024-08-24 01:41:39 +00:00
drm/i915: Make for_each_engine_masked work on intel_gt
Medium term goal is to eliminate the i915->engine[] array and to get there we have recently introduced equivalent array in intel_gt. Now we need to migrate the code further towards this state. This next step is to eliminate usage of i915->engines[] from the for_each_engine_masked iterator. For this to work we also need to use engine->id as index when populating the gt->engine[] array and adjust the default engine set indexing to use engine->legacy_idx instead of assuming gt->engines[] indexing. v2: * Populate gt->engine[] earlier. * Check that we don't duplicate engine->legacy_idx v3: * Work around the initialization order issue between default_engines() and intel_engines_driver_register() which sets engine->legacy_idx for now. It will be fixed properly later. v4: * Merge with forgotten v2.5. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191017161852.8836-1-tvrtko.ursulin@linux.intel.com
This commit is contained in:
parent
1dfffa0051
commit
a50134b198
11 changed files with 37 additions and 32 deletions
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@ -203,15 +203,22 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
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for_each_engine(engine, gt, id) {
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struct intel_context *ce;
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if (engine->legacy_idx == INVALID_ENGINE)
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continue;
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GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
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GEM_BUG_ON(e->engines[engine->legacy_idx]);
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ce = intel_context_create(ctx, engine);
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if (IS_ERR(ce)) {
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__free_engines(e, id);
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__free_engines(e, e->num_engines + 1);
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return ERR_CAST(ce);
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}
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e->engines[id] = ce;
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e->num_engines = id + 1;
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e->engines[engine->legacy_idx] = ce;
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e->num_engines = max(e->num_engines, engine->legacy_idx);
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}
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e->num_engines++;
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return e;
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}
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@ -277,6 +277,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
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BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
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BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
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if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
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return -EINVAL;
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if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
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return -EINVAL;
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@ -293,6 +296,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
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BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
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engine->id = id;
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engine->legacy_idx = INVALID_ENGINE;
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engine->mask = BIT(id);
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engine->i915 = gt->i915;
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engine->gt = gt;
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@ -328,6 +332,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
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intel_engine_sanitize_mmio(engine);
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gt->engine_class[info->class][info->instance] = engine;
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gt->engine[id] = engine;
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intel_engine_add_user(engine);
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gt->i915->engine[id] = engine;
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@ -148,6 +148,7 @@ enum intel_engine_id {
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VECS1,
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#define _VECS(n) (VECS0 + (n))
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I915_NUM_ENGINES
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#define INVALID_ENGINE ((enum intel_engine_id)-1)
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};
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struct st_preempt_hang {
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@ -160,10 +160,10 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
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};
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if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
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return -1;
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return INVALID_ENGINE;
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if (GEM_DEBUG_WARN_ON(ring->instance >= map[ring->class].max))
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return -1;
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return INVALID_ENGINE;
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return map[ring->class].base + ring->instance;
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}
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@ -171,23 +171,15 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
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static void add_legacy_ring(struct legacy_ring *ring,
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struct intel_engine_cs *engine)
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{
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int idx;
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if (engine->gt != ring->gt || engine->class != ring->class) {
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ring->gt = engine->gt;
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ring->class = engine->class;
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ring->instance = 0;
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}
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idx = legacy_ring_idx(ring);
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if (unlikely(idx == -1))
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return;
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GEM_BUG_ON(idx >= ARRAY_SIZE(ring->gt->engine));
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ring->gt->engine[idx] = engine;
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ring->instance++;
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engine->legacy_idx = idx;
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engine->legacy_idx = legacy_ring_idx(ring);
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if (engine->legacy_idx != INVALID_ENGINE)
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ring->instance++;
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}
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void intel_engines_driver_register(struct drm_i915_private *i915)
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@ -186,7 +186,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine_masked(engine, i915, engine_mask, id)
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for_each_engine_masked(engine, gt, engine_mask, id)
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gen8_clear_engine_error_register(engine);
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}
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}
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@ -237,7 +237,7 @@ static void hangcheck_declare_hang(struct intel_gt *gt,
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hung &= ~stuck;
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len = scnprintf(msg, sizeof(msg),
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"%s on ", stuck == hung ? "no progress" : "hang");
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for_each_engine_masked(engine, gt->i915, hung, tmp)
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for_each_engine_masked(engine, gt, hung, tmp)
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len += scnprintf(msg + len, sizeof(msg) - len,
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"%s, ", engine->name);
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msg[len-2] = '\0';
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@ -298,7 +298,7 @@ static int gen6_reset_engines(struct intel_gt *gt,
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intel_engine_mask_t tmp;
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hw_mask = 0;
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for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
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for_each_engine_masked(engine, gt, engine_mask, tmp) {
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GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
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hw_mask |= hw_engine_mask[engine->id];
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}
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@ -432,7 +432,7 @@ static int gen11_reset_engines(struct intel_gt *gt,
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hw_mask = GEN11_GRDOM_FULL;
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} else {
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hw_mask = 0;
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for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
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for_each_engine_masked(engine, gt, engine_mask, tmp) {
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GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
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hw_mask |= hw_engine_mask[engine->id];
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ret = gen11_lock_sfc(engine, &hw_mask);
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@ -451,7 +451,7 @@ static int gen11_reset_engines(struct intel_gt *gt,
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* expiration).
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*/
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if (engine_mask != ALL_ENGINES)
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for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
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for_each_engine_masked(engine, gt, engine_mask, tmp)
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gen11_unlock_sfc(engine);
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return ret;
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@ -510,7 +510,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
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intel_engine_mask_t tmp;
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int ret;
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for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
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for_each_engine_masked(engine, gt, engine_mask, tmp) {
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ret = gen8_engine_reset_prepare(engine);
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if (ret && !reset_non_ready)
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goto skip_reset;
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@ -536,7 +536,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
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ret = gen6_reset_engines(gt, engine_mask, retry);
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skip_reset:
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for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
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for_each_engine_masked(engine, gt, engine_mask, tmp)
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gen8_engine_reset_cancel(engine);
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return ret;
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@ -1206,7 +1206,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
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* single reset fails.
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*/
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if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
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for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
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for_each_engine_masked(engine, gt, engine_mask, tmp) {
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BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
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if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
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>->reset.flags))
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@ -534,7 +534,7 @@ static void clean_execlist(struct intel_vgpu *vgpu,
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struct intel_vgpu_submission *s = &vgpu->submission;
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intel_engine_mask_t tmp;
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for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
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for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
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kfree(s->ring_scan_buffer[engine->id]);
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s->ring_scan_buffer[engine->id] = NULL;
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s->ring_scan_buffer_size[engine->id] = 0;
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@ -548,7 +548,7 @@ static void reset_execlist(struct intel_vgpu *vgpu,
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struct intel_engine_cs *engine;
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intel_engine_mask_t tmp;
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for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
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for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp)
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init_vgpu_execlist(vgpu, engine->id);
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}
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@ -887,7 +887,7 @@ void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
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intel_engine_mask_t tmp;
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/* free the unsubmited workloads in the queues. */
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for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
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for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
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list_for_each_entry_safe(pos, n,
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&s->workload_q_head[engine->id], list) {
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list_del_init(&pos->list);
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@ -590,8 +590,8 @@ static struct active_node *reuse_idle_barrier(struct i915_active *ref, u64 idx)
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int i915_active_acquire_preallocate_barrier(struct i915_active *ref,
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struct intel_engine_cs *engine)
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{
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struct drm_i915_private *i915 = engine->i915;
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intel_engine_mask_t tmp, mask = engine->mask;
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struct intel_gt *gt = engine->gt;
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struct llist_node *pos, *next;
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int err;
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@ -603,7 +603,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref,
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* We can then use the preallocated nodes in
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* i915_active_acquire_barrier()
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*/
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for_each_engine_masked(engine, i915, mask, tmp) {
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for_each_engine_masked(engine, gt, mask, tmp) {
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u64 idx = engine->kernel_context->timeline->fence_context;
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struct active_node *node;
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@ -1415,10 +1415,10 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
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for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
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/* Iterator over subset of engines selected by mask */
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#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
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for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
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#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
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for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
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(tmp__) ? \
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((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
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((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
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0;)
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#define rb_to_uabi_engine(rb) \
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