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idpf: add singleq start_xmit and napi poll
Add the start_xmit, TX and RX napi poll support for the single queue model. Unlike split queue model, single queue uses same queue to post buffer descriptors and completed descriptors. Signed-off-by: Joshua Hay <joshua.a.hay@intel.com> Co-developed-by: Alan Brady <alan.brady@intel.com> Signed-off-by: Alan Brady <alan.brady@intel.com> Co-developed-by: Madhu Chittim <madhu.chittim@intel.com> Signed-off-by: Madhu Chittim <madhu.chittim@intel.com> Co-developed-by: Phani Burra <phani.r.burra@intel.com> Signed-off-by: Phani Burra <phani.r.burra@intel.com> Reviewed-by: Sridhar Samudrala <sridhar.samudrala@intel.com> Reviewed-by: Willem de Bruijn <willemb@google.com> Co-developed-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com> Signed-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Joshua Hay
Tony Nguyen
parent
3a8845af66
commit
a5ab9ee0df
8 changed files with 1290 additions and 31 deletions
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@ -14,6 +14,7 @@ struct idpf_vport_max_q;
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#include <linux/etherdevice.h>
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#include <linux/pci.h>
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#include <linux/bitfield.h>
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#include <linux/sctp.h>
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#include <net/gro.h>
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#include <linux/dim.h>
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@ -280,6 +281,7 @@ enum idpf_vport_flags {
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* @txq_grps: Array of TX queue groups
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* @txq_model: Split queue or single queue queuing model
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* @txqs: Used only in hotpath to get to the right queue very fast
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* @crc_enable: Enable CRC insertion offload
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* @num_rxq: Number of allocated RX queues
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* @num_bufq: Number of allocated buffer queues
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* @rxq_desc_count: RX queue descriptor count. *MUST* have enough descriptors
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@ -326,6 +328,7 @@ struct idpf_vport {
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struct idpf_txq_group *txq_grps;
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u32 txq_model;
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struct idpf_queue **txqs;
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bool crc_enable;
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u16 num_rxq;
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u16 num_bufq;
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@ -534,6 +537,9 @@ struct idpf_vport_config {
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* @vc_state: Virtchnl message state
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* @vc_msg: Virtchnl message buffer
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* @dev_ops: See idpf_dev_ops
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* @num_vfs: Number of allocated VFs through sysfs. PF does not directly talk
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* to VFs but is used to initialize them
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* @crc_enable: Enable CRC insertion offload
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* @req_tx_splitq: TX split or single queue model to request
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* @req_rx_splitq: RX split or single queue model to request
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* @vport_ctrl_lock: Lock to protect the vport control flow
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@ -587,6 +593,8 @@ struct idpf_adapter {
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DECLARE_BITMAP(vc_state, IDPF_VC_NBITS);
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char vc_msg[IDPF_CTLQ_MAX_BUF_LEN];
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struct idpf_dev_ops dev_ops;
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int num_vfs;
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bool crc_enable;
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bool req_tx_splitq;
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bool req_rx_splitq;
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@ -848,5 +856,7 @@ int idpf_send_create_vport_msg(struct idpf_adapter *adapter,
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struct idpf_vport_max_q *max_q);
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int idpf_check_supported_desc_ids(struct idpf_vport *vport);
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int idpf_send_map_unmap_queue_vector_msg(struct idpf_vport *vport, bool map);
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int idpf_send_set_sriov_vfs_msg(struct idpf_adapter *adapter, u16 num_vfs);
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int idpf_sriov_configure(struct pci_dev *pdev, int num_vfs);
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#endif /* !_IDPF_H_ */
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@ -64,6 +64,32 @@ enum idpf_rss_hash {
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#define IDPF_TXD_COMPLQ_QID_S 0
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#define IDPF_TXD_COMPLQ_QID_M GENMASK_ULL(9, 0)
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/* For base mode TX descriptors */
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#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S 23
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#define IDPF_TXD_CTX_QW0_TUNN_L4T_CS_M BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_L4T_CS_S)
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#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_S 19
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#define IDPF_TXD_CTX_QW0_TUNN_DECTTL_M \
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(0xFULL << IDPF_TXD_CTX_QW0_TUNN_DECTTL_S)
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#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_S 12
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#define IDPF_TXD_CTX_QW0_TUNN_NATLEN_M \
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(0X7FULL << IDPF_TXD_CTX_QW0_TUNN_NATLEN_S)
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#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S 11
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#define IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M \
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BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_S)
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#define IDPF_TXD_CTX_EIP_NOINC_IPID_CONST \
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IDPF_TXD_CTX_QW0_TUNN_EIP_NOINC_M
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#define IDPF_TXD_CTX_QW0_TUNN_NATT_S 9
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#define IDPF_TXD_CTX_QW0_TUNN_NATT_M (0x3ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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#define IDPF_TXD_CTX_UDP_TUNNELING BIT_ULL(IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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#define IDPF_TXD_CTX_GRE_TUNNELING (0x2ULL << IDPF_TXD_CTX_QW0_TUNN_NATT_S)
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S 2
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_M \
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(0x3FULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IPLEN_S)
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S 0
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#define IDPF_TXD_CTX_QW0_TUNN_EXT_IP_M \
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(0x3ULL << IDPF_TXD_CTX_QW0_TUNN_EXT_IP_S)
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#define IDPF_TXD_CTX_QW1_MSS_S 50
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#define IDPF_TXD_CTX_QW1_MSS_M GENMASK_ULL(63, 50)
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#define IDPF_TXD_CTX_QW1_TSO_LEN_S 30
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@ -112,6 +138,27 @@ enum idpf_tx_desc_dtype_value {
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IDPF_TX_DESC_DTYPE_DESC_DONE = 15,
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};
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enum idpf_tx_ctx_desc_cmd_bits {
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IDPF_TX_CTX_DESC_TSO = 0x01,
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IDPF_TX_CTX_DESC_TSYN = 0x02,
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IDPF_TX_CTX_DESC_IL2TAG2 = 0x04,
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IDPF_TX_CTX_DESC_RSVD = 0x08,
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IDPF_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
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IDPF_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
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IDPF_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
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IDPF_TX_CTX_DESC_SWTCH_VSI = 0x30,
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IDPF_TX_CTX_DESC_FILT_AU_EN = 0x40,
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IDPF_TX_CTX_DESC_FILT_AU_EVICT = 0x80,
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IDPF_TX_CTX_DESC_RSVD1 = 0xF00
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};
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enum idpf_tx_desc_len_fields {
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/* Note: These are predefined bit offsets */
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IDPF_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */
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IDPF_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
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IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */
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};
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enum idpf_tx_base_desc_cmd_bits {
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IDPF_TX_DESC_CMD_EOP = BIT(0),
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IDPF_TX_DESC_CMD_RS = BIT(1),
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@ -148,6 +195,16 @@ struct idpf_splitq_tx_compl_desc {
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u8 rsvd; /* Reserved */
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}; /* writeback used with completion queues */
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/* Context descriptors */
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struct idpf_base_tx_ctx_desc {
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struct {
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__le32 tunneling_params;
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__le16 l2tag2;
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__le16 rsvd1;
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} qw0;
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__le64 qw1; /* type_cmd_tlen_mss/rt_hint */
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};
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/* Common cmd field defines for all desc except Flex Flow Scheduler (0x0C) */
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enum idpf_tx_flex_desc_cmd_bits {
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IDPF_TX_FLEX_DESC_CMD_EOP = BIT(0),
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@ -1565,4 +1565,5 @@ static const struct net_device_ops idpf_netdev_ops_splitq = {
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static const struct net_device_ops idpf_netdev_ops_singleq = {
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.ndo_open = idpf_open,
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.ndo_stop = idpf_stop,
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.ndo_start_xmit = idpf_tx_singleq_start,
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};
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@ -133,6 +133,7 @@ static int idpf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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break;
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case IDPF_DEV_ID_VF:
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idpf_vf_dev_ops_init(adapter);
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adapter->crc_enable = true;
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break;
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default:
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err = -ENODEV;
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File diff suppressed because it is too large
Load diff
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@ -1953,7 +1953,7 @@ void idpf_tx_splitq_build_flow_desc(union idpf_tx_flex_desc *desc,
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*
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* Returns 0 if stop is not needed
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*/
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static int idpf_tx_maybe_stop_common(struct idpf_queue *tx_q, unsigned int size)
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int idpf_tx_maybe_stop_common(struct idpf_queue *tx_q, unsigned int size)
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{
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struct netdev_queue *nq;
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@ -2017,8 +2017,8 @@ static int idpf_tx_maybe_stop_splitq(struct idpf_queue *tx_q,
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* to do a register write to update our queue status. We know this can only
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* mean tail here as HW should be owning head for TX.
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*/
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static void idpf_tx_buf_hw_update(struct idpf_queue *tx_q, u32 val,
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bool xmit_more)
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void idpf_tx_buf_hw_update(struct idpf_queue *tx_q, u32 val,
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bool xmit_more)
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{
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struct netdev_queue *nq;
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@ -2041,11 +2041,13 @@ static void idpf_tx_buf_hw_update(struct idpf_queue *tx_q, u32 val,
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/**
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* idpf_tx_desc_count_required - calculate number of Tx descriptors needed
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* @txq: queue to send buffer on
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* @skb: send buffer
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*
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* Returns number of data descriptors needed for this skb.
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*/
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static unsigned int idpf_tx_desc_count_required(struct sk_buff *skb)
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unsigned int idpf_tx_desc_count_required(struct idpf_queue *txq,
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struct sk_buff *skb)
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{
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const struct skb_shared_info *shinfo;
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unsigned int count = 0, i;
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@ -2071,6 +2073,16 @@ static unsigned int idpf_tx_desc_count_required(struct sk_buff *skb)
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count++;
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}
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if (idpf_chk_linearize(skb, txq->tx_max_bufs, count)) {
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if (__skb_linearize(skb))
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return 0;
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count = idpf_size_to_txd_count(skb->len);
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u64_stats_update_begin(&txq->stats_sync);
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u64_stats_inc(&txq->q_stats.tx.linearize);
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u64_stats_update_end(&txq->stats_sync);
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}
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return count;
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}
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@ -2081,8 +2093,8 @@ static unsigned int idpf_tx_desc_count_required(struct sk_buff *skb)
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* @first: original first buffer info buffer for packet
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* @idx: starting point on ring to unwind
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*/
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static void idpf_tx_dma_map_error(struct idpf_queue *txq, struct sk_buff *skb,
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struct idpf_tx_buf *first, u16 idx)
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void idpf_tx_dma_map_error(struct idpf_queue *txq, struct sk_buff *skb,
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struct idpf_tx_buf *first, u16 idx)
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{
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u64_stats_update_begin(&txq->stats_sync);
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u64_stats_inc(&txq->q_stats.tx.dma_map_errs);
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@ -2327,7 +2339,7 @@ static void idpf_tx_splitq_map(struct idpf_queue *tx_q,
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* Returns error (negative) if TSO was requested but cannot be applied to the
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* given skb, 0 if TSO does not apply to the given skb, or 1 otherwise.
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*/
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static int idpf_tso(struct sk_buff *skb, struct idpf_tx_offload_params *off)
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int idpf_tso(struct sk_buff *skb, struct idpf_tx_offload_params *off)
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{
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const struct skb_shared_info *shinfo = skb_shinfo(skb);
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union {
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@ -2488,8 +2500,8 @@ static bool __idpf_chk_linearize(struct sk_buff *skb, unsigned int max_bufs)
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* E.g.: a packet with 7 fragments can require 9 DMA transactions; 1 for TSO
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* header, 1 for segment payload, and then 7 for the fragments.
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*/
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static bool idpf_chk_linearize(struct sk_buff *skb, unsigned int max_bufs,
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unsigned int count)
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bool idpf_chk_linearize(struct sk_buff *skb, unsigned int max_bufs,
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unsigned int count)
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{
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if (likely(count < max_bufs))
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return false;
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@ -2527,8 +2539,7 @@ idpf_tx_splitq_get_ctx_desc(struct idpf_queue *txq)
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* @tx_q: queue to send buffer on
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* @skb: pointer to skb
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*/
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static netdev_tx_t idpf_tx_drop_skb(struct idpf_queue *tx_q,
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struct sk_buff *skb)
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netdev_tx_t idpf_tx_drop_skb(struct idpf_queue *tx_q, struct sk_buff *skb)
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{
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u64_stats_update_begin(&tx_q->stats_sync);
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u64_stats_inc(&tx_q->q_stats.tx.skb_drops);
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@ -2556,16 +2567,9 @@ static netdev_tx_t idpf_tx_splitq_frame(struct sk_buff *skb,
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unsigned int count;
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int tso;
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count = idpf_tx_desc_count_required(skb);
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if (idpf_chk_linearize(skb, tx_q->tx_max_bufs, count)) {
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if (__skb_linearize(skb))
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return idpf_tx_drop_skb(tx_q, skb);
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count = idpf_size_to_txd_count(skb->len);
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u64_stats_update_begin(&tx_q->stats_sync);
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u64_stats_inc(&tx_q->q_stats.tx.linearize);
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u64_stats_update_end(&tx_q->stats_sync);
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}
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count = idpf_tx_desc_count_required(tx_q, skb);
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if (unlikely(!count))
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return idpf_tx_drop_skb(tx_q, skb);
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tso = idpf_tso(skb, &tx_params.offload);
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if (unlikely(tso < 0))
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@ -2683,8 +2687,7 @@ netdev_tx_t idpf_tx_splitq_start(struct sk_buff *skb,
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* skb_set_hash based on PTYPE as parsed by HW Rx pipeline and is part of
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* Rx desc.
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*/
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static enum pkt_hash_types
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idpf_ptype_to_htype(const struct idpf_rx_ptype_decoded *decoded)
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enum pkt_hash_types idpf_ptype_to_htype(const struct idpf_rx_ptype_decoded *decoded)
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{
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if (!decoded->known)
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return PKT_HASH_TYPE_NONE;
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@ -2944,8 +2947,8 @@ static int idpf_rx_process_skb_fields(struct idpf_queue *rxq,
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* It will just attach the page as a frag to the skb.
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* The function will then update the page offset.
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*/
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static void idpf_rx_add_frag(struct idpf_rx_buf *rx_buf, struct sk_buff *skb,
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unsigned int size)
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void idpf_rx_add_frag(struct idpf_rx_buf *rx_buf, struct sk_buff *skb,
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unsigned int size)
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{
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skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buf->page,
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rx_buf->page_offset, size, rx_buf->truesize);
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@ -2963,9 +2966,9 @@ static void idpf_rx_add_frag(struct idpf_rx_buf *rx_buf, struct sk_buff *skb,
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* data from the current receive descriptor, taking care to set up the
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* skb correctly.
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*/
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static struct sk_buff *idpf_rx_construct_skb(struct idpf_queue *rxq,
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struct idpf_rx_buf *rx_buf,
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unsigned int size)
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struct sk_buff *idpf_rx_construct_skb(struct idpf_queue *rxq,
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struct idpf_rx_buf *rx_buf,
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unsigned int size)
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{
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unsigned int headlen;
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struct sk_buff *skb;
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@ -3595,7 +3598,7 @@ static void idpf_net_dim(struct idpf_q_vector *q_vector)
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* Update the net_dim() algorithm and re-enable the interrupt associated with
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* this vector.
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*/
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static void idpf_vport_intr_update_itr_ena_irq(struct idpf_q_vector *q_vector)
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void idpf_vport_intr_update_itr_ena_irq(struct idpf_q_vector *q_vector)
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{
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u32 intval;
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@ -72,6 +72,12 @@ do { \
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} \
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} while (0)
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#define IDPF_SINGLEQ_BUMP_RING_IDX(q, idx) \
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do { \
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if (unlikely(++(idx) == (q)->desc_count)) \
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idx = 0; \
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} while (0)
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#define IDPF_RX_HDR_SIZE 256
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#define IDPF_RX_BUF_2048 2048
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#define IDPF_RX_BUF_4096 4096
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@ -101,6 +107,10 @@ do { \
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(&(((struct virtchnl2_splitq_rx_buf_desc *)((rxq)->desc_ring))[i]))
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#define IDPF_SPLITQ_RX_BI_DESC(rxq, i) ((((rxq)->ring))[i])
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#define IDPF_BASE_TX_DESC(txq, i) \
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(&(((struct idpf_base_tx_desc *)((txq)->desc_ring))[i]))
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#define IDPF_BASE_TX_CTX_DESC(txq, i) \
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(&(((struct idpf_base_tx_ctx_desc *)((txq)->desc_ring))[i]))
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#define IDPF_SPLITQ_TX_COMPLQ_DESC(txcq, i) \
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(&(((struct idpf_splitq_tx_compl_desc *)((txcq)->desc_ring))[i]))
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@ -136,6 +146,9 @@ do { \
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#define IDPF_TXD_LAST_DESC_CMD (IDPF_TX_DESC_CMD_EOP | IDPF_TX_DESC_CMD_RS)
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#define IDPF_TX_FLAGS_TSO BIT(0)
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#define IDPF_TX_FLAGS_IPV4 BIT(1)
|
||||
#define IDPF_TX_FLAGS_IPV6 BIT(2)
|
||||
#define IDPF_TX_FLAGS_TUNNEL BIT(3)
|
||||
|
||||
union idpf_tx_flex_desc {
|
||||
struct idpf_flex_tx_desc q; /* queue based scheduling */
|
||||
|
|
@ -199,6 +212,8 @@ struct idpf_buf_lifo {
|
|||
/**
|
||||
* struct idpf_tx_offload_params - Offload parameters for a given packet
|
||||
* @tx_flags: Feature flags enabled for this packet
|
||||
* @hdr_offsets: Offset parameter for single queue model
|
||||
* @cd_tunneling: Type of tunneling enabled for single queue model
|
||||
* @tso_len: Total length of payload to segment
|
||||
* @mss: Segment size
|
||||
* @tso_segs: Number of segments to be sent
|
||||
|
|
@ -208,6 +223,9 @@ struct idpf_buf_lifo {
|
|||
struct idpf_tx_offload_params {
|
||||
u32 tx_flags;
|
||||
|
||||
u32 hdr_offsets;
|
||||
u32 cd_tunneling;
|
||||
|
||||
u32 tso_len;
|
||||
u16 mss;
|
||||
u16 tso_segs;
|
||||
|
|
@ -235,6 +253,13 @@ struct idpf_tx_splitq_params {
|
|||
struct idpf_tx_offload_params offload;
|
||||
};
|
||||
|
||||
enum idpf_tx_ctx_desc_eipt_offload {
|
||||
IDPF_TX_CTX_EXT_IP_NONE = 0x0,
|
||||
IDPF_TX_CTX_EXT_IP_IPV6 = 0x1,
|
||||
IDPF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
|
||||
IDPF_TX_CTX_EXT_IP_IPV4 = 0x3
|
||||
};
|
||||
|
||||
/* Checksum offload bits decoded from the receive descriptor. */
|
||||
struct idpf_rx_csum_decoded {
|
||||
u32 l3l4p : 1;
|
||||
|
|
@ -249,6 +274,11 @@ struct idpf_rx_csum_decoded {
|
|||
u32 raw_csum : 16;
|
||||
};
|
||||
|
||||
struct idpf_rx_extracted {
|
||||
unsigned int size;
|
||||
u16 rx_ptype;
|
||||
};
|
||||
|
||||
#define IDPF_TX_COMPLQ_CLEAN_BUDGET 256
|
||||
#define IDPF_TX_MIN_PKT_LEN 17
|
||||
#define IDPF_TX_DESCS_FOR_SKB_DATA_PTR 1
|
||||
|
|
@ -832,6 +862,25 @@ static inline u32 idpf_size_to_txd_count(unsigned int size)
|
|||
return DIV_ROUND_UP(size, IDPF_TX_MAX_DESC_DATA_ALIGNED);
|
||||
}
|
||||
|
||||
/**
|
||||
* idpf_tx_singleq_build_ctob - populate command tag offset and size
|
||||
* @td_cmd: Command to be filled in desc
|
||||
* @td_offset: Offset to be filled in desc
|
||||
* @size: Size of the buffer
|
||||
* @td_tag: td tag to be filled
|
||||
*
|
||||
* Returns the 64 bit value populated with the input parameters
|
||||
*/
|
||||
static inline __le64 idpf_tx_singleq_build_ctob(u64 td_cmd, u64 td_offset,
|
||||
unsigned int size, u64 td_tag)
|
||||
{
|
||||
return cpu_to_le64(IDPF_TX_DESC_DTYPE_DATA |
|
||||
(td_cmd << IDPF_TXD_QW1_CMD_S) |
|
||||
(td_offset << IDPF_TXD_QW1_OFFSET_S) |
|
||||
((u64)size << IDPF_TXD_QW1_TX_BUF_SZ_S) |
|
||||
(td_tag << IDPF_TXD_QW1_L2TAG1_S));
|
||||
}
|
||||
|
||||
void idpf_tx_splitq_build_ctb(union idpf_tx_flex_desc *desc,
|
||||
struct idpf_tx_splitq_params *params,
|
||||
u16 td_cmd, u16 size);
|
||||
|
|
@ -921,17 +970,38 @@ int idpf_vport_queues_alloc(struct idpf_vport *vport);
|
|||
void idpf_vport_queues_rel(struct idpf_vport *vport);
|
||||
void idpf_vport_intr_rel(struct idpf_vport *vport);
|
||||
int idpf_vport_intr_alloc(struct idpf_vport *vport);
|
||||
void idpf_vport_intr_update_itr_ena_irq(struct idpf_q_vector *q_vector);
|
||||
void idpf_vport_intr_deinit(struct idpf_vport *vport);
|
||||
int idpf_vport_intr_init(struct idpf_vport *vport);
|
||||
enum pkt_hash_types idpf_ptype_to_htype(const struct idpf_rx_ptype_decoded *decoded);
|
||||
int idpf_config_rss(struct idpf_vport *vport);
|
||||
int idpf_init_rss(struct idpf_vport *vport);
|
||||
void idpf_deinit_rss(struct idpf_vport *vport);
|
||||
int idpf_rx_bufs_init_all(struct idpf_vport *vport);
|
||||
void idpf_rx_add_frag(struct idpf_rx_buf *rx_buf, struct sk_buff *skb,
|
||||
unsigned int size);
|
||||
struct sk_buff *idpf_rx_construct_skb(struct idpf_queue *rxq,
|
||||
struct idpf_rx_buf *rx_buf,
|
||||
unsigned int size);
|
||||
bool idpf_init_rx_buf_hw_alloc(struct idpf_queue *rxq, struct idpf_rx_buf *buf);
|
||||
void idpf_rx_buf_hw_update(struct idpf_queue *rxq, u32 val);
|
||||
void idpf_tx_buf_hw_update(struct idpf_queue *tx_q, u32 val,
|
||||
bool xmit_more);
|
||||
unsigned int idpf_size_to_txd_count(unsigned int size);
|
||||
netdev_tx_t idpf_tx_drop_skb(struct idpf_queue *tx_q, struct sk_buff *skb);
|
||||
void idpf_tx_dma_map_error(struct idpf_queue *txq, struct sk_buff *skb,
|
||||
struct idpf_tx_buf *first, u16 ring_idx);
|
||||
unsigned int idpf_tx_desc_count_required(struct idpf_queue *txq,
|
||||
struct sk_buff *skb);
|
||||
bool idpf_chk_linearize(struct sk_buff *skb, unsigned int max_bufs,
|
||||
unsigned int count);
|
||||
int idpf_tx_maybe_stop_common(struct idpf_queue *tx_q, unsigned int size);
|
||||
netdev_tx_t idpf_tx_splitq_start(struct sk_buff *skb,
|
||||
struct net_device *netdev);
|
||||
netdev_tx_t idpf_tx_singleq_start(struct sk_buff *skb,
|
||||
struct net_device *netdev);
|
||||
bool idpf_rx_singleq_buf_hw_alloc_all(struct idpf_queue *rxq,
|
||||
u16 cleaned_count);
|
||||
int idpf_tso(struct sk_buff *skb, struct idpf_tx_offload_params *off);
|
||||
|
||||
#endif /* !_IDPF_TXRX_H_ */
|
||||
|
|
|
|||
|
|
@ -2893,6 +2893,8 @@ void idpf_vport_init(struct idpf_vport *vport, struct idpf_vport_max_q *max_q)
|
|||
idpf_vport_calc_num_q_desc(vport);
|
||||
idpf_vport_calc_num_q_groups(vport);
|
||||
idpf_vport_alloc_vec_indexes(vport);
|
||||
|
||||
vport->crc_enable = adapter->crc_enable;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in a new issue