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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: hpet: Work around hardware stupidity x86, build: Disable -fPIE when compiling with CONFIG_CC_STACKPROTECTOR=y x86, cpufeature: Suppress compiler warning with gcc 3.x x86, UV: Fix initialization of max_pnode
This commit is contained in:
commit
a5b617368c
6 changed files with 23 additions and 39 deletions
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@ -74,7 +74,7 @@ endif
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ifdef CONFIG_CC_STACKPROTECTOR
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ifdef CONFIG_CC_STACKPROTECTOR
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cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh
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cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh
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ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(biarch)),y)
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ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(KBUILD_CPPFLAGS) $(biarch)),y)
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stackp-y := -fstack-protector
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stackp-y := -fstack-protector
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KBUILD_CFLAGS += $(stackp-y)
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KBUILD_CFLAGS += $(stackp-y)
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else
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else
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@ -296,6 +296,7 @@ extern const char * const x86_power_flags[32];
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#endif /* CONFIG_X86_64 */
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#endif /* CONFIG_X86_64 */
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#if __GNUC__ >= 4
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/*
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/*
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* Static testing of CPU features. Used the same as boot_cpu_has().
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* Static testing of CPU features. Used the same as boot_cpu_has().
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* These are only valid after alternatives have run, but will statically
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* These are only valid after alternatives have run, but will statically
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@ -304,7 +305,7 @@ extern const char * const x86_power_flags[32];
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*/
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*/
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static __always_inline __pure bool __static_cpu_has(u16 bit)
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static __always_inline __pure bool __static_cpu_has(u16 bit)
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{
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{
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#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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#if __GNUC__ > 4 || __GNUC_MINOR__ >= 5
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asm goto("1: jmp %l[t_no]\n"
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asm goto("1: jmp %l[t_no]\n"
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"2:\n"
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"2:\n"
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".section .altinstructions,\"a\"\n"
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".section .altinstructions,\"a\"\n"
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@ -345,7 +346,6 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
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#endif
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#endif
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}
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}
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#if __GNUC__ >= 4
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#define static_cpu_has(bit) \
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#define static_cpu_has(bit) \
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( \
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( \
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__builtin_constant_p(boot_cpu_has(bit)) ? \
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__builtin_constant_p(boot_cpu_has(bit)) ? \
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@ -68,7 +68,6 @@ extern unsigned long force_hpet_address;
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extern u8 hpet_blockid;
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extern u8 hpet_blockid;
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extern int hpet_force_user;
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extern int hpet_force_user;
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extern u8 hpet_msi_disable;
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extern u8 hpet_msi_disable;
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extern u8 hpet_readback_cmp;
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extern int is_hpet_enabled(void);
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extern int is_hpet_enabled(void);
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extern int hpet_enable(void);
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extern int hpet_enable(void);
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extern void hpet_disable(void);
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extern void hpet_disable(void);
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@ -698,9 +698,11 @@ void __init uv_system_init(void)
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for (j = 0; j < 64; j++) {
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for (j = 0; j < 64; j++) {
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if (!test_bit(j, &present))
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if (!test_bit(j, &present))
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continue;
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continue;
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uv_blade_info[blade].pnode = (i * 64 + j);
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pnode = (i * 64 + j);
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uv_blade_info[blade].pnode = pnode;
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uv_blade_info[blade].nr_possible_cpus = 0;
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uv_blade_info[blade].nr_possible_cpus = 0;
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uv_blade_info[blade].nr_online_cpus = 0;
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uv_blade_info[blade].nr_online_cpus = 0;
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max_pnode = max(pnode, max_pnode);
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blade++;
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blade++;
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}
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}
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}
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}
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@ -738,7 +740,6 @@ void __init uv_system_init(void)
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uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
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uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
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uv_node_to_blade[nid] = blade;
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uv_node_to_blade[nid] = blade;
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uv_cpu_to_blade[cpu] = blade;
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uv_cpu_to_blade[cpu] = blade;
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max_pnode = max(pnode, max_pnode);
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}
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}
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/* Add blade/pnode info for nodes without cpus */
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/* Add blade/pnode info for nodes without cpus */
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@ -750,7 +751,6 @@ void __init uv_system_init(void)
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pnode = (paddr >> m_val) & pnode_mask;
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pnode = (paddr >> m_val) & pnode_mask;
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blade = boot_pnode_to_blade(pnode);
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blade = boot_pnode_to_blade(pnode);
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uv_node_to_blade[nid] = blade;
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uv_node_to_blade[nid] = blade;
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max_pnode = max(pnode, max_pnode);
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}
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}
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map_gru_high(max_pnode);
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map_gru_high(max_pnode);
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@ -18,7 +18,6 @@
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#include <asm/apic.h>
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#include <asm/apic.h>
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#include <asm/iommu.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/gart.h>
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#include <asm/hpet.h>
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static void __init fix_hypertransport_config(int num, int slot, int func)
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static void __init fix_hypertransport_config(int num, int slot, int func)
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{
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{
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@ -192,21 +191,6 @@ static void __init ati_bugs_contd(int num, int slot, int func)
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}
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}
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#endif
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#endif
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/*
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* Force the read back of the CMP register in hpet_next_event()
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* to work around the problem that the CMP register write seems to be
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* delayed. See hpet_next_event() for details.
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*
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* We do this on all SMBUS incarnations for now until we have more
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* information about the affected chipsets.
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*/
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static void __init ati_hpet_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_HPET_TIMER
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hpet_readback_cmp = 1;
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#endif
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}
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#define QFLAG_APPLY_ONCE 0x1
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#define QFLAG_APPLY_ONCE 0x1
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#define QFLAG_APPLIED 0x2
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#define QFLAG_APPLIED 0x2
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#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
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#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
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@ -236,8 +220,6 @@ static struct chipset early_qrk[] __initdata = {
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
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{ PCI_VENDOR_ID_ATI, PCI_ANY_ID,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
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{}
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{}
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};
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};
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@ -35,7 +35,6 @@
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unsigned long hpet_address;
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unsigned long hpet_address;
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u8 hpet_blockid; /* OS timer block num */
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u8 hpet_blockid; /* OS timer block num */
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u8 hpet_msi_disable;
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u8 hpet_msi_disable;
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u8 hpet_readback_cmp;
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#ifdef CONFIG_PCI_MSI
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#ifdef CONFIG_PCI_MSI
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static unsigned long hpet_num_timers;
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static unsigned long hpet_num_timers;
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@ -395,23 +394,27 @@ static int hpet_next_event(unsigned long delta,
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* at that point and we would wait for the next hpet interrupt
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* at that point and we would wait for the next hpet interrupt
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* forever. We found out that reading the CMP register back
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* forever. We found out that reading the CMP register back
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* forces the transfer so we can rely on the comparison with
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* forces the transfer so we can rely on the comparison with
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* the counter register below.
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* the counter register below. If the read back from the
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* compare register does not match the value we programmed
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* then we might have a real hardware problem. We can not do
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* much about it here, but at least alert the user/admin with
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* a prominent warning.
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*
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*
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* That works fine on those ATI chipsets, but on newer Intel
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* An erratum on some chipsets (ICH9,..), results in
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* chipsets (ICH9...) this triggers due to an erratum: Reading
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* comparator read immediately following a write returning old
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* the comparator immediately following a write is returning
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* value. Workaround for this is to read this value second
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* the old value.
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* time, when first read returns old value.
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*
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*
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* We restrict the read back to the affected ATI chipsets (set
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* In fact the write to the comparator register is delayed up
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* by quirks) and also run it with hpet=verbose for debugging
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* to two HPET cycles so the workaround we tried to restrict
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* purposes.
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* the readback to those known to be borked ATI chipsets
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* failed miserably. So we give up on optimizations forever
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* and penalize all HPET incarnations unconditionally.
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*/
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*/
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if (hpet_readback_cmp || hpet_verbose) {
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if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
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u32 cmp = hpet_readl(HPET_Tn_CMP(timer));
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if (hpet_readl(HPET_Tn_CMP(timer)) != cnt)
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if (cmp != cnt)
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printk_once(KERN_WARNING
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printk_once(KERN_WARNING
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"hpet: compare register read back failed.\n");
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"hpet: compare register read back failed.\n");
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}
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}
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return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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