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ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock
A quad core SMP build could get into hardware livelock with concurrent LLOCK/SCOND. Workaround that by adding a PREFETCHW which is serialized by SCU (System Coherency Unit). It brings the cache line in Exclusive state and makes others invalidate their lines. This gives enough time for winner to complete the LLOCK/SCOND, before others can get the line back. The prefetchw in the ll/sc loop is not nice but this is the only software workaround for current version of RTL. Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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1 changed files with 12 additions and 2 deletions
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@ -23,13 +23,21 @@
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#define atomic_set(v, i) (((v)->counter) = (i))
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#ifdef CONFIG_ISA_ARCV2
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#define PREFETCHW " prefetchw [%1] \n"
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#else
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#define PREFETCHW
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#endif
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#define ATOMIC_OP(op, c_op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned int temp; \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%1] \n" \
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"1: \n" \
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PREFETCHW \
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" llock %0, [%1] \n" \
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" " #asm_op " %0, %0, %2 \n" \
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" scond %0, [%1] \n" \
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" bnz 1b \n" \
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@ -50,7 +58,9 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %0, [%1] \n" \
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"1: \n" \
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PREFETCHW \
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" llock %0, [%1] \n" \
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" " #asm_op " %0, %0, %2 \n" \
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" scond %0, [%1] \n" \
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" bnz 1b \n" \
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