drm next for 6.3-rc1
Removals:
- remove legacy dri1 drivers -
- i810, mga, r128, savage, sis, tdfx, via
New driver:
- intel VPU accelerator driver
- habanalabs comes via drm tree now
drm/core:
- use drm_dbg_ helpers in several places
- Document defaults for CRTC backgrounds
- Document use of drm_minor
edid:
- improve mode parsing and refactoring
connector:
- support analog TV mode property
media:
- add some common formats
udmabuf:
- add vmap/vunmap methods
fourcc:
- add XRGB1555 and RGB565 formats
- document open source user waiver
firmware:
- fix color-format selection for system framebuffer
format-helper:
- Add conversion from XRGB8888 to various sysfb formats
- Make XRGB8888 the only driver-emulated legacy format
- Add conversion from XRGB8888 to XBGR8888 and ABGR8888
fb-helper:
- fix preferred depth and bpp values across drivers
- Avoid blank consoles from selecting an incorrect color format
probe-helper:
- Enable/disable HPD on connectors
scheduler:
- Fix lockup in drm_sched_entity_kill()
- Deprecate drm_sched_resubmit_jobs()
bridge:
- remove unused functions
- implement i2c probe_new in various drivers
- ite-it6505: Locking fixes, Cache EDID data
- ite-it66121: Support IT6610 chip
- lontium-tl9611: Fix HDMI on DragonBoard 845c
- parade-ps8640: Use atomic bridge functions
- Support i.MX93 LDB plus DT bindings
debugfs:
- add per device helpers and convert drivers
displayport:
- mst fixes
- add DP adaptive sync DPCD definitions
fbdev:
- always pick 32bpp as default
- remove some unused code
simpledrm:
- support system memory framebuffers
panel:
- add orientation quirks for Lenovo Yoga Tab 3 X90F and DynaBook K50
- Use ktime_get_boottime() to measure power-down delay
- Fix auto-suspend delay
- Visionox VTDR6130 AMOLED DSI
- Support Himax HX8394
- Convert many drivers to common generic DSI write-sequence helper
- AUO A030JTN01
ttm:
- drop bo wait wrapper
- fix MIPS build
habanalabs:
- moved driver to accel subsystem
- gaudi2 decoder error improvement
- more trace events
- Gaudi2 abrupt reset by firmware support
- add uAPI to flush memory transactions
- add uAPI to pass through userspace reqs to fw
- remove dma-buf export by handle
amdgpu:
- add new INFO queries for peak and min sclk/mclk for profile modes
- Add PCIe info to the INFO IOCTL
- secure display support for multiple displays
- DML optimizations
- DCN 3.2 updates
- PSR updates
- DP 2.1 updates
- SR-IOV RAS updates
- VCN RAS support
- SMU 13.x updates
- Switch 1 element arrays to flexible arrays
- Add RAS support for DF 4.3
- Stack size improvements
- S0ix rework
- Allow 0 as a vram limit on APUs
- Handle profiling modes for SMU13.x
- Fix possible segfault in failure case
- Rework FW requests to happen in early_init for all IPs so
that we don't lose the sbios console if FW is missing
- Fix power reporting on certain firmwares for CZN/RN
- Allow S0ix without BIOS support
- Enable freesync over PCon
- Re-enable the AGP aperture on GMC 11.x
amdkfd:
- Error handling fixes
- PASID fixes
- Fix for cleared VRAM BOs
- Fix cleanup if GPUVM creation fails
- Memory accounting fix
- Use resource_size rather than open codeing it
- GC11 mGPU fix
radeon:
- Switch 1 element arrays to flexible arrays
- Fix memory leak on shutdown
- move to new logging
i915:
- Meteorlake display/OA/GSC fw/workarounds enabling
- DP MST DSC support
- Gamma/degamma readout support for the state checker
- Enable SDP split support for DP 2.0
- Add probe blocking support to i915.force_probe parameter
- Enable Xe HP 4tile support
- Avoid display direct calls to uncore
- Fix HuC delayed load memory leaks
- Add DG2 workarounds Wa_18018764978 and Wa_18019271663
- Improve suspend / resume times with VT-d scanout workaround active
- Fix DG2 visual corruption on small BAR systems by not forgetting to copy CCS aux state
- Fix TLB invalidation for Gen12.50 video and compute engines
- Enable HF-EEODB by switching HDMI, DP and LVDS to use struct drm_edid
- Start using unversioned DMC firmware paths for new platforms
- ELD refactor: Stop using hardware buffer, precompute ELD
- lots of display code refactoring
nouveau:
- drop legacy ioctl support
- replace 0-sized array
msm:
- dpu/dsi/mdss: Support for SM8350, SM8450 SM8550 and SC8280XP platform
- Added bindings for SM8150
- dpu: Partial support for DSC on SM8150 and SM8250
- dpu: Fixed color transformation matrix being lost on suspend/resume
- dp: Support SDM845 and SC8280XP platforms
- dp: Support for limiting DP link rate via DT property
- dsi: Validate display modes according to the DSI OPP table
- dsi: DSI PHY support for the SM6375 platform
- Add MSM_SUBMIT_BO_NO_IMPLICI
- a2xx: Support to load legacy firmware
- a6xx: GPU devcore dump updates for a650/a660
- GPU devfreq tuning and fixes
- Turn 8960 HDMI PHY into clock provider,
- Make 8960 HDMI PHY use PXO clock from DT
etnaviv:
- experimental versilicon NPU support
- report GPU load via fdinfo format
- MMU fault message improvements
tegra:
- rework syncpoint interrupt
mediatek:
- DSI timing fix
- fix config deps
ast:
- various fixes
exynos:
- restore bridge chain order fixes
gud:
- convert to shadow plane buffers
- perform flushing synchronously during atomic update
- Use new debugfs helpers
arm/hdlcd:
- Use new debugfs helper
ili9486:
- Support 16-bit pixel data
imx:
- Split off IPUv3 driver
mipi-dbi:
- convert to DRM shadow-plane helpers
- rsp driver changes
- Support separate I/O-voltage supply
mxsfb:
- Depend on ARCH_MXS or ARCH_MXC
sun4i:
- convert to new TV mode property
vc4:
- convert to new TV mode property
- kunit tests
- Support RGB565 and RGB666 formats
- convert dsi driver to bridge
- Various HVS an CRTC fixes
v3d:
- Do not opencode drm_gem_object_lookup()
virtio:
- improve tracing
vkms:
- support small cursors in IGT tests
- Fix SEGFAULT from incorrect GEM-buffer mapping
rcar-du:
- fixes and improvements
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Merge tag 'drm-next-2023-02-23' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"There are a bunch of changes all over in the usual places.
Highlights:
- habanalabs moves from misc to accel
- first accel driver for Intel VPU (Versatile Processing Unit)
inference engine
- dropped all the ancient legacy DRI1 drivers. I think it's been at
least 10 years since anyone has heard about these.
- Intel DG2 updates and prelim Meteorlake enablement
- etnaviv adds support for Versilicon NPU device (a GPU like engine
with inference accelerators)
Detailed summary:
Removals:
- remove legacy dri1 drivers: i810, mga, r128, savage, sis, tdfx, via
New driver:
- intel VPU accelerator driver
- habanalabs comes via drm tree now
drm/core:
- use drm_dbg_ helpers in several places
- Document defaults for CRTC backgrounds
- Document use of drm_minor
edid:
- improve mode parsing and refactoring
connector:
- support analog TV mode property
media:
- add some common formats
udmabuf:
- add vmap/vunmap methods
fourcc:
- add XRGB1555 and RGB565 formats
- document open source user waiver
firmware:
- fix color-format selection for system framebuffer
format-helper:
- Add conversion from XRGB8888 to various sysfb formats
- Make XRGB8888 the only driver-emulated legacy format
- Add conversion from XRGB8888 to XBGR8888 and ABGR8888
fb-helper:
- fix preferred depth and bpp values across drivers
- Avoid blank consoles from selecting an incorrect color format
probe-helper:
- Enable/disable HPD on connectors
scheduler:
- Fix lockup in drm_sched_entity_kill()
- Deprecate drm_sched_resubmit_jobs()
bridge:
- remove unused functions
- implement i2c probe_new in various drivers
- ite-it6505: Locking fixes, Cache EDID data
- ite-it66121: Support IT6610 chip
- lontium-tl9611: Fix HDMI on DragonBoard 845c
- parade-ps8640: Use atomic bridge functions
- Support i.MX93 LDB plus DT bindings
debugfs:
- add per device helpers and convert drivers
displayport:
- mst fixes
- add DP adaptive sync DPCD definitions
fbdev:
- always pick 32bpp as default
- remove some unused code
simpledrm:
- support system memory framebuffers
panel:
- add orientation quirks for Lenovo Yoga Tab 3 X90F and DynaBook K50
- Use ktime_get_boottime() to measure power-down delay
- Fix auto-suspend delay
- Visionox VTDR6130 AMOLED DSI
- Support Himax HX8394
- Convert many drivers to common generic DSI write-sequence helper
- AUO A030JTN01
ttm:
- drop bo wait wrapper
- fix MIPS build
habanalabs:
- moved driver to accel subsystem
- gaudi2 decoder error improvement
- more trace events
- Gaudi2 abrupt reset by firmware support
- add uAPI to flush memory transactions
- add uAPI to pass through userspace reqs to fw
- remove dma-buf export by handle
amdgpu:
- add new INFO queries for peak and min sclk/mclk for profile modes
- Add PCIe info to the INFO IOCTL
- secure display support for multiple displays
- DML optimizations
- DCN 3.2 updates
- PSR updates
- DP 2.1 updates
- SR-IOV RAS updates
- VCN RAS support
- SMU 13.x updates
- Switch 1 element arrays to flexible arrays
- Add RAS support for DF 4.3
- Stack size improvements
- S0ix rework
- Allow 0 as a vram limit on APUs
- Handle profiling modes for SMU13.x
- Fix possible segfault in failure case
- Rework FW requests to happen in early_init for all IPs so that we
don't lose the sbios console if FW is missing
- Fix power reporting on certain firmwares for CZN/RN
- Allow S0ix without BIOS support
- Enable freesync over PCon
- Re-enable the AGP aperture on GMC 11.x
amdkfd:
- Error handling fixes
- PASID fixes
- Fix for cleared VRAM BOs
- Fix cleanup if GPUVM creation fails
- Memory accounting fix
- Use resource_size rather than open codeing it
- GC11 mGPU fix
radeon:
- Switch 1 element arrays to flexible arrays
- Fix memory leak on shutdown
- move to new logging
i915:
- Meteorlake display/OA/GSC fw/workarounds enabling
- DP MST DSC support
- Gamma/degamma readout support for the state checker
- Enable SDP split support for DP 2.0
- Add probe blocking support to i915.force_probe parameter
- Enable Xe HP 4tile support
- Avoid display direct calls to uncore
- Fix HuC delayed load memory leaks
- Add DG2 workarounds Wa_18018764978 and Wa_18019271663
- Improve suspend / resume times with VT-d scanout workaround active
- Fix DG2 visual corruption on small BAR systems by not forgetting to
copy CCS aux state
- Fix TLB invalidation for Gen12.50 video and compute engines
- Enable HF-EEODB by switching HDMI, DP and LVDS to use struct
drm_edid
- Start using unversioned DMC firmware paths for new platforms
- ELD refactor: Stop using hardware buffer, precompute ELD
- lots of display code refactoring
nouveau:
- drop legacy ioctl support
- replace 0-sized array
msm:
- dpu/dsi/mdss: Support for SM8350, SM8450 SM8550 and SC8280XP platform
- Added bindings for SM8150
- dpu: Partial support for DSC on SM8150 and SM8250
- dpu: Fixed color transformation matrix being lost on suspend/resume
- dp: Support SDM845 and SC8280XP platforms
- dp: Support for limiting DP link rate via DT property
- dsi: Validate display modes according to the DSI OPP table
- dsi: DSI PHY support for the SM6375 platform
- Add MSM_SUBMIT_BO_NO_IMPLICI
- a2xx: Support to load legacy firmware
- a6xx: GPU devcore dump updates for a650/a660
- GPU devfreq tuning and fixes
- Turn 8960 HDMI PHY into clock provider,
- Make 8960 HDMI PHY use PXO clock from DT
etnaviv:
- experimental versilicon NPU support
- report GPU load via fdinfo format
- MMU fault message improvements
tegra:
- rework syncpoint interrupt
mediatek:
- DSI timing fix
- fix config deps
ast:
- various fixes
exynos:
- restore bridge chain order fixes
gud:
- convert to shadow plane buffers
- perform flushing synchronously during atomic update
- Use new debugfs helpers
arm/hdlcd:
- Use new debugfs helper
ili9486:
- Support 16-bit pixel data
imx:
- Split off IPUv3 driver
mipi-dbi:
- convert to DRM shadow-plane helpers
- rsp driver changes
- Support separate I/O-voltage supply
mxsfb:
- Depend on ARCH_MXS or ARCH_MXC
sun4i:
- convert to new TV mode property
vc4:
- convert to new TV mode property
- kunit tests
- Support RGB565 and RGB666 formats
- convert dsi driver to bridge
- Various HVS an CRTC fixes
v3d:
- Do not opencode drm_gem_object_lookup()
virtio:
- improve tracing
vkms:
- support small cursors in IGT tests
- Fix SEGFAULT from incorrect GEM-buffer mapping
rcar-du:
- fixes and improvements"
* tag 'drm-next-2023-02-23' of git://anongit.freedesktop.org/drm/drm: (1455 commits)
msm/fbdev: fix unused variable warning with clang.
drm/fb-helper: Remove drm_fb_helper_unprepare() from drm_fb_helper_fini()
dma-buf: make kobj_type structure constant
drm/shmem-helper: Fix locking for drm_gem_shmem_get_pages_sgt()
drm/amd/display: disable SubVP + DRR to prevent underflow
drm/amd/display: Fail atomic_check early on normalize_zpos error
drm/amd/pm: avoid unaligned access warnings
drm/amd/display: avoid unaligned access warnings
drm/amd/display: Remove duplicate/repeating expressions
drm/amd/display: Remove duplicate/repeating expression
drm/amd/display: Make variables declaration inside ifdef guard
drm/amd/display: Fix excess arguments on kernel-doc
drm/amd/display: Add previously missing includes
drm/amd/amdgpu: Add function prototypes to headers
drm/amd/display: Add function prototypes to headers
drm/amd/display: Turn global functions into static
drm/amd/display: remove unused _calculate_degamma_curve function
drm/amd/display: remove unused func declaration from resource headers
drm/amd/display: unset initial value for tf since it's never used
drm/amd/display: camel case cleanup in color_gamma file
...
This commit is contained in:
Linus Torvalds
commit
a5c95ca18a
|
|
@ -201,7 +201,19 @@ What: /sys/class/habanalabs/hl<n>/status
|
|||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: ogabbay@kernel.org
|
||||
Description: Status of the card: "Operational", "Malfunction", "In reset".
|
||||
Description: Status of the card:
|
||||
|
||||
* "operational" - Device is available for work.
|
||||
* "in reset" - Device is going through reset, will be
|
||||
available shortly.
|
||||
* "disabled" - Device is not usable.
|
||||
* "needs reset" - Device is not usable until a hard reset
|
||||
is initiated.
|
||||
* "in device creation" - Device is not available yet, as it
|
||||
is still initializing.
|
||||
* "in reset after device release" - Device is going through
|
||||
a compute-reset which is executed after a device release
|
||||
(relevant for Gaudi2 only).
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/thermal_ver
|
||||
Date: Jan 2019
|
||||
|
|
|
|||
|
|
@ -67,9 +67,9 @@ tree - drivers/accel/.
|
|||
The accelerator devices will be exposed to the user space with the dedicated
|
||||
261 major number and will have the following convention:
|
||||
|
||||
- device char files - /dev/accel/accel*
|
||||
- sysfs - /sys/class/accel/accel*/
|
||||
- debugfs - /sys/kernel/debug/accel/*/
|
||||
- device char files - /dev/accel/accel\*
|
||||
- sysfs - /sys/class/accel/accel\*/
|
||||
- debugfs - /sys/kernel/debug/accel/\*/
|
||||
|
||||
Getting Started
|
||||
===============
|
||||
|
|
|
|||
|
|
@ -1,112 +0,0 @@
|
|||
Cadence DSI bridge
|
||||
==================
|
||||
|
||||
The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be set to "cdns,dsi".
|
||||
- reg: physical base address and length of the controller's registers.
|
||||
- interrupts: interrupt line connected to the DSI bridge.
|
||||
- clocks: DSI bridge clocks.
|
||||
- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
|
||||
- phys: phandle link to the MIPI D-PHY controller.
|
||||
- phy-names: must contain "dphy".
|
||||
- #address-cells: must be set to 1.
|
||||
- #size-cells: must be set to 0.
|
||||
|
||||
Optional properties:
|
||||
- resets: DSI reset lines.
|
||||
- reset-names: can contain "dsi_p_rst".
|
||||
|
||||
Required subnodes:
|
||||
- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
|
||||
2 ports are available:
|
||||
* port 0: this port is only needed if some of your DSI devices are
|
||||
controlled through an external bus like I2C or SPI. Can have at
|
||||
most 4 endpoints. The endpoint number is directly encoding the
|
||||
DSI virtual channel used by this device.
|
||||
* port 1: represents the DPI input.
|
||||
Other ports will be added later to support the new kind of inputs.
|
||||
|
||||
- one subnode per DSI device connected on the DSI bus. Each DSI device should
|
||||
contain a reg property encoding its virtual channel.
|
||||
|
||||
Example:
|
||||
dsi0: dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
clocks = <&pclk>, <&sysclk>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
interrupts = <1>;
|
||||
phys = <&dphy0>;
|
||||
phy-names = "dphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_dpi_input: endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: dsi-dev@0 {
|
||||
compatible = "<vendor,panel>";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
or
|
||||
|
||||
dsi0: dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
clocks = <&pclk>, <&sysclk>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
interrupts = <1>;
|
||||
phys = <&dphy1>;
|
||||
phy-names = "dphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dsi0_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&dsi_panel_input>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_dpi_input: endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@xxx {
|
||||
panel: panel@59 {
|
||||
compatible = "<vendor,panel>";
|
||||
reg = <0x59>;
|
||||
|
||||
port {
|
||||
dsi_panel_input: endpoint {
|
||||
remote-endpoint = <&dsi0_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence DSI bridge
|
||||
|
||||
maintainers:
|
||||
- Boris Brezillon <boris.brezillon@bootlin.com>
|
||||
|
||||
description: |
|
||||
CDNS DSI is a bridge device which converts DPI to DSI
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cdns,dsi
|
||||
- ti,j721e-dsi
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description:
|
||||
Register block for controller's registers.
|
||||
- description:
|
||||
Register block for wrapper settings registers in case of TI J7 SoCs.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PSM clock, used by the IP
|
||||
- description: sys clock, used by the IP
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: dsi_p_clk
|
||||
- const: dsi_sys_clk
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: dphy
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: dsi_p_rst
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Output port representing the DSI output. It can have
|
||||
at most 4 endpoints. The endpoint number is directly encoding
|
||||
the DSI virtual channel used by this device.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
Input port representing the DPI input.
|
||||
|
||||
required:
|
||||
- port@1
|
||||
|
||||
allOf:
|
||||
- $ref: ../dsi-controller.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,j721e-dsi
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- ports
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
clocks = <&pclk>, <&sysclk>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
interrupts = <1>;
|
||||
phys = <&dphy0>;
|
||||
phy-names = "dphy";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "panasonic,vvx10f034n00";
|
||||
reg = <0>;
|
||||
power-supply = <&vcc_lcd_reg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dsi@fd0c0000 {
|
||||
compatible = "cdns,dsi";
|
||||
reg = <0x0 0xfd0c0000 0x0 0x1000>;
|
||||
clocks = <&pclk>, <&sysclk>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
interrupts = <1>;
|
||||
phys = <&dphy1>;
|
||||
phy-names = "dphy";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&dsi_panel_input>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&xxx_dpi_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -16,7 +16,9 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-ldb
|
||||
enum:
|
||||
- fsl,imx8mp-ldb
|
||||
- fsl,imx93-ldb
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
|
@ -57,6 +59,18 @@ required:
|
|||
- clocks
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx93-ldb
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@2: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -52,9 +52,49 @@ properties:
|
|||
maxItems: 1
|
||||
description: extcon specifier for the Power Delivery
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: A port node pointing to DPI host port node
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: A port node pointing to DPI host port node
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
link-frequencies:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
description: Allowed max link frequencies in Hz
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description: Video port for DP output
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
minItems: 1
|
||||
uniqueItems: true
|
||||
items:
|
||||
- enum: [ 0, 1 ]
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -63,6 +103,7 @@ required:
|
|||
- interrupts
|
||||
- reset-gpios
|
||||
- extcon
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -85,9 +126,24 @@ examples:
|
|||
reset-gpios = <&pio 179 1>;
|
||||
extcon = <&usbc_extcon>;
|
||||
|
||||
port {
|
||||
it6505_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
it6505_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
link-frequencies = /bits/ 64 <150000000>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
it6505_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
data-lanes = <0 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,9 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: ite,it66121
|
||||
enum:
|
||||
- ite,it66121
|
||||
- ite,it6610
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -11,13 +11,14 @@ maintainers:
|
|||
|
||||
description: |
|
||||
This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
|
||||
R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
|
||||
R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
|
||||
to four data lanes.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r8a779a0-dsi-csi2-tx # for V3U
|
||||
- renesas,r8a779g0-dsi-csi2-tx # for V4H
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-mipi-dsi # RZ/V2L
|
||||
- const: renesas,rzg2l-mipi-dsi
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-aal
|
||||
- mediatek,mt8188-disp-aal
|
||||
- mediatek,mt8192-disp-aal
|
||||
- mediatek,mt8195-disp-aal
|
||||
- const: mediatek,mt8183-disp-aal
|
||||
|
|
|
|||
|
|
@ -27,12 +27,13 @@ properties:
|
|||
- const: mediatek,mt8192-disp-ccorr
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-ccorr
|
||||
- mediatek,mt8195-disp-ccorr
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-ccorr
|
||||
- const: mediatek,mt8183-disp-ccorr
|
||||
- const: mediatek,mt8192-disp-ccorr
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ properties:
|
|||
- enum:
|
||||
- mediatek,mt8183-disp-color
|
||||
- mediatek,mt8186-disp-color
|
||||
- mediatek,mt8188-disp-color
|
||||
- mediatek,mt8192-disp-color
|
||||
- mediatek,mt8195-disp-color
|
||||
- const: mediatek,mt8173-disp-color
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-dither
|
||||
- mediatek,mt8188-disp-dither
|
||||
- mediatek,mt8192-disp-dither
|
||||
- mediatek,mt8195-disp-dither
|
||||
- const: mediatek,mt8183-disp-dither
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-gamma
|
||||
- mediatek,mt8188-disp-gamma
|
||||
- mediatek,mt8192-disp-gamma
|
||||
- mediatek,mt8195-disp-gamma
|
||||
- const: mediatek,mt8183-disp-gamma
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ properties:
|
|||
- const: mediatek,mt2701-disp-ovl
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-ovl
|
||||
- mediatek,mt8195-disp-ovl
|
||||
- const: mediatek,mt8183-disp-ovl
|
||||
- items:
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8186-disp-postmask
|
||||
- mediatek,mt8188-disp-postmask
|
||||
- const: mediatek,mt8192-disp-postmask
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -31,6 +31,10 @@ properties:
|
|||
- const: mediatek,mt8183-disp-rdma
|
||||
- items:
|
||||
- const: mediatek,mt8195-disp-rdma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8188-disp-rdma
|
||||
- const: mediatek,mt8195-disp-rdma
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7623-disp-rdma
|
||||
|
|
|
|||
|
|
@ -21,6 +21,9 @@ properties:
|
|||
- qcom,sc7280-edp
|
||||
- qcom,sc8180x-dp
|
||||
- qcom,sc8180x-edp
|
||||
- qcom,sc8280xp-dp
|
||||
- qcom,sc8280xp-edp
|
||||
- qcom,sdm845-dp
|
||||
- qcom,sm8350-dp
|
||||
|
||||
reg:
|
||||
|
|
@ -81,6 +84,7 @@ properties:
|
|||
|
||||
data-lanes:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
deprecated: true
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
|
|
@ -102,8 +106,28 @@ properties:
|
|||
description: Input endpoint of the controller
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
description: Output endpoint of the controller
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
link-frequencies:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -127,11 +151,10 @@ allOf:
|
|||
enum:
|
||||
- qcom,sc7280-edp
|
||||
- qcom,sc8180x-edp
|
||||
- qcom,sc8280xp-edp
|
||||
then:
|
||||
properties:
|
||||
"#sound-dai-cells": false
|
||||
reg:
|
||||
maxItems: 4
|
||||
else:
|
||||
properties:
|
||||
aux-bus: false
|
||||
|
|
@ -193,6 +216,8 @@ examples:
|
|||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&typec>;
|
||||
data-lanes = <0 1>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,7 +13,15 @@ maintainers:
|
|||
description: |
|
||||
Common properties for QCom DPU display controller.
|
||||
|
||||
# Do not select this by default, otherwise it is also selected for all
|
||||
# display-controller@ nodes
|
||||
select:
|
||||
false
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^display-controller@[0-9a-f]+$'
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
|
|
@ -40,10 +48,6 @@ properties:
|
|||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
|
|
|
|||
|
|
@ -9,14 +9,33 @@ title: Qualcomm Display DSI controller
|
|||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "../dsi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,mdss-dsi-ctrl
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8064-dsi-ctrl
|
||||
- qcom,msm8916-dsi-ctrl
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
- qcom,msm8974-dsi-ctrl
|
||||
- qcom,msm8996-dsi-ctrl
|
||||
- qcom,msm8998-dsi-ctrl
|
||||
- qcom,qcm2290-dsi-ctrl
|
||||
- qcom,sc7180-dsi-ctrl
|
||||
- qcom,sc7280-dsi-ctrl
|
||||
- qcom,sdm660-dsi-ctrl
|
||||
- qcom,sdm845-dsi-ctrl
|
||||
- qcom,sm8150-dsi-ctrl
|
||||
- qcom,sm8250-dsi-ctrl
|
||||
- qcom,sm8350-dsi-ctrl
|
||||
- qcom,sm8450-dsi-ctrl
|
||||
- qcom,sm8550-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
- items:
|
||||
- enum:
|
||||
- dsi-ctrl-6g-qcm2290
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
deprecated: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -28,22 +47,23 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display byte clock
|
||||
- description: Display byte interface clock
|
||||
- description: Display pixel clock
|
||||
- description: Display core clock
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
description: |
|
||||
Several clocks are used, depending on the variant. Typical ones are::
|
||||
- bus:: Display AHB clock.
|
||||
- byte:: Display byte clock.
|
||||
- byte_intf:: Display byte interface clock.
|
||||
- core:: Display core clock.
|
||||
- core_mss:: Core MultiMedia SubSystem clock.
|
||||
- iface:: Display AXI clock.
|
||||
- mdp_core:: MDP Core clock.
|
||||
- mnoc:: MNOC clock
|
||||
- pixel:: Display pixel clock.
|
||||
minItems: 3
|
||||
maxItems: 9
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
minItems: 3
|
||||
maxItems: 9
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
|
@ -52,10 +72,6 @@ properties:
|
|||
deprecated: true
|
||||
const: dsi
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
syscon-sfpb:
|
||||
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
|
@ -67,12 +83,16 @@ properties:
|
|||
2 DSI links.
|
||||
|
||||
assigned-clocks:
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
description: |
|
||||
Parents of "byte" and "pixel" for the given platform.
|
||||
For DSIv2 platforms this should contain "byte", "esc", "src" and
|
||||
"pixel_src" clocks.
|
||||
|
||||
assigned-clock-parents:
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
description: |
|
||||
The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
|
||||
|
||||
|
|
@ -103,7 +123,7 @@ properties:
|
|||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
minItems: 1
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
|
|
@ -119,7 +139,7 @@ properties:
|
|||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
minItems: 1
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
|
|
@ -127,6 +147,26 @@ properties:
|
|||
- port@0
|
||||
- port@1
|
||||
|
||||
avdd-supply:
|
||||
description:
|
||||
Phandle to vdd regulator device node
|
||||
|
||||
vcca-supply:
|
||||
description:
|
||||
Phandle to vdd regulator device node
|
||||
|
||||
vdd-supply:
|
||||
description:
|
||||
VDD regulator
|
||||
|
||||
vddio-supply:
|
||||
description:
|
||||
VDD-IO regulator
|
||||
|
||||
vdda-supply:
|
||||
description:
|
||||
VDDA regulator
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -139,7 +179,192 @@ required:
|
|||
- assigned-clock-parents
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
allOf:
|
||||
- $ref: ../dsi-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,apq8064-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core_mmss
|
||||
- const: src
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8916-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8953-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8974-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: byte
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: core_mmss
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8996-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: byte
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core_mmss
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8998-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sc7180-dsi-ctrl
|
||||
- qcom,sc7280-dsi-ctrl
|
||||
- qcom,sm8150-dsi-ctrl
|
||||
- qcom,sm8250-dsi-ctrl
|
||||
- qcom,sm8350-dsi-ctrl
|
||||
- qcom,sm8450-dsi-ctrl
|
||||
- qcom,sm8550-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdm660-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 9
|
||||
clock-names:
|
||||
items:
|
||||
- const: mdp_core
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: mnoc
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core_mmss
|
||||
- const: pixel
|
||||
- const: core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sdm845-dsi-ctrl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
@ -149,7 +374,7 @@ examples:
|
|||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-hpm-fam-b
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
- qcom,dsi-phy-28nm-8960
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,10 @@ properties:
|
|||
- qcom,dsi-phy-7nm
|
||||
- qcom,dsi-phy-7nm-8150
|
||||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sm6375-dsi-phy-7nm
|
||||
- qcom,sm8350-dsi-phy-5nm
|
||||
- qcom,sm8450-dsi-phy-5nm
|
||||
- qcom,sm8550-dsi-phy-4nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
@ -44,7 +48,6 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vdds-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -4,14 +4,13 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Description of Qualcomm Display DSI PHY common dt properties
|
||||
title: Qualcomm Display DSI PHY Common Properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
description: |
|
||||
This defines the DSI PHY dt properties which are common for all
|
||||
dsi phy versions.
|
||||
description:
|
||||
Common properties for Qualcomm Display DSI PHY.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
|
|
|
|||
|
|
@ -149,6 +149,8 @@ allOf:
|
|||
description: GPU 3D engine clock
|
||||
- const: rbbmtimer
|
||||
description: GPU RBBM Timer for Adreno 5xx series
|
||||
- const: rbcpr
|
||||
description: GPU RB Core Power Reduction clock
|
||||
minItems: 2
|
||||
maxItems: 7
|
||||
|
||||
|
|
|
|||
|
|
@ -1,132 +0,0 @@
|
|||
Qualcomm adreno/snapdragon MDP5 display controller
|
||||
|
||||
Description:
|
||||
|
||||
This is the bindings documentation for the MDP5 display
|
||||
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
|
||||
|
||||
MDP5:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdp5" - MDP5
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "mdp_phys"
|
||||
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
|
||||
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required.
|
||||
- * "bus"
|
||||
- * "iface"
|
||||
- * "core"
|
||||
- * "vsync"
|
||||
- ports: contains the list of output ports from MDP. These connect to interfaces
|
||||
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
|
||||
special case since it is a part of the MDP block itself).
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
The availability of output ports can vary across SoC revisions:
|
||||
|
||||
For MSM8974 and APQ8084:
|
||||
Port 0 -> MDP_INTF0 (eDP)
|
||||
Port 1 -> MDP_INTF1 (DSI1)
|
||||
Port 2 -> MDP_INTF2 (DSI2)
|
||||
Port 3 -> MDP_INTF3 (HDMI)
|
||||
|
||||
For MSM8916:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
|
||||
For MSM8994 and MSM8996:
|
||||
Port 0 -> MDP_INTF1 (DSI1)
|
||||
Port 1 -> MDP_INTF2 (DSI2)
|
||||
Port 2 -> MDP_INTF3 (HDMI)
|
||||
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut"
|
||||
* "tbu"
|
||||
* "tbu_rt"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
mdss: mdss@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
reg-names = "mdss_phys", "vbif_phys";
|
||||
|
||||
power-domains = <&gcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus",
|
||||
"vsync"
|
||||
|
||||
interrupts = <0 72 0>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp: mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x1a01000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0 0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp5_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@1a98000 {
|
||||
...
|
||||
ports {
|
||||
...
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp5_intf1_out>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
dsi_phy0: dsi-phy@1a98300 {
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -15,7 +15,15 @@ description:
|
|||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
# Do not select this by default, otherwise it is also selected for qcom,mdss
|
||||
# devices.
|
||||
select:
|
||||
false
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^display-subsystem@[0-9a-f]+$"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
|
@ -70,7 +78,6 @@ properties:
|
|||
- description: MDSS_CORE reset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
|
|
|
|||
|
|
@ -0,0 +1,156 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
|
||||
|
||||
description:
|
||||
MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
|
||||
and MSM8996.
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
- Rob Clark <robdclark@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,mdp5
|
||||
deprecated: true
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8084-mdp5
|
||||
- qcom,msm8916-mdp5
|
||||
- qcom,msm8917-mdp5
|
||||
- qcom,msm8953-mdp5
|
||||
- qcom,msm8974-mdp5
|
||||
- qcom,msm8976-mdp5
|
||||
- qcom,msm8994-mdp5
|
||||
- qcom,msm8996-mdp5
|
||||
- qcom,sdm630-mdp5
|
||||
- qcom,sdm660-mdp5
|
||||
- const: qcom,mdp5
|
||||
|
||||
$nodename:
|
||||
pattern: '^display-controller@[0-9a-f]+$'
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp_phys
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- minItems: 4
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
- const: lut
|
||||
- const: tbu
|
||||
- const: tbu_rt
|
||||
#MSM8996 has additional iommu clock
|
||||
- items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: iommu
|
||||
- const: vsync
|
||||
|
||||
interconnects:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
|
||||
- description: Interconnect path from mdp1 port to the data bus
|
||||
- description: Interconnect path from rotator port to the data bus
|
||||
|
||||
interconnect-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mdp0-mem
|
||||
- const: mdp1-mem
|
||||
- const: rotator-mem
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: apps SMMU with the Stream-ID mask for Hard-Fail port0
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
opp-table:
|
||||
type: object
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: >
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. MDP5 devices support up to 4 ports:
|
||||
one or two DSI ports, HDMI and eDP.
|
||||
|
||||
patternProperties:
|
||||
"^port@[0-3]+$":
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
# at least one port is required
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
display-controller@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
reg = <0x1a01000 0x90000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
clocks = <&gcc GCC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_MDSS_AXI_CLK>,
|
||||
<&gcc GCC_MDSS_MDP_CLK>,
|
||||
<&gcc GCC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -15,6 +15,9 @@ description:
|
|||
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^display-subsystem@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,mdss
|
||||
|
|
@ -44,18 +47,30 @@ properties:
|
|||
The MDSS power domain provided by GCC
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display axi clock
|
||||
- description: Display vsync clock
|
||||
oneOf:
|
||||
- minItems: 3
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display axi clock
|
||||
- description: Display vsync clock
|
||||
- description: Display core clock
|
||||
- minItems: 1
|
||||
items:
|
||||
- description: Display abh clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: vsync
|
||||
oneOf:
|
||||
- minItems: 3
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: vsync
|
||||
- const: core
|
||||
- minItems: 1
|
||||
items:
|
||||
- const: iface
|
||||
- const: core
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
|
@ -84,17 +99,19 @@ required:
|
|||
- ranges
|
||||
|
||||
patternProperties:
|
||||
"^mdp@[1-9a-f][0-9a-f]*$":
|
||||
"^display-controller@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdp5
|
||||
contains:
|
||||
const: qcom,mdp5
|
||||
|
||||
"^dsi@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
contains:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
|
|
@ -107,12 +124,6 @@ patternProperties:
|
|||
- qcom,dsi-phy-20nm
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
|
||||
"^hdmi-phy@[1-9a-f][0-9a-f]*$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,hdmi-phy-8084
|
||||
- qcom,hdmi-phy-8660
|
||||
- qcom,hdmi-phy-8960
|
||||
|
|
@ -137,7 +148,7 @@ examples:
|
|||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
mdss@1a00000 {
|
||||
display-subsystem@1a00000 {
|
||||
compatible = "qcom,mdss";
|
||||
reg = <0x1a00000 0x1000>,
|
||||
<0x1ac8000 0x3000>;
|
||||
|
|
@ -161,8 +172,8 @@ examples:
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mdp@1a01000 {
|
||||
compatible = "qcom,mdp5";
|
||||
display-controller@1a01000 {
|
||||
compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
|
||||
reg = <0x01a01000 0x89000>;
|
||||
reg-names = "mdp_phys";
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for MSM8998 target
|
||||
title: Qualcomm Display DPU on MSM8998
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
|
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-dpu
|
||||
const: qcom,msm8998-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
@ -46,6 +45,13 @@ properties:
|
|||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,msm8998-mdss
|
||||
const: qcom,msm8998-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -47,7 +46,9 @@ patternProperties:
|
|||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,msm8998-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
|
|
@ -55,6 +56,9 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,dsi-phy-10nm-8998
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -126,7 +130,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@c994000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c994000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
@ -196,7 +200,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@c996000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0c996000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for QCM2290 target
|
||||
title: Qualcomm Display DPU on QCM2290
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
|
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-dpu
|
||||
const: qcom,qcm2290-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
@ -42,6 +41,13 @@ properties:
|
|||
- const: lut
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,qcm2290-mdss
|
||||
const: qcom,qcm2290-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -61,6 +60,9 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,dsi-phy-14nm-2290
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7180 target
|
||||
title: Qualcomm Display DPU on SC7180
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
|
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-dpu
|
||||
const: qcom,sc7180-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
@ -44,6 +43,13 @@ properties:
|
|||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-mdss
|
||||
const: qcom,sc7180-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -59,7 +58,9 @@ patternProperties:
|
|||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sc7180-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
|
|
@ -67,6 +68,9 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,dsi-phy-10nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -142,7 +146,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7280
|
||||
title: Qualcomm Display DPU on SC7280
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
|
@ -43,6 +43,13 @@ properties:
|
|||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -58,7 +58,9 @@ patternProperties:
|
|||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sc7280-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^edp@[0-9a-f]+$":
|
||||
type: object
|
||||
|
|
@ -74,6 +76,9 @@ patternProperties:
|
|||
- qcom,sc7280-dsi-phy-7nm
|
||||
- qcom,sc7280-edp-phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -162,7 +167,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,122 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8280XP Display Processing Unit
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for SC8280XP Display Processing Unit.
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc8280xp-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <460000000>,
|
||||
<19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp3_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp2_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8280XP Mobile Display Subsystem
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc8280xp-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-dp
|
||||
- qcom,sc8280xp-edp
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sc8280xp-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
power-domains = <&dispcc0 MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface",
|
||||
"ahb",
|
||||
"core";
|
||||
|
||||
resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x1000 0x402>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc8280xp-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdss0_mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp3_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
endpoint {
|
||||
remote-endpoint = <&mdss0_dp2_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
title: Qualcomm Display DPU on SDM845
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
|
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
@ -42,6 +41,13 @@ properties:
|
|||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
const: qcom,sdm845-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -47,11 +46,19 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,sdm845-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sdm845-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
|
|
@ -59,6 +66,9 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,dsi-phy-10nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -128,7 +138,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
@ -198,7 +208,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SM6115 target
|
||||
title: Qualcomm Display DPU on SM6115
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
|
@ -13,8 +13,7 @@ $ref: /schemas/display/msm/dpu-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6115-dpu
|
||||
const: qcom,sm6115-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm6115-mdss
|
||||
const: qcom,sm6115-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,92 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8150 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display hf axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8150-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,332 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8150 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description:
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS are mentioned for SM8150 target.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8150-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8150-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8150-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-7nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8150.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sm8150-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
|
||||
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "nrt_bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x420>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8150-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-171428571 {
|
||||
opp-hz = /bits/ 64 <171428571>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-345000000 {
|
||||
opp-hz = /bits/ 64 <345000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-460000000 {
|
||||
opp-hz = /bits/ 64 <460000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8150_MMCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-7nm";
|
||||
reg = <0x0ae96400 0x200>,
|
||||
<0x0ae96600 0x280>,
|
||||
<0x0ae96900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -39,6 +39,13 @@ properties:
|
|||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@ $ref: /schemas/display/msm/mdss-common.yaml#
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8250-mdss
|
||||
const: qcom,sm8250-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
@ -55,7 +54,9 @@ patternProperties:
|
|||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,mdss-dsi-ctrl
|
||||
items:
|
||||
- const: qcom,sm8250-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
|
|
@ -63,6 +64,9 @@ patternProperties:
|
|||
compatible:
|
||||
const: qcom,dsi-phy-7nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -167,7 +171,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
@ -257,7 +261,7 @@ examples:
|
|||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
compatible = "qcom,sm8250-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,120 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8350 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Robert Foss <robert.foss@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8350-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8350.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8350-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8350_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-345000000 {
|
||||
opp-hz = /bits/ 64 <345000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-460000000 {
|
||||
opp-hz = /bits/ 64 <460000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8350 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Robert Foss <robert.foss@linaro.org>
|
||||
|
||||
description:
|
||||
MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
|
||||
DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8350-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display hf axi clock
|
||||
- description: Display sf axi clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: mdp0-mem
|
||||
- const: mdp1-mem
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8350-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8350-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-5nm-8350
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8350.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sm8350-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "nrt_bus", "core";
|
||||
|
||||
iommus = <&apps_smmu 0x820 0x402>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8350-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8350_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-345000000 {
|
||||
opp-hz = /bits/ 64 <345000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-460000000 {
|
||||
opp-hz = /bits/ 64 <460000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0: dsi@ae94000 {
|
||||
compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8350_MMCX>;
|
||||
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8450 Display DPU
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
$ref: /schemas/display/msm/dpu-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8450-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi
|
||||
- description: Display sf axi
|
||||
- description: Display ahb
|
||||
- description: Display lut
|
||||
- description: Display core
|
||||
- description: Display vsync
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: nrt_bus
|
||||
- const: iface
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8450.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8450-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-172000000{
|
||||
opp-hz = /bits/ 64 <172000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-325000000 {
|
||||
opp-hz = /bits/ 64 <325000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-375000000 {
|
||||
opp-hz = /bits/ 64 <375000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8450 Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description:
|
||||
SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
|
||||
DPU display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8450-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB
|
||||
- description: Display hf AXI
|
||||
- description: Display sf AXI
|
||||
- description: Display core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8450-dpu
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sm8450-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dsi-phy-5nm-8450
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sm8450.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,sm8450-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
|
||||
<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
|
||||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "nrt_bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x2800 0x402>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sm8450-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&gcc GCC_DISP_SF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus",
|
||||
"nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-172000000{
|
||||
opp-hz = /bits/ 64 <172000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-325000000 {
|
||||
opp-hz = /bits/ 64 <325000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-375000000 {
|
||||
opp-hz = /bits/ 64 <375000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-160310000{
|
||||
opp-hz = /bits/ 64 <160310000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi0_phy: phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-5nm-8450";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
||||
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
|
||||
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
power-domains = <&rpmhpd SM8450_MMCX>;
|
||||
|
||||
phys = <&dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi1_phy: phy@ae96400 {
|
||||
compatible = "qcom,dsi-phy-5nm-8450";
|
||||
reg = <0x0ae96400 0x200>,
|
||||
<0x0ae96600 0x280>,
|
||||
<0x0ae96900 0x260>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
vdds-supply = <&vreg_dsi_phy>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/auo,a030jtn01.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: AUO A030JTN01 3.0" (320x480 pixels) 24-bit TFT LCD panel
|
||||
|
||||
description: |
|
||||
Delta RGB 8-bit panel found in some Retrogame handhelds
|
||||
|
||||
maintainers:
|
||||
- Paul Cercueil <paul@crapouillou.net>
|
||||
- Christophe Branchereau <cbranchereau@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: auo,a030jtn01
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-supply
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "auo,a030jtn01";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <10000000>;
|
||||
|
||||
reset-gpios = <&gpe 4 GPIO_ACTIVE_LOW>;
|
||||
power-supply = <&lcd_power>;
|
||||
|
||||
backlight = <&backlight>;
|
||||
|
||||
port {
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&panel_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/focaltech,gpt3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Focaltech GPT3 3.0" (640x480 pixels) IPS LCD panel
|
||||
|
||||
maintainers:
|
||||
- Christophe Branchereau <cbranchereau@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: focaltech,gpt3
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-supply
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "focaltech,gpt3";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <3125000>;
|
||||
|
||||
reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
|
||||
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vcc>;
|
||||
|
||||
port {
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&panel_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/himax,hx8394.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Himax HX8394 MIPI-DSI LCD panel controller
|
||||
|
||||
maintainers:
|
||||
- Ondrej Jirman <megi@xff.cz>
|
||||
- Javier Martinez Canillas <javierm@redhat.com>
|
||||
|
||||
description:
|
||||
Device tree bindings for panels based on the Himax HX8394 controller,
|
||||
such as the HannStar HSD060BHW4 720x1440 TFT LCD panel connected with
|
||||
a MIPI-DSI video interface.
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- hannstar,hsd060bhw4
|
||||
- const: himax,hx8394
|
||||
|
||||
reg: true
|
||||
|
||||
reset-gpios: true
|
||||
|
||||
backlight: true
|
||||
|
||||
port: true
|
||||
|
||||
vcc-supply:
|
||||
description: Panel power supply
|
||||
|
||||
iovcc-supply:
|
||||
description: I/O voltage supply
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- backlight
|
||||
- port
|
||||
- vcc-supply
|
||||
- iovcc-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "hannstar,hsd060bhw4", "himax,hx8394";
|
||||
reg = <0>;
|
||||
vcc-supply = <®_2v8_p>;
|
||||
iovcc-supply = <®_1v8_p>;
|
||||
reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&backlight>;
|
||||
|
||||
port {
|
||||
mipi_in_panel: endpoint {
|
||||
remote-endpoint = <&mipi_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -22,8 +22,9 @@ description: |
|
|||
The standard defines the following interface signals for type C:
|
||||
- Power:
|
||||
- Vdd: Power supply for display module
|
||||
Called power-supply in this binding.
|
||||
- Vddi: Logic level supply for interface signals
|
||||
Combined into one in this binding called: power-supply
|
||||
Called io-supply in this binding.
|
||||
- Interface:
|
||||
- CSx: Chip select
|
||||
- SCL: Serial clock
|
||||
|
|
@ -80,6 +81,11 @@ properties:
|
|||
Controller data/command selection (D/CX) in 4-line SPI mode.
|
||||
If not set, the controller is in 3-line SPI mode.
|
||||
|
||||
io-supply:
|
||||
description: |
|
||||
Logic level supply for interface signals (Vddi).
|
||||
No need to set if this is the same as power-supply.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/visionox,vtdr6130.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Visionox VTDR6130 AMOLED DSI Panel
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: panel-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: visionox,vtdr6130
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: DSI virtual channel
|
||||
|
||||
vddio-supply: true
|
||||
vci-supply: true
|
||||
vdd-supply: true
|
||||
port: true
|
||||
reset-gpios: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vddio-supply
|
||||
- vci-supply
|
||||
- vdd-supply
|
||||
- reset-gpios
|
||||
- port
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
panel@0 {
|
||||
compatible = "visionox,vtdr6130";
|
||||
reg = <0>;
|
||||
|
||||
vddio-supply = <&vreg_l12b_1p8>;
|
||||
vci-supply = <&vreg_l13b_3p0>;
|
||||
vdd-supply = <&vreg_l11b_1p2>;
|
||||
|
||||
reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
panel0_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -40,6 +40,7 @@ properties:
|
|||
- renesas,du-r8a77990 # for R-Car E3 compatible DU
|
||||
- renesas,du-r8a77995 # for R-Car D3 compatible DU
|
||||
- renesas,du-r8a779a0 # for R-Car V3U compatible DU
|
||||
- renesas,du-r8a779g0 # for R-Car V4H compatible DU
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -762,6 +763,7 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- renesas,du-r8a779a0
|
||||
- renesas,du-r8a779g0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -63,6 +63,11 @@ properties:
|
|||
reg:
|
||||
description: Location and size of the framebuffer memory
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description: Phandle to a node describing the memory to be used for the
|
||||
framebuffer. If present, overrides the "reg" property (if one exists).
|
||||
|
||||
clocks:
|
||||
description: List of clocks used by the framebuffer.
|
||||
|
||||
|
|
@ -94,6 +99,7 @@ properties:
|
|||
* `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b
|
||||
* `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
|
||||
* `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
|
||||
* `x8b8g8r8` - 32-bit pixels, d[23:16]=b, d[15:8]=g, d[7:0]=r
|
||||
enum:
|
||||
- a1r5g5b5
|
||||
- a2r10g10b10
|
||||
|
|
@ -105,6 +111,7 @@ properties:
|
|||
- x1r5g5b5
|
||||
- x2r10g10b10
|
||||
- x8r8g8b8
|
||||
- x8b8g8r8
|
||||
|
||||
display:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
|
|
|||
|
|
@ -43,6 +43,9 @@ properties:
|
|||
vddio-supply:
|
||||
description: phandle to VDD I/O supply regulator
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
|
|
@ -53,7 +56,6 @@ allOf:
|
|||
contains:
|
||||
enum:
|
||||
- qcom,hdmi-phy-8660
|
||||
- qcom,hdmi-phy-8960
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
|
@ -63,6 +65,24 @@ allOf:
|
|||
- const: slave_iface
|
||||
vddio-supply: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,hdmi-phy-8960
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: slave_iface
|
||||
- const: pxo
|
||||
vddio-supply: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -96,9 +116,10 @@ examples:
|
|||
"hdmi_pll";
|
||||
reg = <0x4a00400 0x60>,
|
||||
<0x4a00500 0x100>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&mmcc 1>;
|
||||
clock-names = "slave_iface";
|
||||
clocks = <&clk 21>;
|
||||
clock-names = "slave_iface", "pxo";
|
||||
clocks = <&clk 21>, <&pxo_board>;
|
||||
core-vdda-supply = <&pm8921_hdmi_mvs>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reserved-memory/framebuffer.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: /reserved-memory framebuffer node bindings
|
||||
|
||||
maintainers:
|
||||
- devicetree-spec@vger.kernel.org
|
||||
|
||||
allOf:
|
||||
- $ref: reserved-memory.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: framebuffer
|
||||
description: >
|
||||
This indicates a region of memory meant to be used as a framebuffer for
|
||||
a set of display devices. It can be used by an operating system to keep
|
||||
the framebuffer from being overwritten and use it as the backing memory
|
||||
for a display device (such as simple-framebuffer).
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
compatible = "foo";
|
||||
model = "foo";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen {
|
||||
framebuffer {
|
||||
compatible = "simple-framebuffer";
|
||||
memory-region = <&fb>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
fb: framebuffer@80000000 {
|
||||
compatible = "framebuffer";
|
||||
reg = <0x80000000 0x007e9000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -29,7 +29,10 @@ Things between square brackets are optional.
|
|||
Valid names are::
|
||||
|
||||
- NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
|
||||
- NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
|
||||
encoding, and a black level equal to the blanking level.
|
||||
- PAL: 576i output, with the CCIR System-B TV mode and PAL color encoding
|
||||
- PAL-M: 480i output, with the CCIR System-M TV mode and PAL color encoding
|
||||
|
||||
If 'M' is specified in the mode_option argument (after <yres> and before
|
||||
<bpp> and <refresh>, if specified) the timings will be calculated using
|
||||
|
|
@ -70,6 +73,8 @@ Valid options are::
|
|||
- reflect_y (boolean): Perform an axial symmetry on the Y axis
|
||||
- rotate (integer): Rotate the initial framebuffer by x
|
||||
degrees. Valid values are 0, 90, 180 and 270.
|
||||
- tv_mode: Analog TV mode. One of "NTSC", "NTSC-443", "NTSC-J", "PAL",
|
||||
"PAL-M", "PAL-N", or "SECAM".
|
||||
- panel_orientation, one of "normal", "upside_down", "left_side_up", or
|
||||
"right_side_up". For KMS drivers only, this sets the "panel orientation"
|
||||
property on the kms connector as hint for kms users.
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version
|
||||
Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3
|
||||
Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0
|
||||
Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2
|
||||
Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1
|
||||
SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1
|
||||
Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1
|
||||
Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
|
||||
Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version, MP0 version
|
||||
Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3, n/a
|
||||
Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0, 10.0.0
|
||||
Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2, 11.0.3
|
||||
Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1, 10.0.1
|
||||
SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0
|
||||
Ryzen 5000 series / Ryzen 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1
|
||||
Ryzen 6000 series / Ryzen 7x35 series, YELLOW CARP / Rembrandt / Rembrandt+, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3
|
||||
Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
|
||||
Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8
|
||||
|
|
|
|||
|
|
|
@ -22,3 +22,5 @@ AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN
|
|||
AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
|
||||
AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
|
||||
AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
|
||||
AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0
|
||||
AMD Radeon RX 7600M (XT) /7700S /7600S, , DCN 3.2.1, 11.0.2, VCN 4.0.4, 6.0.2
|
||||
|
|
|
|||
|
|
|
@ -37,7 +37,7 @@ Accelerated Processing Units (APU) Info
|
|||
|
||||
.. csv-table::
|
||||
:header-rows: 1
|
||||
:widths: 3, 2, 2, 1, 1, 1
|
||||
:widths: 3, 2, 2, 1, 1, 1, 1
|
||||
:file: ./apu-asic-info-table.csv
|
||||
|
||||
Discrete GPU Info
|
||||
|
|
|
|||
|
|
@ -188,6 +188,13 @@ Bridge Helper Reference
|
|||
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c
|
||||
:export:
|
||||
|
||||
MIPI-DSI bridge operation
|
||||
-------------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c
|
||||
:doc: dsi bridge operations
|
||||
|
||||
|
||||
Bridge Connector Helper Reference
|
||||
---------------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -520,6 +520,12 @@ HDMI Specific Connector Properties
|
|||
.. kernel-doc:: drivers/gpu/drm/drm_connector.c
|
||||
:doc: HDMI connector properties
|
||||
|
||||
Analog TV Specific Connector Properties
|
||||
---------------------------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_connector.c
|
||||
:doc: Analog TV Connector Properties
|
||||
|
||||
Standard CRTC Properties
|
||||
------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -402,19 +402,19 @@ It's possible to run the IGT-tests in a VM in two ways:
|
|||
1. Use IGT inside a VM
|
||||
2. Use IGT from the host machine and write the results in a shared directory.
|
||||
|
||||
As follow, there is an example of using a VM with a shared directory with
|
||||
the host machine to run igt-tests. As an example it's used virtme::
|
||||
Following is an example of using a VM with a shared directory with
|
||||
the host machine to run igt-tests. This example uses virtme::
|
||||
|
||||
$ virtme-run --rwdir /path/for/shared_dir --kdir=path/for/kernel/directory --mods=auto
|
||||
|
||||
Run the igt-tests in the guest machine, as example it's ran the 'kms_flip'
|
||||
Run the igt-tests in the guest machine. This example runs the 'kms_flip'
|
||||
tests::
|
||||
|
||||
$ /path/for/igt-gpu-tools/scripts/run-tests.sh -p -s -t "kms_flip.*" -v
|
||||
|
||||
In this example, instead of build the igt_runner, Piglit is used
|
||||
(-p option); it's created html summary of the tests results and it's saved
|
||||
in the folder "igt-gpu-tools/results"; it's executed only the igt-tests
|
||||
In this example, instead of building the igt_runner, Piglit is used
|
||||
(-p option). It creates an HTML summary of the test results and saves
|
||||
them in the folder "igt-gpu-tools/results". It executes only the igt-tests
|
||||
matching the -t option.
|
||||
|
||||
Display CRC Support
|
||||
|
|
|
|||
|
|
@ -508,17 +508,18 @@ Clean up the debugfs support
|
|||
|
||||
There's a bunch of issues with it:
|
||||
|
||||
- The drm_info_list ->show() function doesn't even bother to cast to the drm
|
||||
structure for you. This is lazy.
|
||||
- Convert drivers to support the drm_debugfs_add_files() function instead of
|
||||
the drm_debugfs_create_files() function.
|
||||
|
||||
- Improve late-register debugfs by rolling out the same debugfs pre-register
|
||||
infrastructure for connector and crtc too. That way, the drivers won't need to
|
||||
split their setup code into init and register anymore.
|
||||
|
||||
- We probably want to have some support for debugfs files on crtc/connectors and
|
||||
maybe other kms objects directly in core. There's even drm_print support in
|
||||
the funcs for these objects to dump kms state, so it's all there. And then the
|
||||
->show() functions should obviously give you a pointer to the right object.
|
||||
|
||||
- The drm_info_list stuff is centered on drm_minor instead of drm_device. For
|
||||
anything we want to print drm_device (or maybe drm_file) is the right thing.
|
||||
|
||||
- The drm_driver->debugfs_init hooks we have is just an artifact of the old
|
||||
midlayered load sequence. DRM debugfs should work more like sysfs, where you
|
||||
can create properties/files for an object anytime you want, and the core
|
||||
|
|
@ -527,8 +528,6 @@ There's a bunch of issues with it:
|
|||
this (together with the drm_minor->drm_device move) would allow us to remove
|
||||
debugfs_init.
|
||||
|
||||
Previous RFC that hasn't landed yet: https://lore.kernel.org/dri-devel/20200513114130.28641-2-wambui.karugax@gmail.com/
|
||||
|
||||
Contact: Daniel Vetter
|
||||
|
||||
Level: Intermediate
|
||||
|
|
|
|||
|
|
@ -54,6 +54,25 @@ VEC (Composite TV out) encoder
|
|||
.. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
|
||||
:doc: VC4 SDTV module
|
||||
|
||||
KUnit Tests
|
||||
===========
|
||||
|
||||
The VC4 Driver uses KUnit to perform driver-specific unit and
|
||||
integration tests.
|
||||
|
||||
These tests are using a mock driver and can be ran using the
|
||||
command below, on either arm or arm64 architectures,
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ ./tools/testing/kunit/kunit.py run \
|
||||
--kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
|
||||
--cross_compile aarch64-linux-gnu- --arch arm64
|
||||
|
||||
Parts of the driver that are currently covered by tests are:
|
||||
* The HVS to PixelValve dynamic FIFO assignment, for the BCM2835-7
|
||||
and BCM2711.
|
||||
|
||||
Memory Management and 3D Command Submission
|
||||
===========================================
|
||||
|
||||
|
|
|
|||
|
|
@ -221,6 +221,7 @@ Code Seq# Include File Comments
|
|||
'a' 00-0F drivers/crypto/qat/qat_common/adf_cfg_common.h conflict! qat driver
|
||||
'b' 00-FF conflict! bit3 vme host bridge
|
||||
<mailto:natalia@nikhefk.nikhef.nl>
|
||||
'b' 00-0F linux/dma-buf.h conflict!
|
||||
'c' all linux/cm4000_cs.h conflict!
|
||||
'c' 00-7F linux/comstats.h conflict!
|
||||
'c' 00-7F linux/coda.h conflict!
|
||||
|
|
|
|||
|
|
@ -262,7 +262,12 @@ the second byte and Y'\ :sub:`7-0` in the third byte.
|
|||
=================
|
||||
|
||||
These formats, commonly referred to as YUYV or YUY2, subsample the chroma
|
||||
components horizontally by 2, storing 2 pixels in 4 bytes.
|
||||
components horizontally by 2, storing 2 pixels in a container. The container
|
||||
is 32-bits for 8-bit formats, and 64-bits for 10+-bit formats.
|
||||
|
||||
The packed YUYV formats with more than 8 bits per component are stored as four
|
||||
16-bit little-endian words. Each word's most significant bits contain one
|
||||
component, and the least significant bits are zero padding.
|
||||
|
||||
.. raw:: latex
|
||||
|
||||
|
|
@ -270,7 +275,7 @@ components horizontally by 2, storing 2 pixels in 4 bytes.
|
|||
|
||||
.. tabularcolumns:: |p{3.4cm}|p{1.2cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|
|
||||
|
||||
.. flat-table:: Packed YUV 4:2:2 Formats
|
||||
.. flat-table:: Packed YUV 4:2:2 Formats in 32-bit container
|
||||
:header-rows: 1
|
||||
:stub-columns: 0
|
||||
|
||||
|
|
@ -337,6 +342,46 @@ components horizontally by 2, storing 2 pixels in 4 bytes.
|
|||
- Y'\ :sub:`3`
|
||||
- Cb\ :sub:`2`
|
||||
|
||||
.. tabularcolumns:: |p{3.4cm}|p{1.2cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|p{0.8cm}|
|
||||
|
||||
.. flat-table:: Packed YUV 4:2:2 Formats in 64-bit container
|
||||
:header-rows: 1
|
||||
:stub-columns: 0
|
||||
|
||||
* - Identifier
|
||||
- Code
|
||||
- Word 0
|
||||
- Word 1
|
||||
- Word 2
|
||||
- Word 3
|
||||
* .. _V4L2-PIX-FMT-Y210:
|
||||
|
||||
- ``V4L2_PIX_FMT_Y210``
|
||||
- 'Y210'
|
||||
|
||||
- Y'\ :sub:`0` (bits 15-6)
|
||||
- Cb\ :sub:`0` (bits 15-6)
|
||||
- Y'\ :sub:`1` (bits 15-6)
|
||||
- Cr\ :sub:`0` (bits 15-6)
|
||||
* .. _V4L2-PIX-FMT-Y212:
|
||||
|
||||
- ``V4L2_PIX_FMT_Y212``
|
||||
- 'Y212'
|
||||
|
||||
- Y'\ :sub:`0` (bits 15-4)
|
||||
- Cb\ :sub:`0` (bits 15-4)
|
||||
- Y'\ :sub:`1` (bits 15-4)
|
||||
- Cr\ :sub:`0` (bits 15-4)
|
||||
* .. _V4L2-PIX-FMT-Y216:
|
||||
|
||||
- ``V4L2_PIX_FMT_Y216``
|
||||
- 'Y216'
|
||||
|
||||
- Y'\ :sub:`0` (bits 15-0)
|
||||
- Cb\ :sub:`0` (bits 15-0)
|
||||
- Y'\ :sub:`1` (bits 15-0)
|
||||
- Cr\ :sub:`0` (bits 15-0)
|
||||
|
||||
.. raw:: latex
|
||||
|
||||
\normalsize
|
||||
|
|
|
|||
|
|
@ -763,6 +763,200 @@ nomenclature that instead use the order of components as seen in a 24- or
|
|||
\normalsize
|
||||
|
||||
|
||||
10 Bits Per Component
|
||||
=====================
|
||||
|
||||
These formats store a 30-bit RGB triplet with an optional 2 bit alpha in four
|
||||
bytes. They are named based on the order of the RGB components as seen in a
|
||||
32-bit word, which is then stored in memory in little endian byte order
|
||||
(unless otherwise noted by the presence of bit 31 in the 4CC value), and on the
|
||||
number of bits for each component.
|
||||
|
||||
.. raw:: latex
|
||||
|
||||
\begingroup
|
||||
\tiny
|
||||
\setlength{\tabcolsep}{2pt}
|
||||
|
||||
.. tabularcolumns:: |p{2.8cm}|p{2.0cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|
|
||||
|
||||
|
||||
.. flat-table:: RGB Formats 10 Bits Per Color Component
|
||||
:header-rows: 2
|
||||
:stub-columns: 0
|
||||
|
||||
* - Identifier
|
||||
- Code
|
||||
- :cspan:`7` Byte 0 in memory
|
||||
- :cspan:`7` Byte 1
|
||||
- :cspan:`7` Byte 2
|
||||
- :cspan:`7` Byte 3
|
||||
* -
|
||||
-
|
||||
- 7
|
||||
- 6
|
||||
- 5
|
||||
- 4
|
||||
- 3
|
||||
- 2
|
||||
- 1
|
||||
- 0
|
||||
|
||||
- 7
|
||||
- 6
|
||||
- 5
|
||||
- 4
|
||||
- 3
|
||||
- 2
|
||||
- 1
|
||||
- 0
|
||||
|
||||
- 7
|
||||
- 6
|
||||
- 5
|
||||
- 4
|
||||
- 3
|
||||
- 2
|
||||
- 1
|
||||
- 0
|
||||
|
||||
- 7
|
||||
- 6
|
||||
- 5
|
||||
- 4
|
||||
- 3
|
||||
- 2
|
||||
- 1
|
||||
- 0
|
||||
* .. _V4L2-PIX-FMT-RGBX1010102:
|
||||
|
||||
- ``V4L2_PIX_FMT_RGBX1010102``
|
||||
- 'RX30'
|
||||
|
||||
- b\ :sub:`5`
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
- x
|
||||
- x
|
||||
|
||||
- g\ :sub:`3`
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- b\ :sub:`9`
|
||||
- b\ :sub:`8`
|
||||
- b\ :sub:`7`
|
||||
- b\ :sub:`6`
|
||||
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
- g\ :sub:`9`
|
||||
- g\ :sub:`8`
|
||||
- g\ :sub:`7`
|
||||
- g\ :sub:`6`
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
|
||||
- r\ :sub:`9`
|
||||
- r\ :sub:`8`
|
||||
- r\ :sub:`7`
|
||||
- r\ :sub:`6`
|
||||
- r\ :sub:`5`
|
||||
- r\ :sub:`4`
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
-
|
||||
* .. _V4L2-PIX-FMT-RGBA1010102:
|
||||
|
||||
- ``V4L2_PIX_FMT_RGBA1010102``
|
||||
- 'RA30'
|
||||
|
||||
- b\ :sub:`5`
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
- a\ :sub:`1`
|
||||
- a\ :sub:`0`
|
||||
|
||||
- g\ :sub:`3`
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- b\ :sub:`9`
|
||||
- b\ :sub:`8`
|
||||
- b\ :sub:`7`
|
||||
- b\ :sub:`6`
|
||||
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
- g\ :sub:`9`
|
||||
- g\ :sub:`8`
|
||||
- g\ :sub:`7`
|
||||
- g\ :sub:`6`
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
|
||||
- r\ :sub:`9`
|
||||
- r\ :sub:`8`
|
||||
- r\ :sub:`7`
|
||||
- r\ :sub:`6`
|
||||
- r\ :sub:`5`
|
||||
- r\ :sub:`4`
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
-
|
||||
* .. _V4L2-PIX-FMT-ARGB2101010:
|
||||
|
||||
- ``V4L2_PIX_FMT_ARGB2101010``
|
||||
- 'AR30'
|
||||
|
||||
- b\ :sub:`7`
|
||||
- b\ :sub:`6`
|
||||
- b\ :sub:`5`
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
- g\ :sub:`3`
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- b\ :sub:`9`
|
||||
- b\ :sub:`8`
|
||||
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
- g\ :sub:`9`
|
||||
- g\ :sub:`8`
|
||||
- g\ :sub:`7`
|
||||
- g\ :sub:`6`
|
||||
|
||||
- a\ :sub:`1`
|
||||
- a\ :sub:`0`
|
||||
- r\ :sub:`9`
|
||||
- r\ :sub:`8`
|
||||
- r\ :sub:`7`
|
||||
- r\ :sub:`6`
|
||||
- r\ :sub:`5`
|
||||
- r\ :sub:`4`
|
||||
-
|
||||
|
||||
.. raw:: latex
|
||||
|
||||
\endgroup
|
||||
|
||||
|
||||
Deprecated RGB Formats
|
||||
======================
|
||||
|
||||
|
|
|
|||
|
|
@ -949,6 +949,43 @@ The following tables list existing packed RGB formats.
|
|||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-BGR666-1X18:
|
||||
|
||||
- MEDIA_BUS_FMT_BGR666_1X18
|
||||
- 0x1023
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
- b\ :sub:`5`
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
- g\ :sub:`3`
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- r\ :sub:`5`
|
||||
- r\ :sub:`4`
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-RBG888-1X24:
|
||||
|
||||
- MEDIA_BUS_FMT_RBG888_1X24
|
||||
|
|
@ -1023,6 +1060,80 @@ The following tables list existing packed RGB formats.
|
|||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-BGR666-1X24_CPADHI:
|
||||
|
||||
- MEDIA_BUS_FMT_BGR666_1X24_CPADHI
|
||||
- 0x1024
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
- 0
|
||||
- 0
|
||||
- b\ :sub:`5`
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
- 0
|
||||
- 0
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
- g\ :sub:`3`
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- 0
|
||||
- 0
|
||||
- r\ :sub:`5`
|
||||
- r\ :sub:`4`
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-RGB565-1X24_CPADHI:
|
||||
|
||||
- MEDIA_BUS_FMT_RGB565_1X24_CPADHI
|
||||
- 0x1022
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
-
|
||||
- 0
|
||||
- 0
|
||||
- 0
|
||||
- r\ :sub:`4`
|
||||
- r\ :sub:`3`
|
||||
- r\ :sub:`2`
|
||||
- r\ :sub:`1`
|
||||
- r\ :sub:`0`
|
||||
- 0
|
||||
- 0
|
||||
- g\ :sub:`5`
|
||||
- g\ :sub:`4`
|
||||
- g\ :sub:`3`
|
||||
- g\ :sub:`2`
|
||||
- g\ :sub:`1`
|
||||
- g\ :sub:`0`
|
||||
- 0
|
||||
- 0
|
||||
- 0
|
||||
- b\ :sub:`4`
|
||||
- b\ :sub:`3`
|
||||
- b\ :sub:`2`
|
||||
- b\ :sub:`1`
|
||||
- b\ :sub:`0`
|
||||
* .. _MEDIA-BUS-FMT-BGR888-1X24:
|
||||
|
||||
- MEDIA_BUS_FMT_BGR888_1X24
|
||||
|
|
|
|||
62
MAINTAINERS
62
MAINTAINERS
|
|
@ -6417,6 +6417,14 @@ S: Maintained
|
|||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/gpu/drm/tiny/gm12u320.c
|
||||
|
||||
DRM DRIVER FOR HIMAX HX8394 MIPI-DSI LCD panels
|
||||
M: Ondrej Jirman <megi@xff.cz>
|
||||
M: Javier Martinez Canillas <javierm@redhat.com>
|
||||
S: Maintained
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml
|
||||
F: drivers/gpu/drm/panel/panel-himax-hx8394.c
|
||||
|
||||
DRM DRIVER FOR HX8357D PANELS
|
||||
M: Emma Anholt <emma@anholt.net>
|
||||
S: Maintained
|
||||
|
|
@ -6438,11 +6446,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
|
|||
F: Documentation/devicetree/bindings/display/ilitek,ili9486.yaml
|
||||
F: drivers/gpu/drm/tiny/ili9486.c
|
||||
|
||||
DRM DRIVER FOR INTEL I810 VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/i810/
|
||||
F: include/uapi/drm/i810_drm.h
|
||||
|
||||
DRM DRIVER FOR JADARD JD9365DA-H3 MIPI-DSI LCD PANELS
|
||||
M: Jagan Teki <jagan@edgeble.ai>
|
||||
S: Maintained
|
||||
|
|
@ -6471,11 +6474,6 @@ S: Maintained
|
|||
F: Documentation/devicetree/bindings/display/panel/mantix,mlaf057we51-x.yaml
|
||||
F: drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c
|
||||
|
||||
DRM DRIVER FOR MATROX G200/G400 GRAPHICS CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/mga/
|
||||
F: include/uapi/drm/mga_drm.h
|
||||
|
||||
DRM DRIVER FOR MGA G200 GRAPHICS CHIPS
|
||||
M: Dave Airlie <airlied@redhat.com>
|
||||
R: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
|
|
@ -6594,11 +6592,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
|
|||
F: drivers/gpu/drm/qxl/
|
||||
F: include/uapi/drm/qxl_drm.h
|
||||
|
||||
DRM DRIVER FOR RAGE 128 VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/r128/
|
||||
F: include/uapi/drm/r128_drm.h
|
||||
|
||||
DRM DRIVER FOR RAYDIUM RM67191 PANELS
|
||||
M: Robert Chiras <robert.chiras@nxp.com>
|
||||
S: Maintained
|
||||
|
|
@ -6626,11 +6619,6 @@ S: Maintained
|
|||
F: Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml
|
||||
F: drivers/gpu/drm/panel/panel-sitronix-st7703.c
|
||||
|
||||
DRM DRIVER FOR SAVAGE VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/savage/
|
||||
F: include/uapi/drm/savage_drm.h
|
||||
|
||||
DRM DRIVER FOR FIRMWARE FRAMEBUFFERS
|
||||
M: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
M: Javier Martinez Canillas <javierm@redhat.com>
|
||||
|
|
@ -6646,11 +6634,6 @@ F: include/drm/drm_aperture.h
|
|||
F: include/linux/aperture.h
|
||||
F: include/video/nomodeset.h
|
||||
|
||||
DRM DRIVER FOR SIS VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/sis/
|
||||
F: include/uapi/drm/sis_drm.h
|
||||
|
||||
DRM DRIVER FOR SITRONIX ST7586 PANELS
|
||||
M: David Lechner <david@lechnology.com>
|
||||
S: Maintained
|
||||
|
|
@ -6678,10 +6661,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
|
|||
F: Documentation/devicetree/bindings/display/ste,mcde.yaml
|
||||
F: drivers/gpu/drm/mcde/
|
||||
|
||||
DRM DRIVER FOR TDFX VIDEO CARDS
|
||||
S: Orphan / Obsolete
|
||||
F: drivers/gpu/drm/tdfx/
|
||||
|
||||
DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE
|
||||
M: Jagan Teki <jagan@amarulasolutions.com>
|
||||
S: Maintained
|
||||
|
|
@ -6781,6 +6760,16 @@ C: irc://irc.oftc.net/dri-devel
|
|||
T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git
|
||||
F: Documentation/accel/
|
||||
F: drivers/accel/
|
||||
F: include/drm/drm_accel.h
|
||||
|
||||
DRM ACCEL DRIVERS FOR INTEL VPU
|
||||
M: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
|
||||
M: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/accel/ivpu/
|
||||
F: include/uapi/drm/ivpu_accel.h
|
||||
|
||||
DRM DRIVERS FOR ALLWINNER A10
|
||||
M: Maxime Ripard <mripard@kernel.org>
|
||||
|
|
@ -6851,7 +6840,7 @@ M: Philipp Zabel <p.zabel@pengutronix.de>
|
|||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/display/imx/
|
||||
F: drivers/gpu/drm/imx/
|
||||
F: drivers/gpu/drm/imx/ipuv3/
|
||||
F: drivers/gpu/ipu-v3/
|
||||
|
||||
DRM DRIVERS FOR FREESCALE IMX BRIDGE
|
||||
|
|
@ -6874,9 +6863,10 @@ F: drivers/gpu/drm/gma500/
|
|||
DRM DRIVERS FOR HISILICON
|
||||
M: Xinliang Liu <xinliang.liu@linaro.org>
|
||||
M: Tian Tao <tiantao6@hisilicon.com>
|
||||
R: John Stultz <jstultz@google.com>
|
||||
R: Xinwei Kong <kong.kongxinwei@hisilicon.com>
|
||||
R: Chen Feng <puck.chen@hisilicon.com>
|
||||
R: Sumit Semwal <sumit.semwal@linaro.org>
|
||||
R: Yongqin Liu <yongqin.liu@linaro.org>
|
||||
R: John Stultz <jstultz@google.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
|
|
@ -6917,7 +6907,7 @@ M: Thierry Reding <thierry.reding@gmail.com>
|
|||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-tegra@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/tegra/linux.git
|
||||
T: git https://gitlab.freedesktop.org/drm/tegra.git
|
||||
F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
|
||||
F: Documentation/devicetree/bindings/gpu/host1x/
|
||||
F: drivers/gpu/drm/tegra/
|
||||
|
|
@ -8915,13 +8905,15 @@ F: block/partitions/efi.*
|
|||
|
||||
HABANALABS PCI DRIVER
|
||||
M: Oded Gabbay <ogabbay@kernel.org>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
C: irc://irc.oftc.net/dri-devel
|
||||
T: git https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux.git
|
||||
F: Documentation/ABI/testing/debugfs-driver-habanalabs
|
||||
F: Documentation/ABI/testing/sysfs-driver-habanalabs
|
||||
F: drivers/misc/habanalabs/
|
||||
F: drivers/accel/habanalabs/
|
||||
F: include/trace/events/habanalabs.h
|
||||
F: include/uapi/misc/habanalabs.h
|
||||
F: include/uapi/drm/habanalabs_accel.h
|
||||
|
||||
HACKRF MEDIA DRIVER
|
||||
M: Antti Palosaari <crope@iki.fi>
|
||||
|
|
|
|||
|
|
@ -188,3 +188,4 @@ obj-$(CONFIG_COUNTER) += counter/
|
|||
obj-$(CONFIG_MOST) += most/
|
||||
obj-$(CONFIG_PECI) += peci/
|
||||
obj-$(CONFIG_HTE) += hte/
|
||||
obj-$(CONFIG_DRM_ACCEL) += accel/
|
||||
|
|
|
|||
|
|
@ -6,9 +6,10 @@
|
|||
# as, but not limited to, Machine-Learning and Deep-Learning acceleration
|
||||
# devices
|
||||
#
|
||||
if DRM
|
||||
|
||||
menuconfig DRM_ACCEL
|
||||
bool "Compute Acceleration Framework"
|
||||
depends on DRM
|
||||
help
|
||||
Framework for device drivers of compute acceleration devices, such
|
||||
as, but not limited to, Machine-Learning and Deep-Learning
|
||||
|
|
@ -22,3 +23,8 @@ menuconfig DRM_ACCEL
|
|||
major number than GPUs, and will be exposed to user-space using
|
||||
different device files, called accel/accel* (in /dev, sysfs
|
||||
and debugfs).
|
||||
|
||||
source "drivers/accel/habanalabs/Kconfig"
|
||||
source "drivers/accel/ivpu/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
obj-y += habanalabs/
|
||||
obj-y += ivpu/
|
||||
|
|
@ -3,8 +3,10 @@
|
|||
# HabanaLabs AI accelerators driver
|
||||
#
|
||||
|
||||
config HABANA_AI
|
||||
tristate "HabanaAI accelerators (habanalabs)"
|
||||
config DRM_ACCEL_HABANALABS
|
||||
tristate "HabanaLabs AI accelerators"
|
||||
depends on DRM_ACCEL
|
||||
depends on X86_64
|
||||
depends on PCI && HAS_IOMEM
|
||||
select GENERIC_ALLOCATOR
|
||||
select HWMON
|
||||
|
|
@ -19,7 +21,7 @@ config HABANA_AI
|
|||
the user to submit workloads to the devices.
|
||||
|
||||
The user-space interface is described in
|
||||
include/uapi/misc/habanalabs.h
|
||||
include/uapi/drm/habanalabs_accel.h
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
# Makefile for HabanaLabs AI accelerators driver
|
||||
#
|
||||
|
||||
obj-$(CONFIG_HABANA_AI) := habanalabs.o
|
||||
obj-$(CONFIG_DRM_ACCEL_HABANALABS) := habanalabs.o
|
||||
|
||||
include $(src)/common/Makefile
|
||||
habanalabs-y += $(HL_COMMON_FILES)
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* All Rights Reserved.
|
||||
*/
|
||||
|
||||
#include <uapi/misc/habanalabs.h>
|
||||
#include <uapi/drm/habanalabs_accel.h>
|
||||
#include "habanalabs.h"
|
||||
|
||||
#include <linux/mm.h>
|
||||
|
|
@ -88,6 +88,7 @@ static void cb_fini(struct hl_device *hdev, struct hl_cb *cb)
|
|||
static void cb_do_release(struct hl_device *hdev, struct hl_cb *cb)
|
||||
{
|
||||
if (cb->is_pool) {
|
||||
atomic_set(&cb->is_handle_destroyed, 0);
|
||||
spin_lock(&hdev->cb_pool_lock);
|
||||
list_add(&cb->pool_list, &hdev->cb_pool);
|
||||
spin_unlock(&hdev->cb_pool_lock);
|
||||
|
|
@ -298,8 +299,25 @@ int hl_cb_create(struct hl_device *hdev, struct hl_mem_mgr *mmg,
|
|||
|
||||
int hl_cb_destroy(struct hl_mem_mgr *mmg, u64 cb_handle)
|
||||
{
|
||||
struct hl_cb *cb;
|
||||
int rc;
|
||||
|
||||
cb = hl_cb_get(mmg, cb_handle);
|
||||
if (!cb) {
|
||||
dev_dbg(mmg->dev, "CB destroy failed, no CB was found for handle %#llx\n",
|
||||
cb_handle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Make sure that CB handle isn't destroyed more than once */
|
||||
rc = atomic_cmpxchg(&cb->is_handle_destroyed, 0, 1);
|
||||
hl_cb_put(cb);
|
||||
if (rc) {
|
||||
dev_dbg(mmg->dev, "CB destroy failed, handle %#llx was already destroyed\n",
|
||||
cb_handle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rc = hl_mmap_mem_buf_put_handle(mmg, cb_handle);
|
||||
if (rc < 0)
|
||||
return rc; /* Invalid handle */
|
||||
|
|
@ -350,7 +368,7 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
int rc;
|
||||
|
||||
if (!hl_device_operational(hdev, &status)) {
|
||||
dev_warn_ratelimited(hdev->dev,
|
||||
dev_dbg_ratelimited(hdev->dev,
|
||||
"Device is %s. Can't execute CB IOCTL\n",
|
||||
hdev->status[status]);
|
||||
return -EBUSY;
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* All Rights Reserved.
|
||||
*/
|
||||
|
||||
#include <uapi/misc/habanalabs.h>
|
||||
#include <uapi/drm/habanalabs_accel.h>
|
||||
#include "habanalabs.h"
|
||||
|
||||
#include <linux/uaccess.h>
|
||||
|
|
@ -13,7 +13,8 @@
|
|||
|
||||
#define HL_CS_FLAGS_TYPE_MASK (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT | \
|
||||
HL_CS_FLAGS_COLLECTIVE_WAIT | HL_CS_FLAGS_RESERVE_SIGNALS_ONLY | \
|
||||
HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND)
|
||||
HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND | \
|
||||
HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
|
||||
|
||||
|
||||
#define MAX_TS_ITER_NUM 10
|
||||
|
|
@ -397,8 +398,16 @@ static void hl_complete_job(struct hl_device *hdev, struct hl_cs_job *job)
|
|||
* flow by calling 'hl_hw_queue_update_ci'.
|
||||
*/
|
||||
if (cs_needs_completion(cs) &&
|
||||
(job->queue_type == QUEUE_TYPE_EXT || job->queue_type == QUEUE_TYPE_HW))
|
||||
(job->queue_type == QUEUE_TYPE_EXT || job->queue_type == QUEUE_TYPE_HW)) {
|
||||
|
||||
/* In CS based completions, the timestamp is already available,
|
||||
* so no need to extract it from job
|
||||
*/
|
||||
if (hdev->asic_prop.completion_mode == HL_COMPLETION_MODE_JOB)
|
||||
cs->completion_timestamp = job->timestamp;
|
||||
|
||||
cs_put(cs);
|
||||
}
|
||||
|
||||
hl_cs_job_put(job);
|
||||
}
|
||||
|
|
@ -775,7 +784,7 @@ out:
|
|||
}
|
||||
|
||||
if (cs->timestamp) {
|
||||
cs->fence->timestamp = ktime_get();
|
||||
cs->fence->timestamp = cs->completion_timestamp;
|
||||
hl_push_cs_outcome(hdev, &cs->ctx->outcome_store, cs->sequence,
|
||||
cs->fence->timestamp, cs->fence->error);
|
||||
}
|
||||
|
|
@ -1117,6 +1126,27 @@ void hl_release_pending_user_interrupts(struct hl_device *hdev)
|
|||
wake_pending_user_interrupt_threads(interrupt);
|
||||
}
|
||||
|
||||
static void force_complete_cs(struct hl_device *hdev)
|
||||
{
|
||||
struct hl_cs *cs;
|
||||
|
||||
spin_lock(&hdev->cs_mirror_lock);
|
||||
|
||||
list_for_each_entry(cs, &hdev->cs_mirror_list, mirror_node) {
|
||||
cs->fence->error = -EIO;
|
||||
complete_all(&cs->fence->completion);
|
||||
}
|
||||
|
||||
spin_unlock(&hdev->cs_mirror_lock);
|
||||
}
|
||||
|
||||
void hl_abort_waitings_for_completion(struct hl_device *hdev)
|
||||
{
|
||||
force_complete_cs(hdev);
|
||||
force_complete_multi_cs(hdev);
|
||||
hl_release_pending_user_interrupts(hdev);
|
||||
}
|
||||
|
||||
static void job_wq_completion(struct work_struct *work)
|
||||
{
|
||||
struct hl_cs_job *job = container_of(work, struct hl_cs_job,
|
||||
|
|
@ -1274,6 +1304,8 @@ static enum hl_cs_type hl_cs_get_cs_type(u32 cs_type_flags)
|
|||
return CS_UNRESERVE_SIGNALS;
|
||||
else if (cs_type_flags & HL_CS_FLAGS_ENGINE_CORE_COMMAND)
|
||||
return CS_TYPE_ENGINE_CORE;
|
||||
else if (cs_type_flags & HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
|
||||
return CS_TYPE_FLUSH_PCI_HBW_WRITES;
|
||||
else
|
||||
return CS_TYPE_DEFAULT;
|
||||
}
|
||||
|
|
@ -1286,6 +1318,13 @@ static int hl_cs_sanity_checks(struct hl_fpriv *hpriv, union hl_cs_args *args)
|
|||
enum hl_device_status status;
|
||||
enum hl_cs_type cs_type;
|
||||
bool is_sync_stream;
|
||||
int i;
|
||||
|
||||
for (i = 0 ; i < sizeof(args->in.pad) ; i++)
|
||||
if (args->in.pad[i]) {
|
||||
dev_dbg(hdev->dev, "Padding bytes must be 0\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!hl_device_operational(hdev, &status)) {
|
||||
return -EBUSY;
|
||||
|
|
@ -2422,6 +2461,21 @@ static int cs_ioctl_engine_cores(struct hl_fpriv *hpriv, u64 engine_cores,
|
|||
return rc;
|
||||
}
|
||||
|
||||
static int cs_ioctl_flush_pci_hbw_writes(struct hl_fpriv *hpriv)
|
||||
{
|
||||
struct hl_device *hdev = hpriv->hdev;
|
||||
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
||||
|
||||
if (!prop->hbw_flush_reg) {
|
||||
dev_dbg(hdev->dev, "HBW flush is not supported\n");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
RREG32(prop->hbw_flush_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
|
||||
{
|
||||
union hl_cs_args *args = data;
|
||||
|
|
@ -2478,6 +2532,9 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
rc = cs_ioctl_engine_cores(hpriv, args->in.engine_cores,
|
||||
args->in.num_engine_cores, args->in.core_command);
|
||||
break;
|
||||
case CS_TYPE_FLUSH_PCI_HBW_WRITES:
|
||||
rc = cs_ioctl_flush_pci_hbw_writes(hpriv);
|
||||
break;
|
||||
default:
|
||||
rc = cs_ioctl_default(hpriv, chunks, num_chunks, &cs_seq,
|
||||
args->in.cs_flags,
|
||||
|
|
@ -2569,7 +2626,9 @@ report_results:
|
|||
*status = CS_WAIT_STATUS_BUSY;
|
||||
}
|
||||
|
||||
if (error == -ETIMEDOUT || error == -EIO)
|
||||
if (completion_rc == -ERESTARTSYS)
|
||||
rc = completion_rc;
|
||||
else if (error == -ETIMEDOUT || error == -EIO)
|
||||
rc = error;
|
||||
|
||||
return rc;
|
||||
|
|
@ -2699,7 +2758,8 @@ static int hl_cs_poll_fences(struct multi_cs_data *mcs_data, struct multi_cs_com
|
|||
break;
|
||||
default:
|
||||
dev_err(hdev->dev, "Invalid fence status\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -2828,6 +2888,9 @@ static int hl_wait_multi_cs_completion(struct multi_cs_data *mcs_data,
|
|||
if (completion_rc > 0)
|
||||
mcs_data->timestamp = mcs_compl->timestamp;
|
||||
|
||||
if (completion_rc == -ERESTARTSYS)
|
||||
return completion_rc;
|
||||
|
||||
mcs_data->wait_status = completion_rc;
|
||||
|
||||
return 0;
|
||||
|
|
@ -2870,7 +2933,13 @@ static int hl_multi_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
u32 size_to_copy;
|
||||
u64 *cs_seq_arr;
|
||||
u8 seq_arr_len;
|
||||
int rc;
|
||||
int rc, i;
|
||||
|
||||
for (i = 0 ; i < sizeof(args->in.pad) ; i++)
|
||||
if (args->in.pad[i]) {
|
||||
dev_dbg(hdev->dev, "Padding bytes must be 0\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!hdev->supports_wait_for_multi_cs) {
|
||||
dev_err(hdev->dev, "Wait for multi CS is not supported\n");
|
||||
|
|
@ -2973,15 +3042,15 @@ put_ctx:
|
|||
free_seq_arr:
|
||||
kfree(cs_seq_arr);
|
||||
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (mcs_data.wait_status == -ERESTARTSYS) {
|
||||
if (rc == -ERESTARTSYS) {
|
||||
dev_err_ratelimited(hdev->dev,
|
||||
"user process got signal while waiting for Multi-CS\n");
|
||||
return -EINTR;
|
||||
rc = -EINTR;
|
||||
}
|
||||
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* update output args */
|
||||
memset(args, 0, sizeof(*args));
|
||||
|
||||
|
|
@ -3119,19 +3188,18 @@ start_over:
|
|||
goto start_over;
|
||||
}
|
||||
} else {
|
||||
/* Fill up the new registration node info */
|
||||
requested_offset_record->ts_reg_info.buf = buf;
|
||||
requested_offset_record->ts_reg_info.cq_cb = cq_cb;
|
||||
requested_offset_record->ts_reg_info.timestamp_kernel_addr =
|
||||
(u64 *) ts_buff->user_buff_address + ts_offset;
|
||||
requested_offset_record->cq_kernel_addr =
|
||||
(u64 *) cq_cb->kernel_address + cq_offset;
|
||||
requested_offset_record->cq_target_value = target_value;
|
||||
|
||||
spin_unlock_irqrestore(wait_list_lock, flags);
|
||||
}
|
||||
|
||||
/* Fill up the new registration node info */
|
||||
requested_offset_record->ts_reg_info.in_use = 1;
|
||||
requested_offset_record->ts_reg_info.buf = buf;
|
||||
requested_offset_record->ts_reg_info.cq_cb = cq_cb;
|
||||
requested_offset_record->ts_reg_info.timestamp_kernel_addr =
|
||||
(u64 *) ts_buff->user_buff_address + ts_offset;
|
||||
requested_offset_record->cq_kernel_addr =
|
||||
(u64 *) cq_cb->kernel_address + cq_offset;
|
||||
requested_offset_record->cq_target_value = target_value;
|
||||
|
||||
*pend = requested_offset_record;
|
||||
|
||||
dev_dbg(buf->mmg->dev, "Found available node in TS kernel CB %p\n",
|
||||
|
|
@ -3179,7 +3247,7 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx,
|
|||
goto put_cq_cb;
|
||||
}
|
||||
|
||||
/* Find first available record */
|
||||
/* get ts buffer record */
|
||||
rc = ts_buff_get_kernel_ts_record(buf, cq_cb, ts_offset,
|
||||
cq_counters_offset, target_value,
|
||||
&interrupt->wait_list_lock, &pend);
|
||||
|
|
@ -3227,7 +3295,19 @@ static int _hl_interrupt_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx,
|
|||
* Note that we cannot have sorted list by target value,
|
||||
* in order to shorten the list pass loop, since
|
||||
* same list could have nodes for different cq counter handle.
|
||||
* Note:
|
||||
* Mark ts buff offset as in use here in the spinlock protection area
|
||||
* to avoid getting in the re-use section in ts_buff_get_kernel_ts_record
|
||||
* before adding the node to the list. this scenario might happen when
|
||||
* multiple threads are racing on same offset and one thread could
|
||||
* set the ts buff in ts_buff_get_kernel_ts_record then the other thread
|
||||
* takes over and get to ts_buff_get_kernel_ts_record and then we will try
|
||||
* to re-use the same ts buff offset, and will try to delete a non existing
|
||||
* node from the list.
|
||||
*/
|
||||
if (register_ts_record)
|
||||
pend->ts_reg_info.in_use = 1;
|
||||
|
||||
list_add_tail(&pend->wait_list_node, &interrupt->wait_list_head);
|
||||
spin_unlock_irqrestore(&interrupt->wait_list_lock, flags);
|
||||
|
||||
|
|
@ -3489,14 +3569,15 @@ static int hl_interrupt_wait_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
|
||||
int hl_wait_ioctl(struct hl_fpriv *hpriv, void *data)
|
||||
{
|
||||
struct hl_device *hdev = hpriv->hdev;
|
||||
union hl_wait_cs_args *args = data;
|
||||
u32 flags = args->in.flags;
|
||||
int rc;
|
||||
|
||||
/* If the device is not operational, no point in waiting for any command submission or
|
||||
* user interrupt
|
||||
/* If the device is not operational, or if an error has happened and user should release the
|
||||
* device, there is no point in waiting for any command submission or user interrupt.
|
||||
*/
|
||||
if (!hl_device_operational(hpriv->hdev, NULL))
|
||||
if (!hl_device_operational(hpriv->hdev, NULL) || hdev->reset_info.watchdog_active)
|
||||
return -EBUSY;
|
||||
|
||||
if (flags & HL_WAIT_CS_FLAGS_INTERRUPT)
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
#define pr_fmt(fmt) "habanalabs: " fmt
|
||||
|
||||
#include <uapi/misc/habanalabs.h>
|
||||
#include <uapi/drm/habanalabs_accel.h>
|
||||
#include "habanalabs.h"
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
|
@ -428,8 +428,10 @@ static void hpriv_release(struct kref *ref)
|
|||
*/
|
||||
reset_device = hdev->reset_upon_device_release || hdev->reset_info.watchdog_active;
|
||||
|
||||
/* Unless device is reset in any case, check idle status and reset if device is not idle */
|
||||
if (!reset_device && hdev->pdev && !hdev->pldm)
|
||||
/* Check the device idle status and reset if not idle.
|
||||
* Skip it if already in reset, or if device is going to be reset in any case.
|
||||
*/
|
||||
if (!hdev->reset_info.in_reset && !reset_device && hdev->pdev && !hdev->pldm)
|
||||
device_is_idle = hdev->asic_funcs->is_device_idle(hdev, idle_mask,
|
||||
HL_BUSY_ENGINES_MASK_EXT_SIZE, NULL);
|
||||
if (!device_is_idle) {
|
||||
|
|
@ -511,11 +513,6 @@ static int hl_device_release(struct inode *inode, struct file *filp)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Each pending user interrupt holds the user's context, hence we
|
||||
* must release them all before calling hl_ctx_mgr_fini().
|
||||
*/
|
||||
hl_release_pending_user_interrupts(hpriv->hdev);
|
||||
|
||||
hl_ctx_mgr_fini(hdev, &hpriv->ctx_mgr);
|
||||
hl_mem_mgr_fini(&hpriv->mem_mgr);
|
||||
|
||||
|
|
@ -1428,8 +1425,8 @@ static void handle_reset_trigger(struct hl_device *hdev, u32 flags)
|
|||
int hl_device_reset(struct hl_device *hdev, u32 flags)
|
||||
{
|
||||
bool hard_reset, from_hard_reset_thread, fw_reset, hard_instead_soft = false,
|
||||
reset_upon_device_release = false, schedule_hard_reset = false, delay_reset,
|
||||
from_dev_release, from_watchdog_thread;
|
||||
reset_upon_device_release = false, schedule_hard_reset = false,
|
||||
delay_reset, from_dev_release, from_watchdog_thread;
|
||||
u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0};
|
||||
struct hl_ctx *ctx;
|
||||
int i, rc;
|
||||
|
|
@ -1446,12 +1443,17 @@ int hl_device_reset(struct hl_device *hdev, u32 flags)
|
|||
delay_reset = !!(flags & HL_DRV_RESET_DELAY);
|
||||
from_watchdog_thread = !!(flags & HL_DRV_RESET_FROM_WD_THR);
|
||||
|
||||
if (!hard_reset && (hl_device_status(hdev) == HL_DEVICE_STATUS_MALFUNCTION)) {
|
||||
dev_dbg(hdev->dev, "soft-reset isn't supported on a malfunctioning device\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!hard_reset && !hdev->asic_prop.supports_compute_reset) {
|
||||
hard_instead_soft = true;
|
||||
hard_reset = true;
|
||||
}
|
||||
|
||||
if (hdev->reset_upon_device_release && (flags & HL_DRV_RESET_DEV_RELEASE)) {
|
||||
if (hdev->reset_upon_device_release && from_dev_release) {
|
||||
if (hard_reset) {
|
||||
dev_crit(hdev->dev,
|
||||
"Aborting reset because hard-reset is mutually exclusive with reset-on-device-release\n");
|
||||
|
|
@ -1512,6 +1514,7 @@ do_reset:
|
|||
&hdev->device_release_watchdog_work.reset_work);
|
||||
|
||||
if (from_dev_release) {
|
||||
hdev->reset_info.in_compute_reset = 0;
|
||||
flags |= HL_DRV_RESET_HARD;
|
||||
flags &= ~HL_DRV_RESET_DEV_RELEASE;
|
||||
hard_reset = true;
|
||||
|
|
@ -1566,7 +1569,8 @@ kill_processes:
|
|||
if (rc == -EBUSY) {
|
||||
if (hdev->device_fini_pending) {
|
||||
dev_crit(hdev->dev,
|
||||
"Failed to kill all open processes, stopping hard reset\n");
|
||||
"%s Failed to kill all open processes, stopping hard reset\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
|
|
@ -1576,7 +1580,8 @@ kill_processes:
|
|||
|
||||
if (rc) {
|
||||
dev_crit(hdev->dev,
|
||||
"Failed to kill all open processes, stopping hard reset\n");
|
||||
"%s Failed to kill all open processes, stopping hard reset\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
|
|
@ -1627,14 +1632,16 @@ kill_processes:
|
|||
* ensure driver puts the driver in a unusable state
|
||||
*/
|
||||
dev_crit(hdev->dev,
|
||||
"Consecutive FW fatal errors received, stopping hard reset\n");
|
||||
"%s Consecutive FW fatal errors received, stopping hard reset\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
rc = -EIO;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
if (hdev->kernel_ctx) {
|
||||
dev_crit(hdev->dev,
|
||||
"kernel ctx was alive during hard reset, something is terribly wrong\n");
|
||||
"%s kernel ctx was alive during hard reset, something is terribly wrong\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
rc = -EBUSY;
|
||||
goto out_err;
|
||||
}
|
||||
|
|
@ -1732,7 +1739,7 @@ kill_processes:
|
|||
rc = hdev->asic_funcs->scrub_device_mem(hdev);
|
||||
if (rc) {
|
||||
dev_err(hdev->dev, "scrub mem failed from device reset (%d)\n", rc);
|
||||
return rc;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
spin_lock(&hdev->reset_info.lock);
|
||||
|
|
@ -1752,9 +1759,13 @@ kill_processes:
|
|||
hdev->reset_info.needs_reset = false;
|
||||
|
||||
if (hard_reset)
|
||||
dev_info(hdev->dev, "Successfully finished resetting the device\n");
|
||||
dev_info(hdev->dev,
|
||||
"Successfully finished resetting the %s device\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
else
|
||||
dev_dbg(hdev->dev, "Successfully finished resetting the device\n");
|
||||
dev_dbg(hdev->dev,
|
||||
"Successfully finished resetting the %s device\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
|
||||
if (hard_reset) {
|
||||
hdev->reset_info.hard_reset_cnt++;
|
||||
|
|
@ -1789,7 +1800,9 @@ out_err:
|
|||
hdev->reset_info.in_compute_reset = 0;
|
||||
|
||||
if (hard_reset) {
|
||||
dev_err(hdev->dev, "Failed to reset! Device is NOT usable\n");
|
||||
dev_err(hdev->dev,
|
||||
"%s Failed to reset! Device is NOT usable\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
hdev->reset_info.hard_reset_cnt++;
|
||||
} else if (reset_upon_device_release) {
|
||||
spin_unlock(&hdev->reset_info.lock);
|
||||
|
|
@ -1870,6 +1883,8 @@ out:
|
|||
|
||||
hl_ctx_put(ctx);
|
||||
|
||||
hl_abort_waitings_for_completion(hdev);
|
||||
|
||||
return 0;
|
||||
|
||||
device_reset:
|
||||
|
|
@ -2186,7 +2201,8 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass)
|
|||
}
|
||||
|
||||
dev_notice(hdev->dev,
|
||||
"Successfully added device to habanalabs driver\n");
|
||||
"Successfully added device %s to habanalabs driver\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
|
||||
hdev->init_done = true;
|
||||
|
||||
|
|
@ -2235,11 +2251,11 @@ out_disabled:
|
|||
device_cdev_sysfs_add(hdev);
|
||||
if (hdev->pdev)
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"Failed to initialize hl%d. Device is NOT usable !\n",
|
||||
hdev->cdev_idx);
|
||||
"Failed to initialize hl%d. Device %s is NOT usable !\n",
|
||||
hdev->cdev_idx, dev_name(&(hdev)->pdev->dev));
|
||||
else
|
||||
pr_err("Failed to initialize hl%d. Device is NOT usable !\n",
|
||||
hdev->cdev_idx);
|
||||
pr_err("Failed to initialize hl%d. Device %s is NOT usable !\n",
|
||||
hdev->cdev_idx, dev_name(&(hdev)->pdev->dev));
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
|
@ -2295,7 +2311,8 @@ void hl_device_fini(struct hl_device *hdev)
|
|||
|
||||
if (ktime_compare(ktime_get(), timeout) > 0) {
|
||||
dev_crit(hdev->dev,
|
||||
"Failed to remove device because reset function did not finish\n");
|
||||
"%s Failed to remove device because reset function did not finish\n",
|
||||
dev_name(&(hdev)->pdev->dev));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -2363,7 +2380,7 @@ void hl_device_fini(struct hl_device *hdev)
|
|||
|
||||
hl_mmu_fini(hdev);
|
||||
|
||||
vfree(hdev->captured_err_info.pgf_info.user_mappings);
|
||||
vfree(hdev->captured_err_info.page_fault_info.user_mappings);
|
||||
|
||||
hl_eq_fini(hdev, &hdev->event_queue);
|
||||
|
||||
|
|
@ -2402,7 +2419,12 @@ void hl_device_fini(struct hl_device *hdev)
|
|||
*/
|
||||
inline u32 hl_rreg(struct hl_device *hdev, u32 reg)
|
||||
{
|
||||
return readl(hdev->rmmio + reg);
|
||||
u32 val = readl(hdev->rmmio + reg);
|
||||
|
||||
if (unlikely(trace_habanalabs_rreg32_enabled()))
|
||||
trace_habanalabs_rreg32(hdev->dev, reg, val);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -2417,12 +2439,17 @@ inline u32 hl_rreg(struct hl_device *hdev, u32 reg)
|
|||
*/
|
||||
inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val)
|
||||
{
|
||||
if (unlikely(trace_habanalabs_wreg32_enabled()))
|
||||
trace_habanalabs_wreg32(hdev->dev, reg, val);
|
||||
|
||||
writel(val, hdev->rmmio + reg);
|
||||
}
|
||||
|
||||
void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
|
||||
u8 flags)
|
||||
{
|
||||
struct razwi_info *razwi_info = &hdev->captured_err_info.razwi_info;
|
||||
|
||||
if (num_of_engines > HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR) {
|
||||
dev_err(hdev->dev,
|
||||
"Number of possible razwi initiators (%u) exceeded limit (%u)\n",
|
||||
|
|
@ -2431,15 +2458,17 @@ void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_
|
|||
}
|
||||
|
||||
/* In case it's the first razwi since the device was opened, capture its parameters */
|
||||
if (atomic_cmpxchg(&hdev->captured_err_info.razwi_info_recorded, 0, 1))
|
||||
if (atomic_cmpxchg(&hdev->captured_err_info.razwi_info.razwi_detected, 0, 1))
|
||||
return;
|
||||
|
||||
hdev->captured_err_info.razwi.timestamp = ktime_to_ns(ktime_get());
|
||||
hdev->captured_err_info.razwi.addr = addr;
|
||||
hdev->captured_err_info.razwi.num_of_possible_engines = num_of_engines;
|
||||
memcpy(&hdev->captured_err_info.razwi.engine_id[0], &engine_id[0],
|
||||
razwi_info->razwi.timestamp = ktime_to_ns(ktime_get());
|
||||
razwi_info->razwi.addr = addr;
|
||||
razwi_info->razwi.num_of_possible_engines = num_of_engines;
|
||||
memcpy(&razwi_info->razwi.engine_id[0], &engine_id[0],
|
||||
num_of_engines * sizeof(u16));
|
||||
hdev->captured_err_info.razwi.flags = flags;
|
||||
razwi_info->razwi.flags = flags;
|
||||
|
||||
razwi_info->razwi_info_available = true;
|
||||
}
|
||||
|
||||
void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
|
||||
|
|
@ -2453,7 +2482,7 @@ void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_o
|
|||
|
||||
static void hl_capture_user_mappings(struct hl_device *hdev, bool is_pmmu)
|
||||
{
|
||||
struct page_fault_info *pgf_info = &hdev->captured_err_info.pgf_info;
|
||||
struct page_fault_info *pgf_info = &hdev->captured_err_info.page_fault_info;
|
||||
struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
|
||||
struct hl_vm_hash_node *hnode;
|
||||
struct hl_userptr *userptr;
|
||||
|
|
@ -2515,14 +2544,18 @@ finish:
|
|||
|
||||
void hl_capture_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu)
|
||||
{
|
||||
struct page_fault_info *pgf_info = &hdev->captured_err_info.page_fault_info;
|
||||
|
||||
/* Capture only the first page fault */
|
||||
if (atomic_cmpxchg(&hdev->captured_err_info.pgf_info_recorded, 0, 1))
|
||||
if (atomic_cmpxchg(&pgf_info->page_fault_detected, 0, 1))
|
||||
return;
|
||||
|
||||
hdev->captured_err_info.pgf_info.pgf.timestamp = ktime_to_ns(ktime_get());
|
||||
hdev->captured_err_info.pgf_info.pgf.addr = addr;
|
||||
hdev->captured_err_info.pgf_info.pgf.engine_id = eng_id;
|
||||
pgf_info->page_fault.timestamp = ktime_to_ns(ktime_get());
|
||||
pgf_info->page_fault.addr = addr;
|
||||
pgf_info->page_fault.engine_id = eng_id;
|
||||
hl_capture_user_mappings(hdev, is_pmmu);
|
||||
|
||||
pgf_info->page_fault_info_available = true;
|
||||
}
|
||||
|
||||
void hl_handle_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu,
|
||||
|
|
@ -14,8 +14,32 @@
|
|||
#include <linux/ctype.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include <trace/events/habanalabs.h>
|
||||
|
||||
#define FW_FILE_MAX_SIZE 0x1400000 /* maximum size of 20MB */
|
||||
|
||||
static char *comms_cmd_str_arr[COMMS_INVLD_LAST] = {
|
||||
[COMMS_NOOP] = __stringify(COMMS_NOOP),
|
||||
[COMMS_CLR_STS] = __stringify(COMMS_CLR_STS),
|
||||
[COMMS_RST_STATE] = __stringify(COMMS_RST_STATE),
|
||||
[COMMS_PREP_DESC] = __stringify(COMMS_PREP_DESC),
|
||||
[COMMS_DATA_RDY] = __stringify(COMMS_DATA_RDY),
|
||||
[COMMS_EXEC] = __stringify(COMMS_EXEC),
|
||||
[COMMS_RST_DEV] = __stringify(COMMS_RST_DEV),
|
||||
[COMMS_GOTO_WFE] = __stringify(COMMS_GOTO_WFE),
|
||||
[COMMS_SKIP_BMC] = __stringify(COMMS_SKIP_BMC),
|
||||
[COMMS_PREP_DESC_ELBI] = __stringify(COMMS_PREP_DESC_ELBI),
|
||||
};
|
||||
|
||||
static char *comms_sts_str_arr[COMMS_STS_INVLD_LAST] = {
|
||||
[COMMS_STS_NOOP] = __stringify(COMMS_STS_NOOP),
|
||||
[COMMS_STS_ACK] = __stringify(COMMS_STS_ACK),
|
||||
[COMMS_STS_OK] = __stringify(COMMS_STS_OK),
|
||||
[COMMS_STS_ERR] = __stringify(COMMS_STS_ERR),
|
||||
[COMMS_STS_VALID_ERR] = __stringify(COMMS_STS_VALID_ERR),
|
||||
[COMMS_STS_TIMEOUT_ERR] = __stringify(COMMS_STS_TIMEOUT_ERR),
|
||||
};
|
||||
|
||||
static char *extract_fw_ver_from_str(const char *fw_str)
|
||||
{
|
||||
char *str, *fw_ver, *whitespace;
|
||||
|
|
@ -311,7 +335,7 @@ int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg,
|
|||
dev_dbg(hdev->dev, "Device CPU packet timeout (0x%x) due to FW reset\n",
|
||||
tmp);
|
||||
else
|
||||
dev_err(hdev->dev, "Device CPU packet timeout (0x%x)\n", tmp);
|
||||
dev_err(hdev->dev, "Device CPU packet timeout (status = 0x%x)\n", tmp);
|
||||
hdev->device_cpu_disabled = true;
|
||||
goto out;
|
||||
}
|
||||
|
|
@ -1322,13 +1346,12 @@ static void detect_cpu_boot_status(struct hl_device *hdev, u32 status)
|
|||
break;
|
||||
default:
|
||||
dev_err(hdev->dev,
|
||||
"Device boot progress - Invalid status code %d\n",
|
||||
status);
|
||||
"Device boot progress - Invalid or unexpected status code %d\n", status);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int hl_fw_wait_preboot_ready(struct hl_device *hdev)
|
||||
int hl_fw_wait_preboot_ready(struct hl_device *hdev)
|
||||
{
|
||||
struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
|
||||
u32 status;
|
||||
|
|
@ -1353,8 +1376,8 @@ static int hl_fw_wait_preboot_ready(struct hl_device *hdev)
|
|||
pre_fw_load->wait_for_preboot_timeout);
|
||||
|
||||
if (rc) {
|
||||
dev_err(hdev->dev, "CPU boot ready status timeout\n");
|
||||
detect_cpu_boot_status(hdev, status);
|
||||
dev_err(hdev->dev, "CPU boot ready timeout (status = %d)\n", status);
|
||||
|
||||
/* If we read all FF, then something is totally wrong, no point
|
||||
* of reading specific errors
|
||||
|
|
@ -1634,6 +1657,7 @@ static void hl_fw_dynamic_send_cmd(struct hl_device *hdev,
|
|||
val = FIELD_PREP(COMMS_COMMAND_CMD_MASK, cmd);
|
||||
val |= FIELD_PREP(COMMS_COMMAND_SIZE_MASK, size);
|
||||
|
||||
trace_habanalabs_comms_send_cmd(hdev->dev, comms_cmd_str_arr[cmd]);
|
||||
WREG32(le32_to_cpu(dyn_regs->kmd_msg_to_cpu), val);
|
||||
}
|
||||
|
||||
|
|
@ -1691,6 +1715,8 @@ static int hl_fw_dynamic_wait_for_status(struct hl_device *hdev,
|
|||
|
||||
dyn_regs = &fw_loader->dynamic_loader.comm_desc.cpu_dyn_regs;
|
||||
|
||||
trace_habanalabs_comms_wait_status(hdev->dev, comms_sts_str_arr[expected_status]);
|
||||
|
||||
/* Wait for expected status */
|
||||
rc = hl_poll_timeout(
|
||||
hdev,
|
||||
|
|
@ -1706,6 +1732,8 @@ static int hl_fw_dynamic_wait_for_status(struct hl_device *hdev,
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
trace_habanalabs_comms_wait_status_done(hdev->dev, comms_sts_str_arr[expected_status]);
|
||||
|
||||
/*
|
||||
* skip storing FW response for NOOP to preserve the actual desired
|
||||
* FW status
|
||||
|
|
@ -1778,6 +1806,8 @@ int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev,
|
|||
{
|
||||
int rc;
|
||||
|
||||
trace_habanalabs_comms_protocol_cmd(hdev->dev, comms_cmd_str_arr[cmd]);
|
||||
|
||||
/* first send clear command to clean former commands */
|
||||
rc = hl_fw_dynamic_send_clear_cmd(hdev, fw_loader);
|
||||
if (rc)
|
||||
|
|
@ -1884,7 +1914,7 @@ static int hl_fw_dynamic_validate_memory_bound(struct hl_device *hdev,
|
|||
*
|
||||
* @hdev: pointer to the habanalabs device structure
|
||||
* @fw_loader: managing structure for loading device's FW
|
||||
* @fw_desc: the descriptor form FW
|
||||
* @fw_desc: the descriptor from FW
|
||||
*
|
||||
* @return 0 on success, otherwise non-zero error code
|
||||
*/
|
||||
|
|
@ -1901,11 +1931,11 @@ static int hl_fw_dynamic_validate_descriptor(struct hl_device *hdev,
|
|||
int rc;
|
||||
|
||||
if (le32_to_cpu(fw_desc->header.magic) != HL_COMMS_DESC_MAGIC)
|
||||
dev_warn(hdev->dev, "Invalid magic for dynamic FW descriptor (%x)\n",
|
||||
dev_dbg(hdev->dev, "Invalid magic for dynamic FW descriptor (%x)\n",
|
||||
fw_desc->header.magic);
|
||||
|
||||
if (fw_desc->header.version != HL_COMMS_DESC_VER)
|
||||
dev_warn(hdev->dev, "Invalid version for dynamic FW descriptor (%x)\n",
|
||||
dev_dbg(hdev->dev, "Invalid version for dynamic FW descriptor (%x)\n",
|
||||
fw_desc->header.version);
|
||||
|
||||
/*
|
||||
|
|
@ -1976,6 +2006,43 @@ static int hl_fw_dynamic_validate_response(struct hl_device *hdev,
|
|||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* hl_fw_dynamic_read_descriptor_msg - read and show the ascii msg that sent by fw
|
||||
*
|
||||
* @hdev: pointer to the habanalabs device structure
|
||||
* @fw_desc: the descriptor from FW
|
||||
*/
|
||||
static void hl_fw_dynamic_read_descriptor_msg(struct hl_device *hdev,
|
||||
struct lkd_fw_comms_desc *fw_desc)
|
||||
{
|
||||
int i;
|
||||
char *msg;
|
||||
|
||||
for (i = 0 ; i < LKD_FW_ASCII_MSG_MAX ; i++) {
|
||||
if (!fw_desc->ascii_msg[i].valid)
|
||||
return;
|
||||
|
||||
/* force NULL termination */
|
||||
msg = fw_desc->ascii_msg[i].msg;
|
||||
msg[LKD_FW_ASCII_MSG_MAX_LEN - 1] = '\0';
|
||||
|
||||
switch (fw_desc->ascii_msg[i].msg_lvl) {
|
||||
case LKD_FW_ASCII_MSG_ERR:
|
||||
dev_err(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
|
||||
break;
|
||||
case LKD_FW_ASCII_MSG_WRN:
|
||||
dev_warn(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
|
||||
break;
|
||||
case LKD_FW_ASCII_MSG_INF:
|
||||
dev_info(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
|
||||
break;
|
||||
default:
|
||||
dev_dbg(hdev->dev, "fw: %s", fw_desc->ascii_msg[i].msg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* hl_fw_dynamic_read_and_validate_descriptor - read and validate FW descriptor
|
||||
*
|
||||
|
|
@ -1988,9 +2055,10 @@ static int hl_fw_dynamic_read_and_validate_descriptor(struct hl_device *hdev,
|
|||
struct fw_load_mgr *fw_loader)
|
||||
{
|
||||
struct lkd_fw_comms_desc *fw_desc;
|
||||
void __iomem *src, *temp_fw_desc;
|
||||
struct pci_mem_region *region;
|
||||
struct fw_response *response;
|
||||
void *temp_fw_desc;
|
||||
void __iomem *src;
|
||||
u16 fw_data_size;
|
||||
enum pci_region region_id;
|
||||
int rc;
|
||||
|
|
@ -2039,6 +2107,10 @@ static int hl_fw_dynamic_read_and_validate_descriptor(struct hl_device *hdev,
|
|||
|
||||
rc = hl_fw_dynamic_validate_descriptor(hdev, fw_loader,
|
||||
(struct lkd_fw_comms_desc *) temp_fw_desc);
|
||||
|
||||
if (!rc)
|
||||
hl_fw_dynamic_read_descriptor_msg(hdev, temp_fw_desc);
|
||||
|
||||
vfree(temp_fw_desc);
|
||||
|
||||
return rc;
|
||||
|
|
@ -2354,7 +2426,7 @@ static int hl_fw_dynamic_wait_for_boot_fit_active(struct hl_device *hdev,
|
|||
hdev->fw_poll_interval_usec,
|
||||
dyn_loader->wait_for_bl_timeout);
|
||||
if (rc) {
|
||||
dev_err(hdev->dev, "failed to wait for boot\n");
|
||||
dev_err(hdev->dev, "failed to wait for boot (status = %d)\n", status);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
@ -2381,7 +2453,7 @@ static int hl_fw_dynamic_wait_for_linux_active(struct hl_device *hdev,
|
|||
hdev->fw_poll_interval_usec,
|
||||
fw_loader->cpu_timeout);
|
||||
if (rc) {
|
||||
dev_err(hdev->dev, "failed to wait for Linux\n");
|
||||
dev_err(hdev->dev, "failed to wait for Linux (status = %d)\n", status);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
@ -2459,51 +2531,54 @@ static void hl_fw_linux_update_state(struct hl_device *hdev,
|
|||
static int hl_fw_dynamic_send_msg(struct hl_device *hdev,
|
||||
struct fw_load_mgr *fw_loader, u8 msg_type, void *data)
|
||||
{
|
||||
struct lkd_msg_comms msg;
|
||||
struct lkd_msg_comms *msg;
|
||||
int rc;
|
||||
|
||||
memset(&msg, 0, sizeof(msg));
|
||||
msg = kzalloc(sizeof(*msg), GFP_KERNEL);
|
||||
if (!msg)
|
||||
return -ENOMEM;
|
||||
|
||||
/* create message to be sent */
|
||||
msg.header.type = msg_type;
|
||||
msg.header.size = cpu_to_le16(sizeof(struct comms_msg_header));
|
||||
msg.header.magic = cpu_to_le32(HL_COMMS_MSG_MAGIC);
|
||||
msg->header.type = msg_type;
|
||||
msg->header.size = cpu_to_le16(sizeof(struct comms_msg_header));
|
||||
msg->header.magic = cpu_to_le32(HL_COMMS_MSG_MAGIC);
|
||||
|
||||
switch (msg_type) {
|
||||
case HL_COMMS_RESET_CAUSE_TYPE:
|
||||
msg.reset_cause = *(__u8 *) data;
|
||||
msg->reset_cause = *(__u8 *) data;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(hdev->dev,
|
||||
"Send COMMS message - invalid message type %u\n",
|
||||
msg_type);
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
rc = hl_fw_dynamic_request_descriptor(hdev, fw_loader,
|
||||
sizeof(struct lkd_msg_comms));
|
||||
if (rc)
|
||||
return rc;
|
||||
goto out;
|
||||
|
||||
/* copy message to space allocated by FW */
|
||||
rc = hl_fw_dynamic_copy_msg(hdev, &msg, fw_loader);
|
||||
rc = hl_fw_dynamic_copy_msg(hdev, msg, fw_loader);
|
||||
if (rc)
|
||||
return rc;
|
||||
goto out;
|
||||
|
||||
rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_DATA_RDY,
|
||||
0, true,
|
||||
fw_loader->cpu_timeout);
|
||||
if (rc)
|
||||
return rc;
|
||||
goto out;
|
||||
|
||||
rc = hl_fw_dynamic_send_protocol_cmd(hdev, fw_loader, COMMS_EXEC,
|
||||
0, true,
|
||||
fw_loader->cpu_timeout);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return 0;
|
||||
out:
|
||||
kfree(msg);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2560,13 +2635,43 @@ static int hl_fw_dynamic_init_cpu(struct hl_device *hdev,
|
|||
}
|
||||
|
||||
if (!(hdev->fw_components & FW_TYPE_BOOT_CPU)) {
|
||||
struct lkd_fw_binning_info *binning_info;
|
||||
|
||||
rc = hl_fw_dynamic_request_descriptor(hdev, fw_loader, 0);
|
||||
if (rc)
|
||||
goto protocol_err;
|
||||
|
||||
/* read preboot version */
|
||||
return hl_fw_dynamic_read_device_fw_version(hdev, FW_COMP_PREBOOT,
|
||||
rc = hl_fw_dynamic_read_device_fw_version(hdev, FW_COMP_PREBOOT,
|
||||
fw_loader->dynamic_loader.comm_desc.cur_fw_ver);
|
||||
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* read binning info from preboot */
|
||||
if (hdev->support_preboot_binning) {
|
||||
binning_info = &fw_loader->dynamic_loader.comm_desc.binning_info;
|
||||
hdev->tpc_binning = le64_to_cpu(binning_info->tpc_mask_l);
|
||||
hdev->dram_binning = le32_to_cpu(binning_info->dram_mask);
|
||||
hdev->edma_binning = le32_to_cpu(binning_info->edma_mask);
|
||||
hdev->decoder_binning = le32_to_cpu(binning_info->dec_mask);
|
||||
hdev->rotator_binning = le32_to_cpu(binning_info->rot_mask);
|
||||
|
||||
rc = hdev->asic_funcs->set_dram_properties(hdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = hdev->asic_funcs->set_binning_masks(hdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
dev_dbg(hdev->dev,
|
||||
"Read binning masks: tpc: 0x%llx, dram: 0x%llx, edma: 0x%x, dec: 0x%x, rot:0x%x\n",
|
||||
hdev->tpc_binning, hdev->dram_binning, hdev->edma_binning,
|
||||
hdev->decoder_binning, hdev->rotator_binning);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* load boot fit to FW */
|
||||
|
|
@ -2687,7 +2792,7 @@ static int hl_fw_static_init_cpu(struct hl_device *hdev,
|
|||
|
||||
if (rc) {
|
||||
dev_dbg(hdev->dev,
|
||||
"No boot fit request received, resuming boot\n");
|
||||
"No boot fit request received (status = %d), resuming boot\n", status);
|
||||
} else {
|
||||
rc = hdev->asic_funcs->load_boot_fit_to_device(hdev);
|
||||
if (rc)
|
||||
|
|
@ -2710,7 +2815,7 @@ static int hl_fw_static_init_cpu(struct hl_device *hdev,
|
|||
|
||||
if (rc) {
|
||||
dev_err(hdev->dev,
|
||||
"Timeout waiting for boot fit load ack\n");
|
||||
"Timeout waiting for boot fit load ack (status = %d)\n", status);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
@ -2788,7 +2893,7 @@ static int hl_fw_static_init_cpu(struct hl_device *hdev,
|
|||
|
||||
if (rc) {
|
||||
dev_err(hdev->dev,
|
||||
"Failed to get ACK on skipping BMC, %d\n",
|
||||
"Failed to get ACK on skipping BMC (status = %d)\n",
|
||||
status);
|
||||
WREG32(msg_to_cpu_reg, KMD_MSG_NA);
|
||||
rc = -EIO;
|
||||
|
|
@ -2815,7 +2920,7 @@ static int hl_fw_static_init_cpu(struct hl_device *hdev,
|
|||
"Device reports FIT image is corrupted\n");
|
||||
else
|
||||
dev_err(hdev->dev,
|
||||
"Failed to load firmware to device, %d\n",
|
||||
"Failed to load firmware to device (status = %d)\n",
|
||||
status);
|
||||
|
||||
rc = -EIO;
|
||||
|
|
@ -3043,3 +3148,27 @@ int hl_fw_get_sec_attest_info(struct hl_device *hdev, struct cpucp_sec_attest_in
|
|||
sizeof(struct cpucp_sec_attest_info), nonce,
|
||||
HL_CPUCP_SEC_ATTEST_INFO_TINEOUT_USEC);
|
||||
}
|
||||
|
||||
int hl_fw_send_generic_request(struct hl_device *hdev, enum hl_passthrough_type sub_opcode,
|
||||
dma_addr_t buff, u32 *size)
|
||||
{
|
||||
struct cpucp_packet pkt = {0};
|
||||
u64 result;
|
||||
int rc = 0;
|
||||
|
||||
pkt.ctl = cpu_to_le32(CPUCP_PACKET_GENERIC_PASSTHROUGH << CPUCP_PKT_CTL_OPCODE_SHIFT);
|
||||
pkt.addr = cpu_to_le64(buff);
|
||||
pkt.data_max_size = cpu_to_le32(*size);
|
||||
pkt.pkt_subidx = cpu_to_le32(sub_opcode);
|
||||
|
||||
rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *)&pkt, sizeof(pkt),
|
||||
HL_CPUCP_INFO_TIMEOUT_USEC, &result);
|
||||
if (rc)
|
||||
dev_err(hdev->dev, "failed to send CPUCP data of generic fw pkt\n");
|
||||
else
|
||||
dev_dbg(hdev->dev, "generic pkt was successful, result: 0x%llx\n", result);
|
||||
|
||||
*size = (u32)result;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
#include "../include/common/cpucp_if.h"
|
||||
#include "../include/common/qman_if.h"
|
||||
#include "../include/hw_ip/mmu/mmu_general.h"
|
||||
#include <uapi/misc/habanalabs.h>
|
||||
#include <uapi/drm/habanalabs_accel.h>
|
||||
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
|
@ -29,6 +29,8 @@
|
|||
#include <linux/coresight.h>
|
||||
#include <linux/dma-buf.h>
|
||||
|
||||
#include "security.h"
|
||||
|
||||
#define HL_NAME "habanalabs"
|
||||
|
||||
struct hl_device;
|
||||
|
|
@ -375,7 +377,8 @@ enum hl_cs_type {
|
|||
CS_TYPE_COLLECTIVE_WAIT,
|
||||
CS_RESERVE_SIGNALS,
|
||||
CS_UNRESERVE_SIGNALS,
|
||||
CS_TYPE_ENGINE_CORE
|
||||
CS_TYPE_ENGINE_CORE,
|
||||
CS_TYPE_FLUSH_PCI_HBW_WRITES,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -545,6 +548,8 @@ struct hl_hints_range {
|
|||
/**
|
||||
* struct asic_fixed_properties - ASIC specific immutable properties.
|
||||
* @hw_queues_props: H/W queues properties.
|
||||
* @special_blocks: points to an array containing special blocks info.
|
||||
* @skip_special_blocks_cfg: special blocks skip configs.
|
||||
* @cpucp_info: received various information from CPU-CP regarding the H/W, e.g.
|
||||
* available sensors.
|
||||
* @uboot_ver: F/W U-boot version.
|
||||
|
|
@ -644,6 +649,10 @@ struct hl_hints_range {
|
|||
* (i.e. the DRAM supports multiple page sizes), otherwise
|
||||
* it will shall be equal to dram_page_size.
|
||||
* @num_engine_cores: number of engine cpu cores
|
||||
* @num_of_special_blocks: special_blocks array size.
|
||||
* @glbl_err_cause_num: global err cause number.
|
||||
* @hbw_flush_reg: register to read to generate HBW flush. value of 0 means HBW flush is
|
||||
* not supported.
|
||||
* @collective_first_sob: first sync object available for collective use
|
||||
* @collective_first_mon: first monitor available for collective use
|
||||
* @sync_stream_first_sob: first sync object available for sync stream use
|
||||
|
|
@ -692,6 +701,8 @@ struct hl_hints_range {
|
|||
*/
|
||||
struct asic_fixed_properties {
|
||||
struct hw_queue_properties *hw_queues_props;
|
||||
struct hl_special_block_info *special_blocks;
|
||||
struct hl_skip_blocks_cfg skip_special_blocks_cfg;
|
||||
struct cpucp_info cpucp_info;
|
||||
char uboot_ver[VERSION_MAX_LEN];
|
||||
char preboot_ver[VERSION_MAX_LEN];
|
||||
|
|
@ -764,6 +775,9 @@ struct asic_fixed_properties {
|
|||
u32 xbar_edge_enabled_mask;
|
||||
u32 device_mem_alloc_default_page_size;
|
||||
u32 num_engine_cores;
|
||||
u32 num_of_special_blocks;
|
||||
u32 glbl_err_cause_num;
|
||||
u32 hbw_flush_reg;
|
||||
u16 collective_first_sob;
|
||||
u16 collective_first_mon;
|
||||
u16 sync_stream_first_sob;
|
||||
|
|
@ -935,6 +949,7 @@ struct hl_mmap_mem_buf {
|
|||
* @size: holds the CB's size.
|
||||
* @roundup_size: holds the cb size after roundup to page size.
|
||||
* @cs_cnt: holds number of CS that this CB participates in.
|
||||
* @is_handle_destroyed: atomic boolean indicating whether or not the CB handle was destroyed.
|
||||
* @is_pool: true if CB was acquired from the pool, false otherwise.
|
||||
* @is_internal: internally allocated
|
||||
* @is_mmu_mapped: true if the CB is mapped to the device's MMU.
|
||||
|
|
@ -951,6 +966,7 @@ struct hl_cb {
|
|||
u32 size;
|
||||
u32 roundup_size;
|
||||
atomic_t cs_cnt;
|
||||
atomic_t is_handle_destroyed;
|
||||
u8 is_pool;
|
||||
u8 is_internal;
|
||||
u8 is_mmu_mapped;
|
||||
|
|
@ -1077,20 +1093,25 @@ struct hl_cq {
|
|||
atomic_t free_slots_cnt;
|
||||
};
|
||||
|
||||
enum hl_user_interrupt_type {
|
||||
HL_USR_INTERRUPT_CQ = 0,
|
||||
HL_USR_INTERRUPT_DECODER,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hl_user_interrupt - holds user interrupt information
|
||||
* @hdev: pointer to the device structure
|
||||
* @type: user interrupt type
|
||||
* @wait_list_head: head to the list of user threads pending on this interrupt
|
||||
* @wait_list_lock: protects wait_list_head
|
||||
* @interrupt_id: msix interrupt id
|
||||
* @is_decoder: whether this entry represents a decoder interrupt
|
||||
*/
|
||||
struct hl_user_interrupt {
|
||||
struct hl_device *hdev;
|
||||
struct list_head wait_list_head;
|
||||
spinlock_t wait_list_lock;
|
||||
u32 interrupt_id;
|
||||
bool is_decoder;
|
||||
struct hl_device *hdev;
|
||||
enum hl_user_interrupt_type type;
|
||||
struct list_head wait_list_head;
|
||||
spinlock_t wait_list_lock;
|
||||
u32 interrupt_id;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -1540,8 +1561,10 @@ struct engines_data {
|
|||
* @check_if_razwi_happened: check if there was a razwi due to RR violation.
|
||||
* @access_dev_mem: access device memory
|
||||
* @set_dram_bar_base: set the base of the DRAM BAR
|
||||
* @set_engine_cores: set a config command to enigne cores
|
||||
* @set_engine_cores: set a config command to engine cores
|
||||
* @send_device_activity: indication to FW about device availability
|
||||
* @set_dram_properties: set DRAM related properties.
|
||||
* @set_binning_masks: set binning/enable masks for all relevant components.
|
||||
*/
|
||||
struct hl_asic_funcs {
|
||||
int (*early_init)(struct hl_device *hdev);
|
||||
|
|
@ -1679,6 +1702,8 @@ struct hl_asic_funcs {
|
|||
int (*set_engine_cores)(struct hl_device *hdev, u32 *core_ids,
|
||||
u32 num_cores, u32 core_command);
|
||||
int (*send_device_activity)(struct hl_device *hdev, bool open);
|
||||
int (*set_dram_properties)(struct hl_device *hdev);
|
||||
int (*set_binning_masks)(struct hl_device *hdev);
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -1739,8 +1764,9 @@ struct hl_cs_counters_atomic {
|
|||
* struct hl_dmabuf_priv - a dma-buf private object.
|
||||
* @dmabuf: pointer to dma-buf object.
|
||||
* @ctx: pointer to the dma-buf owner's context.
|
||||
* @phys_pg_pack: pointer to physical page pack if the dma-buf was exported for
|
||||
* memory allocation handle.
|
||||
* @phys_pg_pack: pointer to physical page pack if the dma-buf was exported
|
||||
* where virtual memory is supported.
|
||||
* @memhash_hnode: pointer to the memhash node. this object holds the export count.
|
||||
* @device_address: physical address of the device's memory. Relevant only
|
||||
* if phys_pg_pack is NULL (dma-buf was exported from address).
|
||||
* The total size can be taken from the dmabuf object.
|
||||
|
|
@ -1749,6 +1775,7 @@ struct hl_dmabuf_priv {
|
|||
struct dma_buf *dmabuf;
|
||||
struct hl_ctx *ctx;
|
||||
struct hl_vm_phys_pg_pack *phys_pg_pack;
|
||||
struct hl_vm_hash_node *memhash_hnode;
|
||||
uint64_t device_address;
|
||||
};
|
||||
|
||||
|
|
@ -1923,6 +1950,7 @@ struct hl_userptr {
|
|||
* @type: CS_TYPE_*.
|
||||
* @jobs_cnt: counter of submitted jobs on all queues.
|
||||
* @encaps_sig_hdl_id: encaps signals handle id, set for the first staged cs.
|
||||
* @completion_timestamp: timestamp of the last completed cs job.
|
||||
* @sob_addr_offset: sob offset from the configuration base address.
|
||||
* @initial_sob_count: count of completed signals in SOB before current submission of signal or
|
||||
* cs with encaps signals.
|
||||
|
|
@ -1955,6 +1983,7 @@ struct hl_cs {
|
|||
struct list_head staged_cs_node;
|
||||
struct list_head debugfs_list;
|
||||
struct hl_cs_encaps_sig_handle *encaps_sig_hdl;
|
||||
ktime_t completion_timestamp;
|
||||
u64 sequence;
|
||||
u64 staged_sequence;
|
||||
u64 timeout_jiffies;
|
||||
|
|
@ -1990,6 +2019,7 @@ struct hl_cs {
|
|||
* @debugfs_list: node in debugfs list of command submission jobs.
|
||||
* @refcount: reference counter for usage of the CS job.
|
||||
* @queue_type: the type of the H/W queue this job is submitted to.
|
||||
* @timestamp: timestamp upon job completion
|
||||
* @id: the id of this job inside a CS.
|
||||
* @hw_queue_id: the id of the H/W queue this job is submitted to.
|
||||
* @user_cb_size: the actual size of the CB we got from the user.
|
||||
|
|
@ -2016,6 +2046,7 @@ struct hl_cs_job {
|
|||
struct list_head debugfs_list;
|
||||
struct kref refcount;
|
||||
enum hl_queue_type queue_type;
|
||||
ktime_t timestamp;
|
||||
u32 id;
|
||||
u32 hw_queue_id;
|
||||
u32 user_cb_size;
|
||||
|
|
@ -2076,12 +2107,16 @@ struct hl_cs_parser {
|
|||
* hl_userptr).
|
||||
* @node: node to hang on the hash table in context object.
|
||||
* @vaddr: key virtual address.
|
||||
* @handle: memory handle for device memory allocation.
|
||||
* @ptr: value pointer (hl_vm_phys_pg_list or hl_userptr).
|
||||
* @export_cnt: number of exports from within the VA block.
|
||||
*/
|
||||
struct hl_vm_hash_node {
|
||||
struct hlist_node node;
|
||||
u64 vaddr;
|
||||
u64 handle;
|
||||
void *ptr;
|
||||
int export_cnt;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -2109,10 +2144,10 @@ struct hl_vm_hw_block_list_node {
|
|||
* @pages: the physical page array.
|
||||
* @npages: num physical pages in the pack.
|
||||
* @total_size: total size of all the pages in this list.
|
||||
* @exported_size: buffer exported size.
|
||||
* @node: used to attach to deletion list that is used when all the allocations are cleared
|
||||
* at the teardown of the context.
|
||||
* @mapping_cnt: number of shared mappings.
|
||||
* @exporting_cnt: number of dma-buf exporting.
|
||||
* @asid: the context related to this list.
|
||||
* @page_size: size of each page in the pack.
|
||||
* @flags: HL_MEM_* flags related to this list.
|
||||
|
|
@ -2126,9 +2161,9 @@ struct hl_vm_phys_pg_pack {
|
|||
u64 *pages;
|
||||
u64 npages;
|
||||
u64 total_size;
|
||||
u64 exported_size;
|
||||
struct list_head node;
|
||||
atomic_t mapping_cnt;
|
||||
u32 exporting_cnt;
|
||||
u32 asid;
|
||||
u32 page_size;
|
||||
u32 flags;
|
||||
|
|
@ -2675,11 +2710,11 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
|
|||
p->size = sz; \
|
||||
})
|
||||
|
||||
#define HL_USR_INTR_STRUCT_INIT(usr_intr, hdev, intr_id, decoder) \
|
||||
#define HL_USR_INTR_STRUCT_INIT(usr_intr, hdev, intr_id, intr_type) \
|
||||
({ \
|
||||
usr_intr.hdev = hdev; \
|
||||
usr_intr.interrupt_id = intr_id; \
|
||||
usr_intr.is_decoder = decoder; \
|
||||
usr_intr.type = intr_type; \
|
||||
INIT_LIST_HEAD(&usr_intr.wait_list_head); \
|
||||
spin_lock_init(&usr_intr.wait_list_lock); \
|
||||
})
|
||||
|
|
@ -2961,37 +2996,53 @@ struct undefined_opcode_info {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct page_fault_info - info about page fault
|
||||
* @pgf_info: page fault information.
|
||||
* struct page_fault_info - page fault information.
|
||||
* @page_fault: holds information collected during a page fault.
|
||||
* @user_mappings: buffer containing user mappings.
|
||||
* @num_of_user_mappings: number of user mappings.
|
||||
* @page_fault_detected: if set as 1, then a page-fault was discovered for the
|
||||
* first time after the driver has finished booting-up.
|
||||
* Since we're looking for the page-fault's root cause,
|
||||
* we don't care of the others that might follow it-
|
||||
* so once changed to 1, it will remain that way.
|
||||
* @page_fault_info_available: indicates that a page fault info is now available.
|
||||
*/
|
||||
struct page_fault_info {
|
||||
struct hl_page_fault_info pgf;
|
||||
struct hl_page_fault_info page_fault;
|
||||
struct hl_user_mapping *user_mappings;
|
||||
u64 num_of_user_mappings;
|
||||
atomic_t page_fault_detected;
|
||||
bool page_fault_info_available;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct razwi_info - RAZWI information.
|
||||
* @razwi: holds information collected during a RAZWI
|
||||
* @razwi_detected: if set as 1, then a RAZWI was discovered for the
|
||||
* first time after the driver has finished booting-up.
|
||||
* Since we're looking for the RAZWI's root cause,
|
||||
* we don't care of the others that might follow it-
|
||||
* so once changed to 1, it will remain that way.
|
||||
* @razwi_info_available: indicates that a RAZWI info is now available.
|
||||
*/
|
||||
struct razwi_info {
|
||||
struct hl_info_razwi_event razwi;
|
||||
atomic_t razwi_detected;
|
||||
bool razwi_info_available;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hl_error_info - holds information collected during an error.
|
||||
* @cs_timeout: CS timeout error information.
|
||||
* @razwi: razwi information.
|
||||
* @razwi_info_recorded: if set writing to razwi information is enabled.
|
||||
* otherwise - disabled, so the first (root cause) razwi will not be
|
||||
* overwritten.
|
||||
* @undef_opcode: undefined opcode information
|
||||
* @pgf_info: page fault information.
|
||||
* @pgf_info_recorded: if set writing to page fault information is enabled.
|
||||
* otherwise - disabled, so the first (root cause) page fault will not be
|
||||
* overwritten.
|
||||
* @razwi_info: RAZWI information.
|
||||
* @undef_opcode: undefined opcode information.
|
||||
* @page_fault_info: page fault information.
|
||||
*/
|
||||
struct hl_error_info {
|
||||
struct cs_timeout_info cs_timeout;
|
||||
struct hl_info_razwi_event razwi;
|
||||
atomic_t razwi_info_recorded;
|
||||
struct razwi_info razwi_info;
|
||||
struct undefined_opcode_info undef_opcode;
|
||||
struct page_fault_info pgf_info;
|
||||
atomic_t pgf_info_recorded;
|
||||
struct page_fault_info page_fault_info;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -3157,6 +3208,8 @@ struct hl_reset_info {
|
|||
* @edma_binning: contains mask of edma engines that is received from the f/w which
|
||||
* indicates which edma engines are binned-out
|
||||
* @device_release_watchdog_timeout_sec: device release watchdog timeout value in seconds.
|
||||
* @rotator_binning: contains mask of rotators engines that is received from the f/w
|
||||
* which indicates which rotator engines are binned-out(Gaudi3 and above).
|
||||
* @id: device minor.
|
||||
* @id_control: minor of the control device.
|
||||
* @cdev_idx: char device index. Used for setting its name.
|
||||
|
|
@ -3214,6 +3267,7 @@ struct hl_reset_info {
|
|||
* @heartbeat: Controls if we want to enable the heartbeat mechanism vs. the f/w, which verifies
|
||||
* that the f/w is always alive. Used only for testing.
|
||||
* @supports_ctx_switch: true if a ctx switch is required upon first submission.
|
||||
* @support_preboot_binning: true if we support read binning info from preboot.
|
||||
*/
|
||||
struct hl_device {
|
||||
struct pci_dev *pdev;
|
||||
|
|
@ -3322,6 +3376,7 @@ struct hl_device {
|
|||
u32 decoder_binning;
|
||||
u32 edma_binning;
|
||||
u32 device_release_watchdog_timeout_sec;
|
||||
u32 rotator_binning;
|
||||
u16 id;
|
||||
u16 id_control;
|
||||
u16 cdev_idx;
|
||||
|
|
@ -3355,6 +3410,7 @@ struct hl_device {
|
|||
u8 supports_mmu_prefetch;
|
||||
u8 reset_upon_device_release;
|
||||
u8 supports_ctx_switch;
|
||||
u8 support_preboot_binning;
|
||||
|
||||
/* Parameters for bring-up */
|
||||
u64 nic_ports_mask;
|
||||
|
|
@ -3729,6 +3785,7 @@ int hl_fw_cpucp_power_get(struct hl_device *hdev, u64 *power);
|
|||
void hl_fw_ask_hard_reset_without_linux(struct hl_device *hdev);
|
||||
void hl_fw_ask_halt_machine_without_linux(struct hl_device *hdev);
|
||||
int hl_fw_init_cpu(struct hl_device *hdev);
|
||||
int hl_fw_wait_preboot_ready(struct hl_device *hdev);
|
||||
int hl_fw_read_preboot_status(struct hl_device *hdev);
|
||||
int hl_fw_dynamic_send_protocol_cmd(struct hl_device *hdev,
|
||||
struct fw_load_mgr *fw_loader,
|
||||
|
|
@ -3772,6 +3829,8 @@ int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
|
|||
void hl_fw_set_pll_profile(struct hl_device *hdev);
|
||||
void hl_sysfs_add_dev_clk_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp);
|
||||
void hl_sysfs_add_dev_vrm_attr(struct hl_device *hdev, struct attribute_group *dev_vrm_attr_grp);
|
||||
int hl_fw_send_generic_request(struct hl_device *hdev, enum hl_passthrough_type sub_opcode,
|
||||
dma_addr_t buff, u32 *size);
|
||||
|
||||
void hw_sob_get(struct hl_hw_sob *hw_sob);
|
||||
void hw_sob_put(struct hl_hw_sob *hw_sob);
|
||||
|
|
@ -3786,6 +3845,7 @@ void hl_dec_fini(struct hl_device *hdev);
|
|||
void hl_dec_ctx_fini(struct hl_ctx *ctx);
|
||||
|
||||
void hl_release_pending_user_interrupts(struct hl_device *hdev);
|
||||
void hl_abort_waitings_for_completion(struct hl_device *hdev);
|
||||
int hl_cs_signal_sob_wraparound_handler(struct hl_device *hdev, u32 q_idx,
|
||||
struct hl_hw_sob **hw_sob, u32 count, bool encaps_sig);
|
||||
|
||||
|
|
@ -222,9 +222,11 @@ int hl_device_open(struct inode *inode, struct file *filp)
|
|||
hl_debugfs_add_file(hpriv);
|
||||
|
||||
atomic_set(&hdev->captured_err_info.cs_timeout.write_enable, 1);
|
||||
atomic_set(&hdev->captured_err_info.razwi_info_recorded, 0);
|
||||
atomic_set(&hdev->captured_err_info.pgf_info_recorded, 0);
|
||||
atomic_set(&hdev->captured_err_info.razwi_info.razwi_detected, 0);
|
||||
atomic_set(&hdev->captured_err_info.page_fault_info.page_fault_detected, 0);
|
||||
hdev->captured_err_info.undef_opcode.write_enable = true;
|
||||
hdev->captured_err_info.razwi_info.razwi_info_available = false;
|
||||
hdev->captured_err_info.page_fault_info.page_fault_info_available = false;
|
||||
|
||||
hdev->open_counter++;
|
||||
hdev->last_successful_open_jif = jiffies;
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
#define pr_fmt(fmt) "habanalabs: " fmt
|
||||
|
||||
#include <uapi/misc/habanalabs.h>
|
||||
#include <uapi/drm/habanalabs_accel.h>
|
||||
#include "habanalabs.h"
|
||||
|
||||
#include <linux/fs.h>
|
||||
|
|
@ -607,16 +607,20 @@ static int cs_timeout_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
|||
|
||||
static int razwi_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
||||
{
|
||||
void __user *out = (void __user *) (uintptr_t) args->return_pointer;
|
||||
struct hl_device *hdev = hpriv->hdev;
|
||||
u32 max_size = args->return_size;
|
||||
struct hl_info_razwi_event *info = &hdev->captured_err_info.razwi;
|
||||
void __user *out = (void __user *) (uintptr_t) args->return_pointer;
|
||||
struct razwi_info *razwi_info;
|
||||
|
||||
if ((!max_size) || (!out))
|
||||
return -EINVAL;
|
||||
|
||||
return copy_to_user(out, info, min_t(size_t, max_size, sizeof(struct hl_info_razwi_event)))
|
||||
? -EFAULT : 0;
|
||||
razwi_info = &hdev->captured_err_info.razwi_info;
|
||||
if (!razwi_info->razwi_info_available)
|
||||
return 0;
|
||||
|
||||
return copy_to_user(out, &razwi_info->razwi,
|
||||
min_t(size_t, max_size, sizeof(struct hl_info_razwi_event))) ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
static int undefined_opcode_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
||||
|
|
@ -786,16 +790,20 @@ static int engine_status_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
|||
|
||||
static int page_fault_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
||||
{
|
||||
void __user *out = (void __user *) (uintptr_t) args->return_pointer;
|
||||
struct hl_device *hdev = hpriv->hdev;
|
||||
u32 max_size = args->return_size;
|
||||
struct hl_page_fault_info *info = &hdev->captured_err_info.pgf_info.pgf;
|
||||
void __user *out = (void __user *) (uintptr_t) args->return_pointer;
|
||||
struct page_fault_info *pgf_info;
|
||||
|
||||
if ((!max_size) || (!out))
|
||||
return -EINVAL;
|
||||
|
||||
return copy_to_user(out, info, min_t(size_t, max_size, sizeof(struct hl_page_fault_info)))
|
||||
? -EFAULT : 0;
|
||||
pgf_info = &hdev->captured_err_info.page_fault_info;
|
||||
if (!pgf_info->page_fault_info_available)
|
||||
return 0;
|
||||
|
||||
return copy_to_user(out, &pgf_info->page_fault,
|
||||
min_t(size_t, max_size, sizeof(struct hl_page_fault_info))) ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
static int user_mappings_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
||||
|
|
@ -806,18 +814,68 @@ static int user_mappings_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
|
|||
struct page_fault_info *pgf_info;
|
||||
u64 actual_size;
|
||||
|
||||
pgf_info = &hdev->captured_err_info.pgf_info;
|
||||
args->array_size = pgf_info->num_of_user_mappings;
|
||||
|
||||
if (!out)
|
||||
return -EINVAL;
|
||||
|
||||
pgf_info = &hdev->captured_err_info.page_fault_info;
|
||||
if (!pgf_info->page_fault_info_available)
|
||||
return 0;
|
||||
|
||||
args->array_size = pgf_info->num_of_user_mappings;
|
||||
|
||||
actual_size = pgf_info->num_of_user_mappings * sizeof(struct hl_user_mapping);
|
||||
if (user_buf_size < actual_size)
|
||||
return -ENOMEM;
|
||||
|
||||
return copy_to_user(out, pgf_info->user_mappings, min_t(size_t, user_buf_size, actual_size))
|
||||
? -EFAULT : 0;
|
||||
return copy_to_user(out, pgf_info->user_mappings, actual_size) ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
static int send_fw_generic_request(struct hl_device *hdev, struct hl_info_args *info_args)
|
||||
{
|
||||
void __user *buff = (void __user *) (uintptr_t) info_args->return_pointer;
|
||||
u32 size = info_args->return_size;
|
||||
dma_addr_t dma_handle;
|
||||
bool need_input_buff;
|
||||
void *fw_buff;
|
||||
int rc = 0;
|
||||
|
||||
switch (info_args->fw_sub_opcode) {
|
||||
case HL_PASSTHROUGH_VERSIONS:
|
||||
need_input_buff = false;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (size > SZ_1M) {
|
||||
dev_err(hdev->dev, "buffer size cannot exceed 1MB\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fw_buff = hl_cpu_accessible_dma_pool_alloc(hdev, size, &dma_handle);
|
||||
if (!fw_buff)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
if (need_input_buff && copy_from_user(fw_buff, buff, size)) {
|
||||
dev_dbg(hdev->dev, "Failed to copy from user FW buff\n");
|
||||
rc = -EFAULT;
|
||||
goto free_buff;
|
||||
}
|
||||
|
||||
rc = hl_fw_send_generic_request(hdev, info_args->fw_sub_opcode, dma_handle, &size);
|
||||
if (rc)
|
||||
goto free_buff;
|
||||
|
||||
if (copy_to_user(buff, fw_buff, min(size, info_args->return_size))) {
|
||||
dev_dbg(hdev->dev, "Failed to copy to user FW generic req output\n");
|
||||
rc = -EFAULT;
|
||||
}
|
||||
|
||||
free_buff:
|
||||
hl_cpu_accessible_dma_pool_free(hdev, info_args->return_size, fw_buff);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,
|
||||
|
|
@ -826,9 +884,13 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,
|
|||
enum hl_device_status status;
|
||||
struct hl_info_args *args = data;
|
||||
struct hl_device *hdev = hpriv->hdev;
|
||||
|
||||
int rc;
|
||||
|
||||
if (args->pad) {
|
||||
dev_dbg(hdev->dev, "Padding bytes must be 0\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Information is returned for the following opcodes even if the device
|
||||
* is disabled or in reset.
|
||||
|
|
@ -893,7 +955,7 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,
|
|||
}
|
||||
|
||||
if (!hl_device_operational(hdev, &status)) {
|
||||
dev_warn_ratelimited(dev,
|
||||
dev_dbg_ratelimited(dev,
|
||||
"Device is %s. Can't execute INFO IOCTL\n",
|
||||
hdev->status[status]);
|
||||
return -EBUSY;
|
||||
|
|
@ -947,6 +1009,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,
|
|||
case HL_INFO_ENGINE_STATUS:
|
||||
return engine_status_info(hpriv, args);
|
||||
|
||||
case HL_INFO_FW_GENERIC_REQ:
|
||||
return send_fw_generic_request(hdev, args);
|
||||
|
||||
default:
|
||||
dev_err(dev, "Invalid request %d\n", args->op);
|
||||
rc = -EINVAL;
|
||||
|
|
@ -975,7 +1040,7 @@ static int hl_debug_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
int rc = 0;
|
||||
|
||||
if (!hl_device_operational(hdev, &status)) {
|
||||
dev_warn_ratelimited(hdev->dev,
|
||||
dev_dbg_ratelimited(hdev->dev,
|
||||
"Device is %s. Can't execute DEBUG IOCTL\n",
|
||||
hdev->status[status]);
|
||||
return -EBUSY;
|
||||
|
|
@ -1072,8 +1137,6 @@ static long _hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg,
|
|||
retcode = -EFAULT;
|
||||
goto out_err;
|
||||
}
|
||||
} else if (cmd & IOC_OUT) {
|
||||
memset(kdata, 0, usize);
|
||||
}
|
||||
|
||||
retcode = func(hpriv, kdata);
|
||||
|
|
@ -72,15 +72,17 @@ static void irq_handle_eqe(struct work_struct *work)
|
|||
* @hdev: pointer to device structure
|
||||
* @cs_seq: command submission sequence
|
||||
* @cq: completion queue
|
||||
* @timestamp: interrupt timestamp
|
||||
*
|
||||
*/
|
||||
static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq)
|
||||
static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq, ktime_t timestamp)
|
||||
{
|
||||
struct hl_hw_queue *queue;
|
||||
struct hl_cs_job *job;
|
||||
|
||||
queue = &hdev->kernel_queues[cq->hw_queue_id];
|
||||
job = queue->shadow_queue[hl_pi_2_offset(cs_seq)];
|
||||
job->timestamp = timestamp;
|
||||
queue_work(hdev->cq_wq[cq->cq_idx], &job->finish_work);
|
||||
|
||||
atomic_inc(&queue->ci);
|
||||
|
|
@ -91,9 +93,10 @@ static void job_finish(struct hl_device *hdev, u32 cs_seq, struct hl_cq *cq)
|
|||
*
|
||||
* @hdev: pointer to device structure
|
||||
* @cs_seq: command submission sequence
|
||||
* @timestamp: interrupt timestamp
|
||||
*
|
||||
*/
|
||||
static void cs_finish(struct hl_device *hdev, u16 cs_seq)
|
||||
static void cs_finish(struct hl_device *hdev, u16 cs_seq, ktime_t timestamp)
|
||||
{
|
||||
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
||||
struct hl_hw_queue *queue;
|
||||
|
|
@ -113,6 +116,7 @@ static void cs_finish(struct hl_device *hdev, u16 cs_seq)
|
|||
atomic_inc(&queue->ci);
|
||||
}
|
||||
|
||||
cs->completion_timestamp = timestamp;
|
||||
queue_work(hdev->cs_cmplt_wq, &cs->finish_work);
|
||||
}
|
||||
|
||||
|
|
@ -130,6 +134,7 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg)
|
|||
bool shadow_index_valid, entry_ready;
|
||||
u16 shadow_index;
|
||||
struct hl_cq_entry *cq_entry, *cq_base;
|
||||
ktime_t timestamp = ktime_get();
|
||||
|
||||
if (hdev->disabled) {
|
||||
dev_dbg(hdev->dev,
|
||||
|
|
@ -171,9 +176,9 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg)
|
|||
if (shadow_index_valid && !hdev->disabled) {
|
||||
if (hdev->asic_prop.completion_mode ==
|
||||
HL_COMPLETION_MODE_CS)
|
||||
cs_finish(hdev, shadow_index);
|
||||
cs_finish(hdev, shadow_index, timestamp);
|
||||
else
|
||||
job_finish(hdev, shadow_index, cq);
|
||||
job_finish(hdev, shadow_index, cq, timestamp);
|
||||
}
|
||||
|
||||
/* Clear CQ entry ready bit */
|
||||
|
|
@ -228,7 +233,7 @@ static void hl_ts_free_objects(struct work_struct *work)
|
|||
* list to a dedicated workqueue to do the actual put.
|
||||
*/
|
||||
static int handle_registration_node(struct hl_device *hdev, struct hl_user_pending_interrupt *pend,
|
||||
struct list_head **free_list)
|
||||
struct list_head **free_list, ktime_t now)
|
||||
{
|
||||
struct timestamp_reg_free_node *free_node;
|
||||
u64 timestamp;
|
||||
|
|
@ -246,7 +251,7 @@ static int handle_registration_node(struct hl_device *hdev, struct hl_user_pendi
|
|||
if (!free_node)
|
||||
return -ENOMEM;
|
||||
|
||||
timestamp = ktime_get_ns();
|
||||
timestamp = ktime_to_ns(now);
|
||||
|
||||
*pend->ts_reg_info.timestamp_kernel_addr = timestamp;
|
||||
|
||||
|
|
@ -298,7 +303,7 @@ static void handle_user_interrupt(struct hl_device *hdev, struct hl_user_interru
|
|||
if (pend->ts_reg_info.buf) {
|
||||
if (!reg_node_handle_fail) {
|
||||
rc = handle_registration_node(hdev, pend,
|
||||
&ts_reg_free_list_head);
|
||||
&ts_reg_free_list_head, now);
|
||||
if (rc)
|
||||
reg_node_handle_fail = true;
|
||||
}
|
||||
|
|
@ -333,13 +338,22 @@ irqreturn_t hl_irq_handler_user_interrupt(int irq, void *arg)
|
|||
struct hl_user_interrupt *user_int = arg;
|
||||
struct hl_device *hdev = user_int->hdev;
|
||||
|
||||
if (user_int->is_decoder)
|
||||
handle_user_interrupt(hdev, &hdev->common_decoder_interrupt);
|
||||
else
|
||||
switch (user_int->type) {
|
||||
case HL_USR_INTERRUPT_CQ:
|
||||
handle_user_interrupt(hdev, &hdev->common_user_cq_interrupt);
|
||||
|
||||
/* Handle user cq or decoder interrupts registered on this specific irq */
|
||||
handle_user_interrupt(hdev, user_int);
|
||||
/* Handle user cq interrupt registered on this specific irq */
|
||||
handle_user_interrupt(hdev, user_int);
|
||||
break;
|
||||
case HL_USR_INTERRUPT_DECODER:
|
||||
handle_user_interrupt(hdev, &hdev->common_decoder_interrupt);
|
||||
|
||||
/* Handle decoder interrupt registered on this specific irq */
|
||||
handle_user_interrupt(hdev, user_int);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* All Rights Reserved.
|
||||
*/
|
||||
|
||||
#include <uapi/misc/habanalabs.h>
|
||||
#include <uapi/drm/habanalabs_accel.h>
|
||||
#include "habanalabs.h"
|
||||
#include "../include/hw_ip/mmu/mmu_general.h"
|
||||
|
||||
|
|
@ -19,7 +19,9 @@ MODULE_IMPORT_NS(DMA_BUF);
|
|||
#define HL_MMU_DEBUG 0
|
||||
|
||||
/* use small pages for supporting non-pow2 (32M/40M/48M) DRAM phys page sizes */
|
||||
#define DRAM_POOL_PAGE_SIZE SZ_8M
|
||||
#define DRAM_POOL_PAGE_SIZE SZ_8M
|
||||
|
||||
#define MEM_HANDLE_INVALID ULONG_MAX
|
||||
|
||||
static int allocate_timestamps_buffers(struct hl_fpriv *hpriv,
|
||||
struct hl_mem_in *args, u64 *handle);
|
||||
|
|
@ -371,12 +373,6 @@ static int free_device_memory(struct hl_ctx *ctx, struct hl_mem_in *args)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (phys_pg_pack->exporting_cnt) {
|
||||
spin_unlock(&vm->idr_lock);
|
||||
dev_dbg(hdev->dev, "handle %u is exported, cannot free\n", handle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* must remove from idr before the freeing of the physical pages as the refcount of the pool
|
||||
* is also the trigger of the idr destroy
|
||||
*/
|
||||
|
|
@ -1240,6 +1236,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, u64 *device
|
|||
|
||||
hnode->ptr = vm_type;
|
||||
hnode->vaddr = ret_vaddr;
|
||||
hnode->handle = is_userptr ? MEM_HANDLE_INVALID : handle;
|
||||
|
||||
mutex_lock(&ctx->mem_hash_lock);
|
||||
hash_add(ctx->mem_hash, &hnode->node, ret_vaddr);
|
||||
|
|
@ -1313,6 +1310,12 @@ static int unmap_device_va(struct hl_ctx *ctx, struct hl_mem_in *args,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (hnode->export_cnt) {
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
dev_err(hdev->dev, "failed to unmap %#llx, memory is exported\n", vaddr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
hash_del(&hnode->node);
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
|
||||
|
|
@ -1545,10 +1548,10 @@ static int set_dma_sg(struct scatterlist *sg, u64 bar_address, u64 chunk_size,
|
|||
}
|
||||
|
||||
static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64 *pages, u64 npages,
|
||||
u64 page_size, struct device *dev,
|
||||
enum dma_data_direction dir)
|
||||
u64 page_size, u64 exported_size,
|
||||
struct device *dev, enum dma_data_direction dir)
|
||||
{
|
||||
u64 chunk_size, bar_address, dma_max_seg_size;
|
||||
u64 chunk_size, bar_address, dma_max_seg_size, cur_size_to_export, cur_npages;
|
||||
struct asic_fixed_properties *prop;
|
||||
int rc, i, j, nents, cur_page;
|
||||
struct scatterlist *sg;
|
||||
|
|
@ -1574,16 +1577,23 @@ static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64
|
|||
if (!sgt)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/* remove export size restrictions in case not explicitly defined */
|
||||
cur_size_to_export = exported_size ? exported_size : (npages * page_size);
|
||||
|
||||
/* If the size of each page is larger than the dma max segment size,
|
||||
* then we can't combine pages and the number of entries in the SGL
|
||||
* will just be the
|
||||
* <number of pages> * <chunks of max segment size in each page>
|
||||
*/
|
||||
if (page_size > dma_max_seg_size)
|
||||
nents = npages * DIV_ROUND_UP_ULL(page_size, dma_max_seg_size);
|
||||
else
|
||||
if (page_size > dma_max_seg_size) {
|
||||
/* we should limit number of pages according to the exported size */
|
||||
cur_npages = DIV_ROUND_UP_SECTOR_T(cur_size_to_export, page_size);
|
||||
nents = cur_npages * DIV_ROUND_UP_SECTOR_T(page_size, dma_max_seg_size);
|
||||
} else {
|
||||
cur_npages = npages;
|
||||
|
||||
/* Get number of non-contiguous chunks */
|
||||
for (i = 1, nents = 1, chunk_size = page_size ; i < npages ; i++) {
|
||||
for (i = 1, nents = 1, chunk_size = page_size ; i < cur_npages ; i++) {
|
||||
if (pages[i - 1] + page_size != pages[i] ||
|
||||
chunk_size + page_size > dma_max_seg_size) {
|
||||
nents++;
|
||||
|
|
@ -1593,6 +1603,7 @@ static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64
|
|||
|
||||
chunk_size += page_size;
|
||||
}
|
||||
}
|
||||
|
||||
rc = sg_alloc_table(sgt, nents, GFP_KERNEL | __GFP_ZERO);
|
||||
if (rc)
|
||||
|
|
@ -1615,7 +1626,8 @@ static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64
|
|||
else
|
||||
cur_device_address += dma_max_seg_size;
|
||||
|
||||
chunk_size = min(size_left, dma_max_seg_size);
|
||||
/* make sure not to export over exported size */
|
||||
chunk_size = min3(size_left, dma_max_seg_size, cur_size_to_export);
|
||||
|
||||
bar_address = hdev->dram_pci_bar_start + cur_device_address;
|
||||
|
||||
|
|
@ -1623,6 +1635,8 @@ static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64
|
|||
if (rc)
|
||||
goto error_unmap;
|
||||
|
||||
cur_size_to_export -= chunk_size;
|
||||
|
||||
if (size_left > dma_max_seg_size) {
|
||||
size_left -= dma_max_seg_size;
|
||||
} else {
|
||||
|
|
@ -1634,7 +1648,7 @@ static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64
|
|||
/* Merge pages and put them into the scatterlist */
|
||||
for_each_sgtable_dma_sg(sgt, sg, i) {
|
||||
chunk_size = page_size;
|
||||
for (j = cur_page + 1 ; j < npages ; j++) {
|
||||
for (j = cur_page + 1 ; j < cur_npages ; j++) {
|
||||
if (pages[j - 1] + page_size != pages[j] ||
|
||||
chunk_size + page_size > dma_max_seg_size)
|
||||
break;
|
||||
|
|
@ -1645,10 +1659,13 @@ static struct sg_table *alloc_sgt_from_device_pages(struct hl_device *hdev, u64
|
|||
bar_address = hdev->dram_pci_bar_start +
|
||||
(pages[cur_page] - prop->dram_base_address);
|
||||
|
||||
/* make sure not to export over exported size */
|
||||
chunk_size = min(chunk_size, cur_size_to_export);
|
||||
rc = set_dma_sg(sg, bar_address, chunk_size, dev, dir);
|
||||
if (rc)
|
||||
goto error_unmap;
|
||||
|
||||
cur_size_to_export -= chunk_size;
|
||||
cur_page = j;
|
||||
}
|
||||
}
|
||||
|
|
@ -1719,6 +1736,7 @@ static struct sg_table *hl_map_dmabuf(struct dma_buf_attachment *attachment,
|
|||
phys_pg_pack->pages,
|
||||
phys_pg_pack->npages,
|
||||
phys_pg_pack->page_size,
|
||||
phys_pg_pack->exported_size,
|
||||
attachment->dev,
|
||||
dir);
|
||||
else
|
||||
|
|
@ -1726,6 +1744,7 @@ static struct sg_table *hl_map_dmabuf(struct dma_buf_attachment *attachment,
|
|||
&hl_dmabuf->device_address,
|
||||
1,
|
||||
hl_dmabuf->dmabuf->size,
|
||||
0,
|
||||
attachment->dev,
|
||||
dir);
|
||||
|
||||
|
|
@ -1763,18 +1782,20 @@ static void hl_unmap_dmabuf(struct dma_buf_attachment *attachment,
|
|||
static void hl_release_dmabuf(struct dma_buf *dmabuf)
|
||||
{
|
||||
struct hl_dmabuf_priv *hl_dmabuf = dmabuf->priv;
|
||||
struct hl_ctx *ctx = hl_dmabuf->ctx;
|
||||
struct hl_device *hdev = ctx->hdev;
|
||||
struct hl_vm *vm = &hdev->vm;
|
||||
struct hl_ctx *ctx;
|
||||
|
||||
if (hl_dmabuf->phys_pg_pack) {
|
||||
spin_lock(&vm->idr_lock);
|
||||
hl_dmabuf->phys_pg_pack->exporting_cnt--;
|
||||
spin_unlock(&vm->idr_lock);
|
||||
if (!hl_dmabuf)
|
||||
return;
|
||||
|
||||
ctx = hl_dmabuf->ctx;
|
||||
|
||||
if (hl_dmabuf->memhash_hnode) {
|
||||
mutex_lock(&ctx->mem_hash_lock);
|
||||
hl_dmabuf->memhash_hnode->export_cnt--;
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
}
|
||||
|
||||
hl_ctx_put(hl_dmabuf->ctx);
|
||||
|
||||
hl_ctx_put(ctx);
|
||||
kfree(hl_dmabuf);
|
||||
}
|
||||
|
||||
|
|
@ -1785,7 +1806,7 @@ static const struct dma_buf_ops habanalabs_dmabuf_ops = {
|
|||
.release = hl_release_dmabuf,
|
||||
};
|
||||
|
||||
static int export_dmabuf_common(struct hl_ctx *ctx,
|
||||
static int export_dmabuf(struct hl_ctx *ctx,
|
||||
struct hl_dmabuf_priv *hl_dmabuf,
|
||||
u64 total_size, int flags, int *dmabuf_fd)
|
||||
{
|
||||
|
|
@ -1806,7 +1827,7 @@ static int export_dmabuf_common(struct hl_ctx *ctx,
|
|||
|
||||
fd = dma_buf_fd(hl_dmabuf->dmabuf, flags);
|
||||
if (fd < 0) {
|
||||
dev_err(hdev->dev, "failed to get a file descriptor for a dma-buf\n");
|
||||
dev_err(hdev->dev, "failed to get a file descriptor for a dma-buf, %d\n", fd);
|
||||
rc = fd;
|
||||
goto err_dma_buf_put;
|
||||
}
|
||||
|
|
@ -1819,36 +1840,13 @@ static int export_dmabuf_common(struct hl_ctx *ctx,
|
|||
return 0;
|
||||
|
||||
err_dma_buf_put:
|
||||
hl_dmabuf->dmabuf->priv = NULL;
|
||||
dma_buf_put(hl_dmabuf->dmabuf);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* export_dmabuf_from_addr() - export a dma-buf object for the given memory
|
||||
* address and size.
|
||||
* @ctx: pointer to the context structure.
|
||||
* @device_addr: device memory physical address.
|
||||
* @size: size of device memory.
|
||||
* @flags: DMA-BUF file/FD flags.
|
||||
* @dmabuf_fd: pointer to result FD that represents the dma-buf object.
|
||||
*
|
||||
* Create and export a dma-buf object for an existing memory allocation inside
|
||||
* the device memory, and return a FD which is associated with the dma-buf
|
||||
* object.
|
||||
*
|
||||
* Return: 0 on success, non-zero for failure.
|
||||
*/
|
||||
static int export_dmabuf_from_addr(struct hl_ctx *ctx, u64 device_addr,
|
||||
u64 size, int flags, int *dmabuf_fd)
|
||||
static int validate_export_params_common(struct hl_device *hdev, u64 device_addr, u64 size)
|
||||
{
|
||||
struct hl_dmabuf_priv *hl_dmabuf;
|
||||
struct hl_device *hdev = ctx->hdev;
|
||||
struct asic_fixed_properties *prop;
|
||||
u64 bar_address;
|
||||
int rc;
|
||||
|
||||
prop = &hdev->asic_prop;
|
||||
|
||||
if (!IS_ALIGNED(device_addr, PAGE_SIZE)) {
|
||||
dev_dbg(hdev->dev,
|
||||
"exported device memory address 0x%llx should be aligned to 0x%lx\n",
|
||||
|
|
@ -1863,49 +1861,150 @@ static int export_dmabuf_from_addr(struct hl_ctx *ctx, u64 device_addr,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int validate_export_params_no_mmu(struct hl_device *hdev, u64 device_addr, u64 size)
|
||||
{
|
||||
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
||||
u64 bar_address;
|
||||
int rc;
|
||||
|
||||
rc = validate_export_params_common(hdev, device_addr, size);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (device_addr < prop->dram_user_base_address ||
|
||||
device_addr + size > prop->dram_end_address ||
|
||||
device_addr + size < device_addr) {
|
||||
(device_addr + size) > prop->dram_end_address ||
|
||||
(device_addr + size) < device_addr) {
|
||||
dev_dbg(hdev->dev,
|
||||
"DRAM memory range 0x%llx (+0x%llx) is outside of DRAM boundaries\n",
|
||||
device_addr, size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bar_address = hdev->dram_pci_bar_start +
|
||||
(device_addr - prop->dram_base_address);
|
||||
bar_address = hdev->dram_pci_bar_start + (device_addr - prop->dram_base_address);
|
||||
|
||||
if (bar_address + size >
|
||||
hdev->dram_pci_bar_start + prop->dram_pci_bar_size ||
|
||||
bar_address + size < bar_address) {
|
||||
if ((bar_address + size) > (hdev->dram_pci_bar_start + prop->dram_pci_bar_size) ||
|
||||
(bar_address + size) < bar_address) {
|
||||
dev_dbg(hdev->dev,
|
||||
"DRAM memory range 0x%llx (+0x%llx) is outside of PCI BAR boundaries\n",
|
||||
device_addr, size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
hl_dmabuf = kzalloc(sizeof(*hl_dmabuf), GFP_KERNEL);
|
||||
if (!hl_dmabuf)
|
||||
return -ENOMEM;
|
||||
return 0;
|
||||
}
|
||||
|
||||
hl_dmabuf->device_address = device_addr;
|
||||
static int validate_export_params(struct hl_device *hdev, u64 device_addr, u64 size, u64 offset,
|
||||
struct hl_vm_phys_pg_pack *phys_pg_pack)
|
||||
{
|
||||
struct asic_fixed_properties *prop = &hdev->asic_prop;
|
||||
u64 bar_address;
|
||||
int i, rc;
|
||||
|
||||
rc = export_dmabuf_common(ctx, hl_dmabuf, size, flags, dmabuf_fd);
|
||||
rc = validate_export_params_common(hdev, device_addr, size);
|
||||
if (rc)
|
||||
goto err_free_dmabuf_wrapper;
|
||||
return rc;
|
||||
|
||||
if ((offset + size) > phys_pg_pack->total_size) {
|
||||
dev_dbg(hdev->dev, "offset %#llx and size %#llx exceed total map size %#llx\n",
|
||||
offset, size, phys_pg_pack->total_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0 ; i < phys_pg_pack->npages ; i++) {
|
||||
|
||||
bar_address = hdev->dram_pci_bar_start +
|
||||
(phys_pg_pack->pages[i] - prop->dram_base_address);
|
||||
|
||||
if ((bar_address + phys_pg_pack->page_size) >
|
||||
(hdev->dram_pci_bar_start + prop->dram_pci_bar_size) ||
|
||||
(bar_address + phys_pg_pack->page_size) < bar_address) {
|
||||
dev_dbg(hdev->dev,
|
||||
"DRAM memory range 0x%llx (+0x%x) is outside of PCI BAR boundaries\n",
|
||||
phys_pg_pack->pages[i],
|
||||
phys_pg_pack->page_size);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
err_free_dmabuf_wrapper:
|
||||
kfree(hl_dmabuf);
|
||||
return rc;
|
||||
static struct hl_vm_hash_node *memhash_node_export_get(struct hl_ctx *ctx, u64 addr)
|
||||
{
|
||||
struct hl_device *hdev = ctx->hdev;
|
||||
struct hl_vm_hash_node *hnode;
|
||||
|
||||
/* get the memory handle */
|
||||
mutex_lock(&ctx->mem_hash_lock);
|
||||
hash_for_each_possible(ctx->mem_hash, hnode, node, (unsigned long)addr)
|
||||
if (addr == hnode->vaddr)
|
||||
break;
|
||||
|
||||
if (!hnode) {
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
dev_dbg(hdev->dev, "map address %#llx not found\n", addr);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (upper_32_bits(hnode->handle)) {
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
dev_dbg(hdev->dev, "invalid handle %#llx for map address %#llx\n",
|
||||
hnode->handle, addr);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
/*
|
||||
* node found, increase export count so this memory cannot be unmapped
|
||||
* and the hash node cannot be deleted.
|
||||
*/
|
||||
hnode->export_cnt++;
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
|
||||
return hnode;
|
||||
}
|
||||
|
||||
static void memhash_node_export_put(struct hl_ctx *ctx, struct hl_vm_hash_node *hnode)
|
||||
{
|
||||
mutex_lock(&ctx->mem_hash_lock);
|
||||
hnode->export_cnt--;
|
||||
mutex_unlock(&ctx->mem_hash_lock);
|
||||
}
|
||||
|
||||
static struct hl_vm_phys_pg_pack *get_phys_pg_pack_from_hash_node(struct hl_device *hdev,
|
||||
struct hl_vm_hash_node *hnode)
|
||||
{
|
||||
struct hl_vm_phys_pg_pack *phys_pg_pack;
|
||||
struct hl_vm *vm = &hdev->vm;
|
||||
|
||||
spin_lock(&vm->idr_lock);
|
||||
phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, (u32) hnode->handle);
|
||||
if (!phys_pg_pack) {
|
||||
spin_unlock(&vm->idr_lock);
|
||||
dev_dbg(hdev->dev, "no match for handle 0x%x\n", (u32) hnode->handle);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
spin_unlock(&vm->idr_lock);
|
||||
|
||||
if (phys_pg_pack->vm_type != VM_TYPE_PHYS_PACK) {
|
||||
dev_dbg(hdev->dev, "handle 0x%llx does not represent DRAM memory\n", hnode->handle);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return phys_pg_pack;
|
||||
}
|
||||
|
||||
/**
|
||||
* export_dmabuf_from_handle() - export a dma-buf object for the given memory
|
||||
* handle.
|
||||
* export_dmabuf_from_addr() - export a dma-buf object for the given memory
|
||||
* address and size.
|
||||
* @ctx: pointer to the context structure.
|
||||
* @handle: device memory allocation handle.
|
||||
* @addr: device address.
|
||||
* @size: size of device memory to export.
|
||||
* @offset: the offset into the buffer from which to start exporting
|
||||
* @flags: DMA-BUF file/FD flags.
|
||||
* @dmabuf_fd: pointer to result FD that represents the dma-buf object.
|
||||
*
|
||||
|
|
@ -1915,87 +2014,69 @@ err_free_dmabuf_wrapper:
|
|||
*
|
||||
* Return: 0 on success, non-zero for failure.
|
||||
*/
|
||||
static int export_dmabuf_from_handle(struct hl_ctx *ctx, u64 handle, int flags,
|
||||
int *dmabuf_fd)
|
||||
static int export_dmabuf_from_addr(struct hl_ctx *ctx, u64 addr, u64 size, u64 offset,
|
||||
int flags, int *dmabuf_fd)
|
||||
{
|
||||
struct hl_vm_phys_pg_pack *phys_pg_pack;
|
||||
struct hl_dmabuf_priv *hl_dmabuf;
|
||||
struct hl_device *hdev = ctx->hdev;
|
||||
struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
|
||||
struct hl_vm_hash_node *hnode = NULL;
|
||||
struct asic_fixed_properties *prop;
|
||||
struct hl_vm *vm = &hdev->vm;
|
||||
u64 bar_address;
|
||||
int rc, i;
|
||||
struct hl_dmabuf_priv *hl_dmabuf;
|
||||
struct hl_device *hdev;
|
||||
u64 export_addr;
|
||||
int rc;
|
||||
|
||||
hdev = ctx->hdev;
|
||||
prop = &hdev->asic_prop;
|
||||
|
||||
if (upper_32_bits(handle)) {
|
||||
dev_dbg(hdev->dev, "no match for handle 0x%llx\n", handle);
|
||||
/* offset must be 0 in devices without virtual memory support */
|
||||
if (!prop->dram_supports_virtual_memory && offset) {
|
||||
dev_dbg(hdev->dev, "offset is not allowed in device without virtual memory\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock(&vm->idr_lock);
|
||||
|
||||
phys_pg_pack = idr_find(&vm->phys_pg_pack_handles, (u32) handle);
|
||||
if (!phys_pg_pack) {
|
||||
spin_unlock(&vm->idr_lock);
|
||||
dev_dbg(hdev->dev, "no match for handle 0x%x\n", (u32) handle);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* increment now to avoid freeing device memory while exporting */
|
||||
phys_pg_pack->exporting_cnt++;
|
||||
|
||||
spin_unlock(&vm->idr_lock);
|
||||
|
||||
if (phys_pg_pack->vm_type != VM_TYPE_PHYS_PACK) {
|
||||
dev_dbg(hdev->dev, "handle 0x%llx does not represent DRAM memory\n", handle);
|
||||
rc = -EINVAL;
|
||||
goto err_dec_exporting_cnt;
|
||||
}
|
||||
|
||||
for (i = 0 ; i < phys_pg_pack->npages ; i++) {
|
||||
|
||||
bar_address = hdev->dram_pci_bar_start +
|
||||
(phys_pg_pack->pages[i] -
|
||||
prop->dram_base_address);
|
||||
|
||||
if (bar_address + phys_pg_pack->page_size >
|
||||
hdev->dram_pci_bar_start + prop->dram_pci_bar_size ||
|
||||
bar_address + phys_pg_pack->page_size < bar_address) {
|
||||
|
||||
dev_dbg(hdev->dev,
|
||||
"DRAM memory range 0x%llx (+0x%x) is outside of PCI BAR boundaries\n",
|
||||
phys_pg_pack->pages[i],
|
||||
phys_pg_pack->page_size);
|
||||
|
||||
rc = -EINVAL;
|
||||
goto err_dec_exporting_cnt;
|
||||
}
|
||||
}
|
||||
export_addr = addr + offset;
|
||||
|
||||
hl_dmabuf = kzalloc(sizeof(*hl_dmabuf), GFP_KERNEL);
|
||||
if (!hl_dmabuf) {
|
||||
rc = -ENOMEM;
|
||||
goto err_dec_exporting_cnt;
|
||||
if (!hl_dmabuf)
|
||||
return -ENOMEM;
|
||||
|
||||
if (prop->dram_supports_virtual_memory) {
|
||||
hnode = memhash_node_export_get(ctx, addr);
|
||||
if (IS_ERR(hnode)) {
|
||||
rc = PTR_ERR(hnode);
|
||||
goto err_free_dmabuf_wrapper;
|
||||
}
|
||||
phys_pg_pack = get_phys_pg_pack_from_hash_node(hdev, hnode);
|
||||
if (IS_ERR(phys_pg_pack)) {
|
||||
rc = PTR_ERR(phys_pg_pack);
|
||||
goto dec_memhash_export_cnt;
|
||||
}
|
||||
rc = validate_export_params(hdev, export_addr, size, offset, phys_pg_pack);
|
||||
if (rc)
|
||||
goto dec_memhash_export_cnt;
|
||||
|
||||
phys_pg_pack->exported_size = size;
|
||||
hl_dmabuf->phys_pg_pack = phys_pg_pack;
|
||||
hl_dmabuf->memhash_hnode = hnode;
|
||||
} else {
|
||||
rc = validate_export_params_no_mmu(hdev, export_addr, size);
|
||||
if (rc)
|
||||
goto err_free_dmabuf_wrapper;
|
||||
}
|
||||
|
||||
hl_dmabuf->phys_pg_pack = phys_pg_pack;
|
||||
hl_dmabuf->device_address = export_addr;
|
||||
|
||||
rc = export_dmabuf_common(ctx, hl_dmabuf, phys_pg_pack->total_size,
|
||||
flags, dmabuf_fd);
|
||||
rc = export_dmabuf(ctx, hl_dmabuf, size, flags, dmabuf_fd);
|
||||
if (rc)
|
||||
goto err_free_dmabuf_wrapper;
|
||||
goto dec_memhash_export_cnt;
|
||||
|
||||
return 0;
|
||||
|
||||
dec_memhash_export_cnt:
|
||||
if (prop->dram_supports_virtual_memory)
|
||||
memhash_node_export_put(ctx, hnode);
|
||||
err_free_dmabuf_wrapper:
|
||||
kfree(hl_dmabuf);
|
||||
|
||||
err_dec_exporting_cnt:
|
||||
spin_lock(&vm->idr_lock);
|
||||
phys_pg_pack->exporting_cnt--;
|
||||
spin_unlock(&vm->idr_lock);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
@ -2089,12 +2170,13 @@ static int hl_ts_mmap(struct hl_mmap_mem_buf *buf, struct vm_area_struct *vma, v
|
|||
static int hl_ts_alloc_buf(struct hl_mmap_mem_buf *buf, gfp_t gfp, void *args)
|
||||
{
|
||||
struct hl_ts_buff *ts_buff = NULL;
|
||||
u32 size, num_elements;
|
||||
u32 num_elements;
|
||||
size_t size;
|
||||
void *p;
|
||||
|
||||
num_elements = *(u32 *)args;
|
||||
|
||||
ts_buff = kzalloc(sizeof(*ts_buff), GFP_KERNEL);
|
||||
ts_buff = kzalloc(sizeof(*ts_buff), gfp);
|
||||
if (!ts_buff)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -2180,7 +2262,7 @@ int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
int rc, dmabuf_fd = -EBADF;
|
||||
|
||||
if (!hl_device_operational(hdev, &status)) {
|
||||
dev_warn_ratelimited(hdev->dev,
|
||||
dev_dbg_ratelimited(hdev->dev,
|
||||
"Device is %s. Can't execute MEMORY IOCTL\n",
|
||||
hdev->status[status]);
|
||||
return -EBUSY;
|
||||
|
|
@ -2269,17 +2351,12 @@ int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data)
|
|||
break;
|
||||
|
||||
case HL_MEM_OP_EXPORT_DMABUF_FD:
|
||||
if (hdev->asic_prop.dram_supports_virtual_memory)
|
||||
rc = export_dmabuf_from_handle(ctx,
|
||||
args->in.export_dmabuf_fd.handle,
|
||||
args->in.flags,
|
||||
&dmabuf_fd);
|
||||
else
|
||||
rc = export_dmabuf_from_addr(ctx,
|
||||
args->in.export_dmabuf_fd.handle,
|
||||
args->in.export_dmabuf_fd.mem_size,
|
||||
args->in.flags,
|
||||
&dmabuf_fd);
|
||||
rc = export_dmabuf_from_addr(ctx,
|
||||
args->in.export_dmabuf_fd.addr,
|
||||
args->in.export_dmabuf_fd.mem_size,
|
||||
args->in.export_dmabuf_fd.offset,
|
||||
args->in.flags,
|
||||
&dmabuf_fd);
|
||||
memset(args, 0, sizeof(*args));
|
||||
args->out.fd = dmabuf_fd;
|
||||
break;
|
||||
|
|
@ -25,8 +25,7 @@ struct hl_mmap_mem_buf *hl_mmap_mem_buf_get(struct hl_mem_mgr *mmg, u64 handle)
|
|||
buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT));
|
||||
if (!buf) {
|
||||
spin_unlock(&mmg->lock);
|
||||
dev_warn(mmg->dev,
|
||||
"Buff get failed, no match to handle %#llx\n", handle);
|
||||
dev_dbg(mmg->dev, "Buff get failed, no match to handle %#llx\n", handle);
|
||||
return NULL;
|
||||
}
|
||||
kref_get(&buf->refcount);
|
||||
|
|
@ -781,7 +781,7 @@ static void mmu_dma_mem_free_from_chunk(struct gen_pool *pool,
|
|||
struct gen_pool_chunk *chunk,
|
||||
void *data)
|
||||
{
|
||||
struct hl_device *hdev = (struct hl_device *)data;
|
||||
struct hl_device *hdev = data;
|
||||
|
||||
hl_asic_dma_free_coherent(hdev, (chunk->end_addr - chunk->start_addr) + 1,
|
||||
(void *)chunk->start_addr, chunk->phys_addr);
|
||||
|
|
@ -344,7 +344,6 @@ static void dram_default_mapping_fini(struct hl_ctx *ctx)
|
|||
}
|
||||
}
|
||||
|
||||
hop2_pte_addr = hop2_addr;
|
||||
hop2_pte_addr = hop2_addr;
|
||||
for (i = 0 ; i < num_of_hop3 ; i++) {
|
||||
clear_pte(ctx, hop2_pte_addr);
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue