clk: renesas: Updates for v5.17 (take two)
- Add support for the new R-Car S4-8 (R8A779F0) SoC, - Add GPU clock and resets on RZ/G2L, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYbxjuwAKCRCKwlD9ZEnx cPqVAP9nga20zmYmTzwf6/KINu2Nk2GyUeOoYfmZgJBb1579yAEAinDtjFcVisfq EVOJvY9WjZDzV1oYehMl2aI2OCN3VgQ= =SDQ2 -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a07g044: Add GPU clock and reset entries clk: renesas: r9a07g044: Add mux and divider for G clock clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro clk: renesas: cpg-mssr: Add support for R-Car S4-8 clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions
This commit is contained in:
Stephen Boyd
commit
a5ce1d5118
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@ -31,6 +31,7 @@ config CLK_RENESAS
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select CLK_R8A77990 if ARCH_R8A77990
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select CLK_R8A77995 if ARCH_R8A77995
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select CLK_R8A779A0 if ARCH_R8A779A0
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select CLK_R8A779F0 if ARCH_R8A779F0
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select CLK_R9A06G032 if ARCH_R9A06G032
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select CLK_R9A07G044 if ARCH_R9A07G044
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select CLK_SH73A0 if ARCH_SH73A0
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@ -149,8 +150,11 @@ config CLK_R8A77995
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config CLK_R8A779A0
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bool "R-Car V3U clock support" if COMPILE_TEST
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select CLK_RCAR_CPG_LIB
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select CLK_RENESAS_CPG_MSSR
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select CLK_RCAR_GEN4_CPG
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config CLK_R8A779F0
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bool "R-Car S4-8 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN4_CPG
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config CLK_R9A06G032
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bool "RZ/N1D clock support" if COMPILE_TEST
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@ -178,6 +182,11 @@ config CLK_RCAR_GEN3_CPG
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select CLK_RCAR_CPG_LIB
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_GEN4_CPG
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bool "R-Car Gen4 clock support" if COMPILE_TEST
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select CLK_RCAR_CPG_LIB
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_USB2_CLOCK_SEL
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bool "Renesas R-Car USB2 clock selector support"
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depends on ARCH_RENESAS || COMPILE_TEST
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@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
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obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
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obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
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obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o
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obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
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obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
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@ -10,47 +10,19 @@
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/bug.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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#include "rcar-cpg-lib.h"
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#include "renesas-cpg-mssr.h"
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enum rcar_r8a779a0_clk_types {
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CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_R8A779A0_PLL1,
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CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
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CLK_TYPE_R8A779A0_PLL5,
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CLK_TYPE_R8A779A0_Z,
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CLK_TYPE_R8A779A0_SDH,
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CLK_TYPE_R8A779A0_SD,
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CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_R8A779A0_RPCSRC,
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CLK_TYPE_R8A779A0_RPC,
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CLK_TYPE_R8A779A0_RPCD2,
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};
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struct rcar_r8a779a0_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll5_mult;
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u8 pll5_div;
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u8 osc_prediv;
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};
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#include "rcar-gen4-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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@ -86,36 +58,18 @@ enum clk_ids {
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};
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#define DEF_PLL(_name, _id, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
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.offset = _offset)
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#define DEF_Z(_name, _id, _parent, _div, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_Z, _parent, .div = _div, \
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.offset = _offset)
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#define DEF_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SDH, _parent, .offset = _offset)
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#define DEF_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
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#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
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static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
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DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
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DEF_PLL(".pll20", CLK_PLL20, 0x0834),
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DEF_PLL(".pll21", CLK_PLL21, 0x0838),
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DEF_PLL(".pll30", CLK_PLL30, 0x083c),
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@ -132,14 +86,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
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DEF_RATE(".oco", CLK_OCO, 32768),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A779A0_RPCSRC, CLK_PLL5),
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DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_R8A779A0_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_R8A779A0_RPCD2,
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
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DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
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R8A779A0_CLK_RPC),
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/* Core Clock Outputs */
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DEF_Z("z0", R8A779A0_CLK_Z0, CLK_PLL20, 2, 0),
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DEF_Z("z1", R8A779A0_CLK_Z1, CLK_PLL21, 2, 8),
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DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
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DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8),
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DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
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DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
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@ -163,16 +117,16 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
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DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1),
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DEF_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
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DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
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DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
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DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
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DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
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DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
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DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884),
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DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
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DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
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DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
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};
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static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
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@ -276,258 +230,6 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
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DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
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};
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static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
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static unsigned int cpg_clk_extalr __initdata;
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static u32 cpg_mode __initdata;
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/*
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* Z0 Clock & Z1 Clock
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*/
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#define CPG_FRQCRB 0x00000804
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#define CPG_FRQCRB_KICK BIT(31)
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#define CPG_FRQCRC 0x00000808
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struct cpg_z_clk {
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struct clk_hw hw;
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void __iomem *reg;
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void __iomem *kick_reg;
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unsigned long max_rate; /* Maximum rate for normal mode */
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unsigned int fixed_div;
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u32 mask;
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};
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
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static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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u32 val;
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val = readl(zclk->reg) & zclk->mask;
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mult = 32 - (val >> __ffs(zclk->mask));
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
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32 * zclk->fixed_div);
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}
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static int cpg_z_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int min_mult, max_mult, mult;
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unsigned long rate, prate;
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rate = min(req->rate, req->max_rate);
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if (rate <= zclk->max_rate) {
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/* Set parent rate to initial value for normal modes */
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prate = zclk->max_rate;
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} else {
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/* Set increased parent rate for boost modes */
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prate = rate;
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}
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req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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prate * zclk->fixed_div);
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prate = req->best_parent_rate / zclk->fixed_div;
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min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
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max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
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if (max_mult < min_mult)
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return -EINVAL;
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mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
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mult = clamp(mult, min_mult, max_mult);
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req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
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return 0;
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}
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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unsigned int i;
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mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
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parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
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/*
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* Note: There is no HW information about the worst case latency.
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*
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* Using experimental measurements, it seems that no more than
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* ~10 iterations are needed, independently of the CPU rate.
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* Since this value might be dependent on external xtal rate, pll1
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* rate or even the other emulation clocks rate, use 1000 as a
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* "super" safe value.
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*/
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for (i = 1000; i; i--) {
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static const struct clk_ops cpg_z_clk_ops = {
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.recalc_rate = cpg_z_clk_recalc_rate,
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.determine_rate = cpg_z_clk_determine_rate,
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.set_rate = cpg_z_clk_set_rate,
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};
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static struct clk * __init cpg_z_clk_register(const char *name,
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const char *parent_name,
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void __iomem *reg,
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unsigned int div,
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unsigned int offset)
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{
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struct clk_init_data init = {};
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struct cpg_z_clk *zclk;
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struct clk *clk;
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zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
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if (!zclk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &cpg_z_clk_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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zclk->reg = reg + CPG_FRQCRC;
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zclk->kick_reg = reg + CPG_FRQCRB;
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zclk->hw.init = &init;
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zclk->mask = GENMASK(offset + 4, offset);
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zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
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clk = clk_register(NULL, &zclk->hw);
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if (IS_ERR(clk)) {
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kfree(zclk);
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return clk;
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}
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zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
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zclk->fixed_div;
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return clk;
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}
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/*
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* RPC Clocks
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||||
*/
|
||||
#define CPG_RPCCKCR 0x874
|
||||
|
||||
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
|
||||
{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers)
|
||||
{
|
||||
const struct clk *parent;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent & 0xffff]; /* some types use high bits */
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_R8A779A0_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
div = cpg_pll_config->pll1_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL2X_3X:
|
||||
value = readl(base + core->offset);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_PLL5:
|
||||
mult = cpg_pll_config->pll5_mult;
|
||||
div = cpg_pll_config->pll5_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_Z:
|
||||
return cpg_z_clk_register(core->name, __clk_get_name(parent),
|
||||
base, core->div, core->offset);
|
||||
|
||||
case CLK_TYPE_R8A779A0_SDH:
|
||||
return cpg_sdh_clk_register(core->name, base + core->offset,
|
||||
__clk_get_name(parent), notifiers);
|
||||
|
||||
case CLK_TYPE_R8A779A0_SD:
|
||||
return cpg_sd_clk_register(core->name, base + core->offset,
|
||||
__clk_get_name(parent));
|
||||
|
||||
case CLK_TYPE_R8A779A0_MDSEL:
|
||||
/*
|
||||
* Clock selectable between two parents and two fixed dividers
|
||||
* using a mode pin
|
||||
*/
|
||||
if (cpg_mode & BIT(core->offset)) {
|
||||
div = core->div & 0xffff;
|
||||
} else {
|
||||
parent = clks[core->parent >> 16];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
div = core->div >> 16;
|
||||
}
|
||||
mult = 1;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_OSC:
|
||||
/*
|
||||
* Clock combining OSC EXTAL predivider and a fixed divider
|
||||
*/
|
||||
div = cpg_pll_config->osc_prediv * core->div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_R8A779A0_RPCSRC:
|
||||
return clk_register_divider_table(NULL, core->name,
|
||||
__clk_get_name(parent), 0,
|
||||
base + CPG_RPCCKCR, 3, 2, 0,
|
||||
cpg_rpcsrc_div_table,
|
||||
&cpg_lock);
|
||||
|
||||
case CLK_TYPE_R8A779A0_RPC:
|
||||
return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
|
||||
__clk_get_name(parent), notifiers);
|
||||
|
||||
case CLK_TYPE_R8A779A0_RPCD2:
|
||||
return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
|
||||
__clk_get_name(parent));
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(907), /* RWDT */
|
||||
};
|
||||
|
|
@ -546,17 +248,19 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
|
|||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
|
||||
{ 1, 128, 1, 192, 1, 16, },
|
||||
{ 1, 106, 1, 160, 1, 19, },
|
||||
{ 0, 0, 0, 0, 0, 0, },
|
||||
{ 2, 128, 1, 192, 1, 32, },
|
||||
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
|
||||
{ 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
|
||||
{ 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
|
||||
{ 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
|
||||
};
|
||||
|
||||
|
||||
static int __init r8a779a0_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
|
|
@ -564,10 +268,8 @@ static int __init r8a779a0_cpg_mssr_init(struct device *dev)
|
|||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
cpg_clk_extalr = CLK_EXTALR;
|
||||
spin_lock_init(&cpg_lock);
|
||||
|
||||
return 0;
|
||||
return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
|
||||
|
|
@ -588,7 +290,7 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
|
|||
|
||||
/* Callbacks */
|
||||
.init = r8a779a0_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
|
||||
.cpg_clk_register = rcar_gen4_cpg_clk_register,
|
||||
|
||||
.reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
|
||||
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,183 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a779a0-cpg-mssr.c
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen4-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A779F0_CLK_R,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL5,
|
||||
CLK_PLL6,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL2_DIV2,
|
||||
CLK_PLL3_DIV2,
|
||||
CLK_PLL5_DIV2,
|
||||
CLK_PLL5_DIV4,
|
||||
CLK_PLL6_DIV2,
|
||||
CLK_S0,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
|
||||
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
|
||||
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
|
||||
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
|
||||
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("cl16m", R8A779F0_CLK_CL16M, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_mm", R8A779F0_CLK_S0D2_MM, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3_mm", R8A779F0_CLK_S0D3_MM, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4_mm", R8A779F0_CLK_S0D4_MM, CLK_S0, 4, 1),
|
||||
DEF_FIXED("cl16m_mm", R8A779F0_CLK_CL16M_MM, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_rt", R8A779F0_CLK_S0D2_RT, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3_rt", R8A779F0_CLK_S0D3_RT, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4_rt", R8A779F0_CLK_S0D4_RT, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6_rt", R8A779F0_CLK_S0D6_RT, CLK_S0, 6, 1),
|
||||
DEF_FIXED("cl16m_rt", R8A779F0_CLK_CL16M_RT, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d3_per", R8A779F0_CLK_S0D3_PER, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d6_per", R8A779F0_CLK_S0D6_PER, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12_per", R8A779F0_CLK_S0D12_PER, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24_per", R8A779F0_CLK_S0D24_PER, CLK_S0, 24, 1),
|
||||
DEF_FIXED("cl16m_per", R8A779F0_CLK_CL16M_PER, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_hsc", R8A779F0_CLK_S0D2_HSC, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3_hsc", R8A779F0_CLK_S0D3_HSC, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4_hsc", R8A779F0_CLK_S0D4_HSC, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6_hsc", R8A779F0_CLK_S0D6_HSC, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1),
|
||||
DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1),
|
||||
DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1),
|
||||
DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1),
|
||||
DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870),
|
||||
DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
|
||||
|
||||
DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
|
||||
DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
|
||||
DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
/*
|
||||
* MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC
|
||||
* 14 13 (MHz)
|
||||
* ----------------------------------------------------------------
|
||||
* 0 0 16 / 1 x200 x150 x200 x200 x134 /15
|
||||
* 0 1 20 / 1 x160 x120 x160 x160 x106 /19
|
||||
* 1 0 Prohibited setting
|
||||
* 1 1 40 / 2 x160 x120 x160 x160 x106 /38
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
|
||||
{ 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, },
|
||||
{ 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
|
||||
{ 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, },
|
||||
};
|
||||
|
||||
static int __init r8a779f0_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a779f0_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a779f0_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a779f0_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),
|
||||
.num_hw_mod_clks = 28 * 32,
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a779f0_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen4_cpg_clk_register,
|
||||
|
||||
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
|
||||
};
|
||||
|
|
@ -32,9 +32,9 @@ enum clk_ids {
|
|||
CLK_PLL3_400,
|
||||
CLK_PLL3_533,
|
||||
CLK_PLL3_DIV2,
|
||||
CLK_PLL3_DIV2_2,
|
||||
CLK_PLL3_DIV2_4,
|
||||
CLK_PLL3_DIV2_4_2,
|
||||
CLK_PLL3_DIV4,
|
||||
CLK_SEL_PLL3_3,
|
||||
CLK_DIV_PLL3_C,
|
||||
CLK_PLL4,
|
||||
|
|
@ -50,6 +50,7 @@ enum clk_ids {
|
|||
CLK_PLL2_SDHI_266,
|
||||
CLK_SD0_DIV4,
|
||||
CLK_SD1_DIV4,
|
||||
CLK_SEL_GPU2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
|
|
@ -77,6 +78,7 @@ static const struct clk_div_table dtable_1_32[] = {
|
|||
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
|
||||
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
|
||||
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
|
||||
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
|
||||
|
||||
static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
|
|
@ -106,9 +108,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
|
|||
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
|
||||
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
|
||||
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
|
||||
DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
|
||||
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
|
||||
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
|
||||
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
|
||||
|
|
@ -116,6 +118,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
|
|||
|
||||
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
|
||||
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
|
||||
DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
|
||||
sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
|
||||
|
||||
/* Core output clk */
|
||||
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
|
||||
|
|
@ -141,6 +145,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
|
|||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
|
||||
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
|
||||
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
|
||||
CLK_DIVIDER_HIWORD_MASK),
|
||||
};
|
||||
|
||||
static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
|
||||
|
|
@ -192,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
|
|||
0x554, 6),
|
||||
DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
|
||||
0x554, 7),
|
||||
DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
|
||||
0x558, 0),
|
||||
DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 1),
|
||||
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 2),
|
||||
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
|
||||
0x570, 0),
|
||||
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
|
||||
|
|
@ -279,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
|
|||
DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
|
||||
DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
|
||||
DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
|
||||
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
|
||||
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
|
||||
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
|
||||
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
|
||||
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
|
||||
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
|
||||
|
|
|
|||
|
|
@ -0,0 +1,305 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* R-Car Gen4 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on rcar-gen3-cpg.c
|
||||
*
|
||||
* Copyright (C) 2015-2018 Glider bvba
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen4-cpg.h"
|
||||
#include "rcar-cpg-lib.h"
|
||||
|
||||
static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst;
|
||||
static unsigned int cpg_clk_extalr __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
/*
|
||||
* Z0 Clock & Z1 Clock
|
||||
*/
|
||||
#define CPG_FRQCRB 0x00000804
|
||||
#define CPG_FRQCRB_KICK BIT(31)
|
||||
#define CPG_FRQCRC 0x00000808
|
||||
|
||||
struct cpg_z_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
void __iomem *kick_reg;
|
||||
unsigned long max_rate; /* Maximum rate for normal mode */
|
||||
unsigned int fixed_div;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
|
||||
|
||||
static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
u32 val;
|
||||
|
||||
val = readl(zclk->reg) & zclk->mask;
|
||||
mult = 32 - (val >> __ffs(zclk->mask));
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
|
||||
32 * zclk->fixed_div);
|
||||
}
|
||||
|
||||
static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
unsigned long rate, prate;
|
||||
|
||||
rate = min(req->rate, req->max_rate);
|
||||
if (rate <= zclk->max_rate) {
|
||||
/* Set parent rate to initial value for normal modes */
|
||||
prate = zclk->max_rate;
|
||||
} else {
|
||||
/* Set increased parent rate for boost modes */
|
||||
prate = rate;
|
||||
}
|
||||
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
|
||||
prate * zclk->fixed_div);
|
||||
|
||||
prate = req->best_parent_rate / zclk->fixed_div;
|
||||
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
|
||||
max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
unsigned int i;
|
||||
|
||||
mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
|
||||
parent_rate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
return -EBUSY;
|
||||
|
||||
cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
|
||||
|
||||
/*
|
||||
* Set KICK bit in FRQCRB to update hardware setting and wait for
|
||||
* clock change completion.
|
||||
*/
|
||||
cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
|
||||
|
||||
/*
|
||||
* Note: There is no HW information about the worst case latency.
|
||||
*
|
||||
* Using experimental measurements, it seems that no more than
|
||||
* ~10 iterations are needed, independently of the CPU rate.
|
||||
* Since this value might be dependent on external xtal rate, pll1
|
||||
* rate or even the other emulation clocks rate, use 1000 as a
|
||||
* "super" safe value.
|
||||
*/
|
||||
for (i = 1000; i; i--) {
|
||||
if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
|
||||
return 0;
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.determine_rate = cpg_z_clk_determine_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_z_clk_register(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *reg,
|
||||
unsigned int div,
|
||||
unsigned int offset)
|
||||
{
|
||||
struct clk_init_data init = {};
|
||||
struct cpg_z_clk *zclk;
|
||||
struct clk *clk;
|
||||
|
||||
zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
|
||||
if (!zclk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &cpg_z_clk_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
zclk->reg = reg + CPG_FRQCRC;
|
||||
zclk->kick_reg = reg + CPG_FRQCRB;
|
||||
zclk->hw.init = &init;
|
||||
zclk->mask = GENMASK(offset + 4, offset);
|
||||
zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
|
||||
|
||||
clk = clk_register(NULL, &zclk->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(zclk);
|
||||
return clk;
|
||||
}
|
||||
|
||||
zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
|
||||
zclk->fixed_div;
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* RPC Clocks
|
||||
*/
|
||||
static const struct clk_div_table cpg_rpcsrc_div_table[] = {
|
||||
{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
|
||||
};
|
||||
|
||||
struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers)
|
||||
{
|
||||
const struct clk *parent;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent & 0xffff]; /* some types use high bits */
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_GEN4_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
div = cpg_pll_config->pll1_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL2:
|
||||
mult = cpg_pll_config->pll2_mult;
|
||||
div = cpg_pll_config->pll2_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
div = cpg_pll_config->pll3_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL5:
|
||||
mult = cpg_pll_config->pll5_mult;
|
||||
div = cpg_pll_config->pll5_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL6:
|
||||
mult = cpg_pll_config->pll6_mult;
|
||||
div = cpg_pll_config->pll6_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL2X_3X:
|
||||
value = readl(base + core->offset);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_Z:
|
||||
return cpg_z_clk_register(core->name, __clk_get_name(parent),
|
||||
base, core->div, core->offset);
|
||||
|
||||
case CLK_TYPE_GEN4_SDSRC:
|
||||
div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_SDH:
|
||||
return cpg_sdh_clk_register(core->name, base + core->offset,
|
||||
__clk_get_name(parent), notifiers);
|
||||
|
||||
case CLK_TYPE_GEN4_SD:
|
||||
return cpg_sd_clk_register(core->name, base + core->offset,
|
||||
__clk_get_name(parent));
|
||||
|
||||
case CLK_TYPE_GEN4_MDSEL:
|
||||
/*
|
||||
* Clock selectable between two parents and two fixed dividers
|
||||
* using a mode pin
|
||||
*/
|
||||
if (cpg_mode & BIT(core->offset)) {
|
||||
div = core->div & 0xffff;
|
||||
} else {
|
||||
parent = clks[core->parent >> 16];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
div = core->div >> 16;
|
||||
}
|
||||
mult = 1;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_OSC:
|
||||
/*
|
||||
* Clock combining OSC EXTAL predivider and a fixed divider
|
||||
*/
|
||||
div = cpg_pll_config->osc_prediv * core->div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_RPCSRC:
|
||||
return clk_register_divider_table(NULL, core->name,
|
||||
__clk_get_name(parent), 0,
|
||||
base + CPG_RPCCKCR, 3, 2, 0,
|
||||
cpg_rpcsrc_div_table,
|
||||
&cpg_lock);
|
||||
|
||||
case CLK_TYPE_GEN4_RPC:
|
||||
return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
|
||||
__clk_get_name(parent), notifiers);
|
||||
|
||||
case CLK_TYPE_GEN4_RPCD2:
|
||||
return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
|
||||
__clk_get_name(parent));
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
|
||||
unsigned int clk_extalr, u32 mode)
|
||||
{
|
||||
cpg_pll_config = config;
|
||||
cpg_clk_extalr = clk_extalr;
|
||||
cpg_mode = mode;
|
||||
|
||||
spin_lock_init(&cpg_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* R-Car Gen4 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
|
||||
#define __CLK_RENESAS_RCAR_GEN4_CPG_H__
|
||||
|
||||
enum rcar_gen4_clk_types {
|
||||
CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN4_PLL1,
|
||||
CLK_TYPE_GEN4_PLL2,
|
||||
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
|
||||
CLK_TYPE_GEN4_PLL3,
|
||||
CLK_TYPE_GEN4_PLL5,
|
||||
CLK_TYPE_GEN4_PLL6,
|
||||
CLK_TYPE_GEN4_SDSRC,
|
||||
CLK_TYPE_GEN4_SDH,
|
||||
CLK_TYPE_GEN4_SD,
|
||||
CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_GEN4_Z,
|
||||
CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN4_RPCSRC,
|
||||
CLK_TYPE_GEN4_RPC,
|
||||
CLK_TYPE_GEN4_RPCD2,
|
||||
|
||||
/* SoC specific definitions start here */
|
||||
CLK_TYPE_GEN4_SOC_BASE,
|
||||
};
|
||||
|
||||
#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
|
||||
|
||||
#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
|
||||
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
|
||||
|
||||
struct rcar_gen4_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
u8 pll1_mult;
|
||||
u8 pll1_div;
|
||||
u8 pll2_mult;
|
||||
u8 pll2_div;
|
||||
u8 pll3_mult;
|
||||
u8 pll3_div;
|
||||
u8 pll5_mult;
|
||||
u8 pll5_div;
|
||||
u8 pll6_mult;
|
||||
u8 pll6_div;
|
||||
u8 osc_prediv;
|
||||
};
|
||||
|
||||
#define CPG_RPCCKCR 0x874
|
||||
#define SD0CKCR1 0x8a4
|
||||
|
||||
struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers);
|
||||
int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
|
||||
unsigned int clk_extalr, u32 mode);
|
||||
|
||||
#endif
|
||||
|
|
@ -57,9 +57,11 @@ static const u16 mstpsr[] = {
|
|||
0x9A0, 0x9A4, 0x9A8, 0x9AC,
|
||||
};
|
||||
|
||||
static const u16 mstpsr_for_v3u[] = {
|
||||
static const u16 mstpsr_for_gen4[] = {
|
||||
0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
|
||||
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
|
||||
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
|
||||
0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
|
||||
0x2E60, 0x2E64, 0x2E68, 0x2E6C,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -71,9 +73,11 @@ static const u16 smstpcr[] = {
|
|||
0x990, 0x994, 0x998, 0x99C,
|
||||
};
|
||||
|
||||
static const u16 mstpcr_for_v3u[] = {
|
||||
static const u16 mstpcr_for_gen4[] = {
|
||||
0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
|
||||
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
|
||||
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
|
||||
0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
|
||||
0x2D60, 0x2D64, 0x2D68, 0x2D6C,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -95,9 +99,11 @@ static const u16 srcr[] = {
|
|||
0x920, 0x924, 0x928, 0x92C,
|
||||
};
|
||||
|
||||
static const u16 srcr_for_v3u[] = {
|
||||
static const u16 srcr_for_gen4[] = {
|
||||
0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
|
||||
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
|
||||
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
|
||||
0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
|
||||
0x2C60, 0x2C64, 0x2C68, 0x2C6C,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -109,9 +115,11 @@ static const u16 srstclr[] = {
|
|||
0x960, 0x964, 0x968, 0x96C,
|
||||
};
|
||||
|
||||
static const u16 srstclr_for_v3u[] = {
|
||||
static const u16 srstclr_for_gen4[] = {
|
||||
0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
|
||||
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
|
||||
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
|
||||
0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
|
||||
0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -158,7 +166,7 @@ struct cpg_mssr_priv {
|
|||
struct {
|
||||
u32 mask;
|
||||
u32 val;
|
||||
} smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
|
||||
} smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)];
|
||||
|
||||
struct clk *clks[];
|
||||
};
|
||||
|
|
@ -839,6 +847,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.compatible = "renesas,r8a779a0-cpg-mssr",
|
||||
.data = &r8a779a0_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A779F0
|
||||
{
|
||||
.compatible = "renesas,r8a779f0-cpg-mssr",
|
||||
.data = &r8a779f0_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
@ -982,11 +996,11 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
|||
priv->reset_clear_regs = srstclr;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
|
||||
priv->control_regs = stbcr;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
|
||||
priv->status_regs = mstpsr_for_v3u;
|
||||
priv->control_regs = mstpcr_for_v3u;
|
||||
priv->reset_regs = srcr_for_v3u;
|
||||
priv->reset_clear_regs = srstclr_for_v3u;
|
||||
} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
|
||||
priv->status_regs = mstpsr_for_gen4;
|
||||
priv->control_regs = mstpcr_for_gen4;
|
||||
priv->reset_regs = srcr_for_gen4;
|
||||
priv->reset_clear_regs = srstclr_for_gen4;
|
||||
} else {
|
||||
error = -EINVAL;
|
||||
goto out_err;
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ struct device_node;
|
|||
enum clk_reg_layout {
|
||||
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
|
||||
CLK_REG_LAYOUT_RZ_A,
|
||||
CLK_REG_LAYOUT_RCAR_V3U,
|
||||
CLK_REG_LAYOUT_RCAR_GEN4,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -178,6 +178,7 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
|
||||
|
||||
void __init cpg_mssr_early_init(struct device_node *np,
|
||||
const struct cpg_mssr_info *info);
|
||||
|
|
|
|||
|
|
@ -12,9 +12,11 @@
|
|||
#define CPG_PL1_DDIV (0x200)
|
||||
#define CPG_PL2_DDIV (0x204)
|
||||
#define CPG_PL3A_DDIV (0x208)
|
||||
#define CPG_PL6_DDIV (0x210)
|
||||
#define CPG_PL2SDHI_DSEL (0x218)
|
||||
#define CPG_CLKSTATUS (0x280)
|
||||
#define CPG_PL3_SSEL (0x408)
|
||||
#define CPG_PL6_SSEL (0x414)
|
||||
#define CPG_PL6_ETH_SSEL (0x418)
|
||||
|
||||
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
|
||||
|
|
@ -35,12 +37,14 @@
|
|||
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
|
||||
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
|
||||
#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
|
||||
#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
|
||||
|
||||
#define SEL_PLL_PACK(offset, bitpos, size) \
|
||||
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
|
||||
|
||||
#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
|
||||
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
|
||||
#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
|
||||
|
||||
#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
|
||||
#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
|
||||
/*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a779f0 CPG Core Clocks */
|
||||
|
||||
#define R8A779F0_CLK_ZX 0
|
||||
#define R8A779F0_CLK_ZS 1
|
||||
#define R8A779F0_CLK_ZT 2
|
||||
#define R8A779F0_CLK_ZTR 3
|
||||
#define R8A779F0_CLK_S0D2 4
|
||||
#define R8A779F0_CLK_S0D3 5
|
||||
#define R8A779F0_CLK_S0D4 6
|
||||
#define R8A779F0_CLK_S0D2_MM 7
|
||||
#define R8A779F0_CLK_S0D3_MM 8
|
||||
#define R8A779F0_CLK_S0D4_MM 9
|
||||
#define R8A779F0_CLK_S0D2_RT 10
|
||||
#define R8A779F0_CLK_S0D3_RT 11
|
||||
#define R8A779F0_CLK_S0D4_RT 12
|
||||
#define R8A779F0_CLK_S0D6_RT 13
|
||||
#define R8A779F0_CLK_S0D3_PER 14
|
||||
#define R8A779F0_CLK_S0D6_PER 15
|
||||
#define R8A779F0_CLK_S0D12_PER 16
|
||||
#define R8A779F0_CLK_S0D24_PER 17
|
||||
#define R8A779F0_CLK_S0D2_HSC 18
|
||||
#define R8A779F0_CLK_S0D3_HSC 19
|
||||
#define R8A779F0_CLK_S0D4_HSC 20
|
||||
#define R8A779F0_CLK_S0D6_HSC 21
|
||||
#define R8A779F0_CLK_S0D12_HSC 22
|
||||
#define R8A779F0_CLK_S0D2_CC 23
|
||||
#define R8A779F0_CLK_CL 24
|
||||
#define R8A779F0_CLK_CL16M 25
|
||||
#define R8A779F0_CLK_CL16M_MM 26
|
||||
#define R8A779F0_CLK_CL16M_RT 27
|
||||
#define R8A779F0_CLK_CL16M_PER 28
|
||||
#define R8A779F0_CLK_CL16M_HSC 29
|
||||
#define R8A779F0_CLK_Z0 30
|
||||
#define R8A779F0_CLK_Z1 31
|
||||
#define R8A779F0_CLK_ZB3 32
|
||||
#define R8A779F0_CLK_ZB3D2 33
|
||||
#define R8A779F0_CLK_ZB3D4 34
|
||||
#define R8A779F0_CLK_SD0H 35
|
||||
#define R8A779F0_CLK_SD0 36
|
||||
#define R8A779F0_CLK_RPC 37
|
||||
#define R8A779F0_CLK_RPCD2 38
|
||||
#define R8A779F0_CLK_MSO 39
|
||||
#define R8A779F0_CLK_SASYNCRT 40
|
||||
#define R8A779F0_CLK_SASYNCPERD1 41
|
||||
#define R8A779F0_CLK_SASYNCPERD2 42
|
||||
#define R8A779F0_CLK_SASYNCPERD4 43
|
||||
#define R8A779F0_CLK_DBGSOC_HSC 44
|
||||
#define R8A779F0_CLK_RSW2 45
|
||||
#define R8A779F0_CLK_OSC 46
|
||||
#define R8A779F0_CLK_ZR 47
|
||||
#define R8A779F0_CLK_CPEX 48
|
||||
#define R8A779F0_CLK_CBFUSA 49
|
||||
#define R8A779F0_CLK_R 50
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
|
||||
/*
|
||||
* Copyright (C) 2021 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the Power Domain Register Numbers (PDR)
|
||||
*/
|
||||
|
||||
#define R8A779F0_PD_A1E0D0C0 0
|
||||
#define R8A779F0_PD_A1E0D0C1 1
|
||||
#define R8A779F0_PD_A1E0D1C0 2
|
||||
#define R8A779F0_PD_A1E0D1C1 3
|
||||
#define R8A779F0_PD_A1E1D0C0 4
|
||||
#define R8A779F0_PD_A1E1D0C1 5
|
||||
#define R8A779F0_PD_A1E1D1C0 6
|
||||
#define R8A779F0_PD_A1E1D1C1 7
|
||||
#define R8A779F0_PD_A2E0D0 16
|
||||
#define R8A779F0_PD_A2E0D1 17
|
||||
#define R8A779F0_PD_A2E1D0 18
|
||||
#define R8A779F0_PD_A2E1D1 19
|
||||
#define R8A779F0_PD_A3E0 20
|
||||
#define R8A779F0_PD_A3E1 21
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A779F0_PD_ALWAYS_ON 64
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/
|
||||
Loading…
Reference in New Issue