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clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL
The audio blocks require specific clock rates. Until now we were using the closest clock rate possible with integer N-M factors. This resulted in audio playback being slightly slower than it should be. The vendor kernel gets around this (for newer SoCs) by using sigma-delta modulation to generate a fractional-N factor. This patch copies the parameters for the H3. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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1 changed files with 25 additions and 13 deletions
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@ -26,6 +26,7 @@
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#include "ccu_nkmp.h"
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#include "ccu_nm.h"
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#include "ccu_phase.h"
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#include "ccu_sdm.h"
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#include "ccu-sun8i-h3.h"
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@ -44,18 +45,29 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
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* the base (2x, 4x and 8x), and one variable divider (the one true
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* pll audio).
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*
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* We don't have any need for the variable divider for now, so we just
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* hardcode it to match with the clock names
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* With sigma-delta modulation for fractional-N on the audio PLL,
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* we have to use specific dividers. This means the variable divider
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* can no longer be used, as the audio codec requests the exact clock
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* rates we support through this mechanism. So we now hard code the
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* variable divider to 1. This means the clock rates will no longer
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* match the clock names.
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*/
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#define SUN8I_H3_PLL_AUDIO_REG 0x008
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static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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"osc24M", 0x008,
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8, 7, /* N */
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0, 5, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static struct ccu_sdm_setting pll_audio_sdm_table[] = {
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{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
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{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
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};
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static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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"osc24M", 0x008,
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8, 7, /* N */
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0, 5, /* M */
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pll_audio_sdm_table, BIT(24),
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0x284, BIT(31),
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
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"osc24M", 0x0010,
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@ -707,9 +719,9 @@ static struct ccu_common *sun50i_h5_ccu_clks[] = {
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&gpu_clk.common,
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};
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/* We hardcode the divider to 4 for now */
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/* We hardcode the divider to 1 for now */
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static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
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"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
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"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
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@ -1129,10 +1141,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
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return;
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}
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/* Force the PLL-Audio-1x divider to 4 */
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/* Force the PLL-Audio-1x divider to 1 */
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val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
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val &= ~GENMASK(19, 16);
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writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
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writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
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sunxi_ccu_probe(node, reg, desc);
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