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drm/msm/a6xx: Use the DMA API for GMU memory objects
The GMU has very few memory allocations and uses a flat memory space so there is no good reason to go out of our way to bypass the DMA APIs which were basically designed for this exact scenario. v7: Check return value of dma_set_mask_and_coherent v4: Use dma_alloc_wc() v3: Set the dma mask correctly and use dma_addr_t for the iova type v2: Pass force_dma false to of_dma_configure to require that the DMA region be set up and return error from of_dma_configure to fail probe. Reviewed-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
parent
a168b512de
commit
a5fb8b9189
2 changed files with 14 additions and 107 deletions
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@ -2,6 +2,7 @@
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/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/interconnect.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_opp.h>
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@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
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static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)
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{
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int count, i;
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u64 iova;
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if (IS_ERR_OR_NULL(bo))
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return;
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count = bo->size >> PAGE_SHIFT;
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iova = bo->iova;
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for (i = 0; i < count; i++, iova += PAGE_SIZE) {
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iommu_unmap(gmu->domain, iova, PAGE_SIZE);
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__free_pages(bo->pages[i], 0);
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}
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kfree(bo->pages);
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dma_free_wc(gmu->dev, bo->size, bo->virt, bo->iova);
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kfree(bo);
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}
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@ -942,7 +932,6 @@ static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
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size_t size)
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{
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struct a6xx_gmu_bo *bo;
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int ret, count, i;
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bo = kzalloc(sizeof(*bo), GFP_KERNEL);
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if (!bo)
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@ -950,86 +939,14 @@ static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
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bo->size = PAGE_ALIGN(size);
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count = bo->size >> PAGE_SHIFT;
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bo->virt = dma_alloc_wc(gmu->dev, bo->size, &bo->iova, GFP_KERNEL);
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bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
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if (!bo->pages) {
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if (!bo->virt) {
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kfree(bo);
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return ERR_PTR(-ENOMEM);
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}
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for (i = 0; i < count; i++) {
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bo->pages[i] = alloc_page(GFP_KERNEL);
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if (!bo->pages[i])
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goto err;
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}
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bo->iova = gmu->uncached_iova_base;
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for (i = 0; i < count; i++) {
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ret = iommu_map(gmu->domain,
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bo->iova + (PAGE_SIZE * i),
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page_to_phys(bo->pages[i]), PAGE_SIZE,
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IOMMU_READ | IOMMU_WRITE);
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if (ret) {
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DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer object\n");
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for (i = i - 1 ; i >= 0; i--)
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iommu_unmap(gmu->domain,
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bo->iova + (PAGE_SIZE * i),
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PAGE_SIZE);
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goto err;
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}
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}
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bo->virt = vmap(bo->pages, count, VM_IOREMAP,
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pgprot_writecombine(PAGE_KERNEL));
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if (!bo->virt)
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goto err;
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/* Align future IOVA addresses on 1MB boundaries */
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gmu->uncached_iova_base += ALIGN(size, SZ_1M);
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return bo;
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err:
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for (i = 0; i < count; i++) {
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if (bo->pages[i])
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__free_pages(bo->pages[i], 0);
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}
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kfree(bo->pages);
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kfree(bo);
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return ERR_PTR(-ENOMEM);
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}
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static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
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{
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int ret;
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/*
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* The GMU address space is hardcoded to treat the range
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* 0x60000000 - 0x80000000 as un-cached memory. All buffers shared
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* between the GMU and the CPU will live in this space
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*/
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gmu->uncached_iova_base = 0x60000000;
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gmu->domain = iommu_domain_alloc(&platform_bus_type);
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if (!gmu->domain)
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return -ENODEV;
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ret = iommu_attach_device(gmu->domain, gmu->dev);
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if (ret) {
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iommu_domain_free(gmu->domain);
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gmu->domain = NULL;
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}
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return ret;
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}
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/* Return the 'arc-level' for the given frequency */
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@ -1289,10 +1206,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
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a6xx_gmu_memory_free(gmu, gmu->hfi);
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iommu_detach_device(gmu->domain, gmu->dev);
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iommu_domain_free(gmu->domain);
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free_irq(gmu->gmu_irq, gmu);
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free_irq(gmu->hfi_irq, gmu);
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@ -1313,7 +1226,15 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
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gmu->dev = &pdev->dev;
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of_dma_configure(gmu->dev, node, true);
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/* Pass force_dma false to require the DT to set the dma region */
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ret = of_dma_configure(gmu->dev, node, false);
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if (ret)
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return ret;
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/* Set the mask after the of_dma_configure() */
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ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(31));
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if (ret)
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return ret;
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/* Fow now, don't do anything fancy until we get our feet under us */
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gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
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@ -1325,11 +1246,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
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if (ret)
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goto err_put_device;
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/* Set up the IOMMU context bank */
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ret = a6xx_gmu_memory_probe(gmu);
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if (ret)
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goto err_put_device;
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/* Allocate memory for for the HFI queues */
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gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K);
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if (IS_ERR(gmu->hfi))
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@ -1375,11 +1291,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
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err_memory:
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a6xx_gmu_memory_free(gmu, gmu->hfi);
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if (gmu->domain) {
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iommu_detach_device(gmu->domain, gmu->dev);
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iommu_domain_free(gmu->domain);
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}
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ret = -ENODEV;
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err_put_device:
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@ -12,8 +12,7 @@
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struct a6xx_gmu_bo {
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void *virt;
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size_t size;
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u64 iova;
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struct page **pages;
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dma_addr_t iova;
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};
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/*
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int hfi_irq;
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int gmu_irq;
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struct iommu_domain *domain;
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u64 uncached_iova_base;
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struct device *gxpd;
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int idle_level;
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