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serial: 8250_aspeed_vuart: add PORT_ASPEED_VUART port type
Commit54da3e381c
("serial: 8250_aspeed_vuart: use UPF_IOREMAP to set up register mapping") fixed a bug that had, as a side-effect, prevented the 8250_aspeed_vuart driver from enabling the VUART's FIFOs. However, fixing that (and hence enabling the FIFOs) has in turn revealed what appears to be a hardware bug in the ASPEED VUART in which the host-side THRE bit doesn't get if the BMC-side receive FIFO trigger level is set to anything but one byte. This causes problems for polled-mode writes from the host -- for example, Linux kernel console writes proceed at a glacial pace (less than 100 bytes per second) because the write path waits for a 10ms timeout to expire after every character instead of being able to continue on to the next character upon seeing THRE asserted. (GRUB behaves similarly.) As a workaround, introduce a new port type for the ASPEED VUART that's identical to PORT_16550A as it had previously been using, but with UART_FCR_R_TRIG_00 instead to set the receive FIFO trigger level to one byte, which (experimentally) seems to avoid the problematic THRE behavior. Fixes:54da3e381c
("serial: 8250_aspeed_vuart: use UPF_IOREMAP to set up register mapping") Tested-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20220211004203.14915-1-zev@bewilderbeest.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
324facd1cc
commit
a603ca60ce
3 changed files with 12 additions and 1 deletions
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@ -487,7 +487,7 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
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port.port.irq = irq_of_parse_and_map(np, 0);
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port.port.handle_irq = aspeed_vuart_handle_irq;
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port.port.iotype = UPIO_MEM;
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port.port.type = PORT_16550A;
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port.port.type = PORT_ASPEED_VUART;
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port.port.uartclk = clk;
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port.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
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| UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_NO_THRE_TEST;
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@ -307,6 +307,14 @@ static const struct serial8250_config uart_config[] = {
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.rxtrig_bytes = {1, 32, 64, 112},
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.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
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},
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[PORT_ASPEED_VUART] = {
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.name = "ASPEED VUART",
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.fifo_size = 16,
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.tx_loadsz = 16,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
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.rxtrig_bytes = {1, 4, 8, 14},
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.flags = UART_CAP_FIFO,
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},
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};
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/* Uart divisor latch read */
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@ -68,6 +68,9 @@
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/* NVIDIA Tegra Combined UART */
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#define PORT_TEGRA_TCU 41
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/* ASPEED AST2x00 virtual UART */
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#define PORT_ASPEED_VUART 42
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/* Intel EG20 */
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#define PORT_PCH_8LINE 44
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#define PORT_PCH_2LINE 45
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