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drm/radeon: Add H/W debugger kfd->kgd functions
This patch adds new interface functions to the kfd2kgd interface file. The new functions allow to perform H/W debugger operations by writing to GPU registers. Signed-off-by: Yair Shachar <yair.shachar@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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3 changed files with 181 additions and 1 deletions
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@ -163,6 +163,19 @@ struct kfd2kgd_calls {
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int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
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unsigned int timeout);
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int (*address_watch_disable)(struct kgd_dev *kgd);
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int (*address_watch_execute)(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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uint32_t cntl_val,
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uint32_t addr_hi,
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uint32_t addr_lo);
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int (*wave_control_execute)(struct kgd_dev *kgd,
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uint32_t gfx_index_val,
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uint32_t sq_cmd);
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uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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unsigned int reg_offset);
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uint16_t (*get_fw_version)(struct kgd_dev *kgd,
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enum kgd_engine_type type);
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};
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@ -149,10 +149,30 @@
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#define KFD_CIK_SDMA_QUEUE_OFFSET 0x200
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#define SQ_IND_INDEX 0x8DE0
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#define SQ_CMD 0x8DEC
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#define SQ_IND_DATA 0x8DE4
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/*
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* The TCP_WATCHx_xxxx addresses that are shown here are in dwords,
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* and that's why they are multiplied by 4
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*/
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#define TCP_WATCH0_ADDR_H (0x32A0*4)
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#define TCP_WATCH1_ADDR_H (0x32A3*4)
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#define TCP_WATCH2_ADDR_H (0x32A6*4)
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#define TCP_WATCH3_ADDR_H (0x32A9*4)
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#define TCP_WATCH0_ADDR_L (0x32A1*4)
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#define TCP_WATCH1_ADDR_L (0x32A4*4)
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#define TCP_WATCH2_ADDR_L (0x32A7*4)
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#define TCP_WATCH3_ADDR_L (0x32AA*4)
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#define TCP_WATCH0_CNTL (0x32A2*4)
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#define TCP_WATCH1_CNTL (0x32A5*4)
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#define TCP_WATCH2_CNTL (0x32A8*4)
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#define TCP_WATCH3_CNTL (0x32AB*4)
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#define CPC_INT_CNTL 0xC2D0
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#define CP_HQD_IQ_RPTR 0xC970u
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#define AQL_ENABLE (1U << 0)
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#define SDMA0_RLC0_RB_CNTL 0xD400u
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#define SDMA_RB_VMID(x) (x << 24)
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#define SDMA0_RLC0_RB_BASE 0xD404u
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@ -186,4 +206,38 @@
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#define SDMA0_CNTL 0xD010
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#define SDMA1_CNTL 0xD810
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enum {
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MAX_TRAPID = 8, /* 3 bits in the bitfield. */
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MAX_WATCH_ADDRESSES = 4
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};
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enum {
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ADDRESS_WATCH_REG_ADDR_HI = 0,
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ADDRESS_WATCH_REG_ADDR_LO,
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ADDRESS_WATCH_REG_CNTL,
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ADDRESS_WATCH_REG_MAX
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};
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enum { /* not defined in the CI/KV reg file */
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ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
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ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
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ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
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/* extend the mask to 26 bits in order to match the low address field */
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ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
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ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
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};
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union TCP_WATCH_CNTL_BITS {
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struct {
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uint32_t mask:24;
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uint32_t vmid:4;
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uint32_t atc:1;
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uint32_t mode:2;
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uint32_t valid:1;
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} bitfields, bits;
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uint32_t u32All;
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signed int i32All;
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float f32All;
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};
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#endif
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@ -34,6 +34,13 @@
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#define CIK_PIPE_PER_MEC (4)
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static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
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TCP_WATCH0_ADDR_H, TCP_WATCH0_ADDR_L, TCP_WATCH0_CNTL,
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TCP_WATCH1_ADDR_H, TCP_WATCH1_ADDR_L, TCP_WATCH1_CNTL,
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TCP_WATCH2_ADDR_H, TCP_WATCH2_ADDR_L, TCP_WATCH2_CNTL,
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TCP_WATCH3_ADDR_H, TCP_WATCH3_ADDR_L, TCP_WATCH3_CNTL
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};
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struct kgd_mem {
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struct radeon_bo *bo;
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uint64_t gpu_addr;
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@ -79,6 +86,18 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
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static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
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static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
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unsigned int timeout);
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static int kgd_address_watch_disable(struct kgd_dev *kgd);
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static int kgd_address_watch_execute(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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uint32_t cntl_val,
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uint32_t addr_hi,
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uint32_t addr_lo);
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static int kgd_wave_control_execute(struct kgd_dev *kgd,
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uint32_t gfx_index_val,
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uint32_t sq_cmd);
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static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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unsigned int reg_offset);
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static const struct kfd2kgd_calls kfd2kgd = {
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.init_gtt_mem_allocation = alloc_gtt_mem,
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@ -96,6 +115,10 @@ static const struct kfd2kgd_calls kfd2kgd = {
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.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_hqd_destroy,
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.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
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.address_watch_disable = kgd_address_watch_disable,
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.address_watch_execute = kgd_address_watch_execute,
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.wave_control_execute = kgd_wave_control_execute,
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.address_watch_get_offset = kgd_address_watch_get_offset,
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.get_fw_version = get_fw_version
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};
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@ -665,6 +688,96 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
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return 0;
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}
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static int kgd_address_watch_disable(struct kgd_dev *kgd)
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{
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union TCP_WATCH_CNTL_BITS cntl;
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unsigned int i;
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cntl.u32All = 0;
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cntl.bitfields.valid = 0;
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cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
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cntl.bitfields.atc = 1;
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/* Turning off this address until we set all the registers */
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for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
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write_register(kgd,
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watchRegs[i * ADDRESS_WATCH_REG_MAX +
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ADDRESS_WATCH_REG_CNTL],
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cntl.u32All);
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return 0;
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}
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static int kgd_address_watch_execute(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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uint32_t cntl_val,
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uint32_t addr_hi,
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uint32_t addr_lo)
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{
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union TCP_WATCH_CNTL_BITS cntl;
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cntl.u32All = cntl_val;
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/* Turning off this watch point until we set all the registers */
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cntl.bitfields.valid = 0;
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write_register(kgd,
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watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
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ADDRESS_WATCH_REG_CNTL],
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cntl.u32All);
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write_register(kgd,
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watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
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ADDRESS_WATCH_REG_ADDR_HI],
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addr_hi);
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write_register(kgd,
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watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
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ADDRESS_WATCH_REG_ADDR_LO],
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addr_lo);
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/* Enable the watch point */
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cntl.bitfields.valid = 1;
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write_register(kgd,
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watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
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ADDRESS_WATCH_REG_CNTL],
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cntl.u32All);
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return 0;
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}
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static int kgd_wave_control_execute(struct kgd_dev *kgd,
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uint32_t gfx_index_val,
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uint32_t sq_cmd)
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{
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struct radeon_device *rdev = get_radeon_device(kgd);
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uint32_t data;
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mutex_lock(&rdev->grbm_idx_mutex);
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write_register(kgd, GRBM_GFX_INDEX, gfx_index_val);
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write_register(kgd, SQ_CMD, sq_cmd);
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/* Restore the GRBM_GFX_INDEX register */
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data = INSTANCE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
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SE_BROADCAST_WRITES;
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write_register(kgd, GRBM_GFX_INDEX, data);
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mutex_unlock(&rdev->grbm_idx_mutex);
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return 0;
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}
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static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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unsigned int reg_offset)
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{
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return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
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}
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static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
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{
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struct radeon_device *rdev = (struct radeon_device *) kgd;
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