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MIPS: mipsregs: Set proper ISA level for virt extensions

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c994a3ec7e ("MIPS: set mips32r5 for virt extensions") setted
some instructions in virt extensions to ISA level mips32r5.

However TLB related vz instructions was leftover, also this
shouldn't be done to a R5 or R6 kernel buid.

Reorg macros to set ISA level as needed when _ASM_SET_VIRT
is called.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang 2024-02-02 18:21:47 +00:00 committed by Thomas Bogendoerfer
parent dd6d29a614
commit a640d6762a
1 changed files with 8 additions and 5 deletions
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13
arch/mips/include/asm/mipsregs.h
View file

@ -2232,7 +2232,14 @@ do { \
_ASM_INSN_IF_MIPS(0x4200000c) \
_ASM_INSN32_IF_MM(0x0000517c)
#else /* !TOOLCHAIN_SUPPORTS_VIRT */
#define _ASM_SET_VIRT ".set\tvirt\n\t"
#if MIPS_ISA_REV >= 5
#define _ASM_SET_VIRT_ISA
#elif defined(CONFIG_64BIT)
#define _ASM_SET_VIRT_ISA ".set\tmips64r5\n\t"
#else
#define _ASM_SET_VIRT_ISA ".set\tmips32r5\n\t"
#endif
#define _ASM_SET_VIRT _ASM_SET_VIRT_ISA ".set\tvirt\n\t"
#define _ASM_SET_MFGC0 _ASM_SET_VIRT
#define _ASM_SET_DMFGC0 _ASM_SET_VIRT
#define _ASM_SET_MTGC0 _ASM_SET_VIRT
@ -2253,7 +2260,6 @@ do { \
({ int __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\tmips32r5\n\t" \
_ASM_SET_MFGC0 \
"mfgc0\t%0, " #source ", %1\n\t" \
_ASM_UNSET_MFGC0 \
@ -2267,7 +2273,6 @@ do { \
({ unsigned long long __res; \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\tmips64r5\n\t" \
_ASM_SET_DMFGC0 \
"dmfgc0\t%0, " #source ", %1\n\t" \
_ASM_UNSET_DMFGC0 \
@ -2281,7 +2286,6 @@ do { \
do { \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\tmips32r5\n\t" \
_ASM_SET_MTGC0 \
"mtgc0\t%z0, " #register ", %1\n\t" \
_ASM_UNSET_MTGC0 \
@ -2294,7 +2298,6 @@ do { \
do { \
__asm__ __volatile__( \
".set\tpush\n\t" \
".set\tmips64r5\n\t" \
_ASM_SET_DMTGC0 \
"dmtgc0\t%z0, " #register ", %1\n\t" \
_ASM_UNSET_DMTGC0 \