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arm64: dts: qcom: sc8180x: switch PCIe QMP PHY to new style of bindings
Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). While we are at it, rename PHY nodes to `phy@`. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-13-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Bjorn Andersson
parent
4a8fbb7c17
commit
a6546460ca
1 changed files with 55 additions and 93 deletions
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@ -1749,23 +1749,28 @@ pcie0: pci@1c00000 {
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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phys = <&pcie0_lane>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie0_phy: phy-wrapper@1c06000 {
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pcie0_phy: phy@1c06000 {
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compatible = "qcom,sc8180x-qmp-pcie-phy";
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reg = <0 0x1c06000 0 0x1c0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0 0x01c06000 0 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"refgen",
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"pipe";
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "phy";
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@ -1774,21 +1779,6 @@ pcie0_phy: phy-wrapper@1c06000 {
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assigned-clock-rates = <100000000>;
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status = "disabled";
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pcie0_lane: phy@1c06200 {
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reg = <0 0x1c06200 0 0x170>, /* tx0 */
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<0 0x1c06400 0 0x200>, /* rx0 */
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<0 0x1c06a00 0 0x1f0>, /* pcs */
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<0 0x1c06600 0 0x170>, /* tx1 */
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<0 0x1c06800 0 0x200>, /* rx1 */
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<0 0x1c06e00 0 0xf4>; /* pcs_com */
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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#phy-cells = <0>;
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};
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};
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pcie3: pci@1c08000 {
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@ -1856,23 +1846,29 @@ pcie3: pci@1c08000 {
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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phys = <&pcie3_lane>;
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phys = <&pcie3_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie3_phy: phy-wrapper@1c0c000 {
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pcie3_phy: phy@1c0c000 {
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compatible = "qcom,sc8180x-qmp-pcie-phy";
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reg = <0 0x1c0c000 0 0x1c0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0 0x01c0c000 0 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_3_CLKREF_CLK>,
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<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_3_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"refgen",
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"pipe";
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#clock-cells = <0>;
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clock-output-names = "pcie_3_pipe_clk";
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_3_PHY_BCR>;
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reset-names = "phy";
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@ -1881,21 +1877,6 @@ pcie3_phy: phy-wrapper@1c0c000 {
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assigned-clock-rates = <100000000>;
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status = "disabled";
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pcie3_lane: phy@1c0c200 {
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reg = <0 0x1c0c200 0 0x170>, /* tx0 */
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<0 0x1c0c400 0 0x200>, /* rx0 */
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<0 0x1c0ca00 0 0x1f0>, /* pcs */
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<0 0x1c0c600 0 0x170>, /* tx1 */
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<0 0x1c0c800 0 0x200>, /* rx1 */
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<0 0x1c0ce00 0 0xf4>; /* pcs_com */
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clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
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clock-names = "pipe0";
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#clock-cells = <0>;
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clock-output-names = "pcie_3_pipe_clk";
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#phy-cells = <0>;
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};
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};
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pcie1: pci@1c10000 {
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@ -1963,23 +1944,29 @@ pcie1: pci@1c10000 {
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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phys = <&pcie1_lane>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie1_phy: phy-wrapper@1c16000 {
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pcie1_phy: phy@1c16000 {
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compatible = "qcom,sc8180x-qmp-pcie-phy";
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reg = <0 0x1c16000 0 0x1c0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0 0x01c16000 0 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_CLKREF_CLK>,
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<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"refgen",
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"pipe";
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#clock-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk";
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "phy";
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@ -1988,21 +1975,6 @@ pcie1_phy: phy-wrapper@1c16000 {
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assigned-clock-rates = <100000000>;
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status = "disabled";
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pcie1_lane: phy@1c0e200 {
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reg = <0 0x1c16200 0 0x170>, /* tx0 */
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<0 0x1c16400 0 0x200>, /* rx0 */
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<0 0x1c16a00 0 0x1f0>, /* pcs */
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<0 0x1c16600 0 0x170>, /* tx1 */
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<0 0x1c16800 0 0x200>, /* rx1 */
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<0 0x1c16e00 0 0xf4>; /* pcs_com */
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
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clock-names = "pipe0";
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#clock-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk";
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#phy-cells = <0>;
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};
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};
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pcie2: pci@1c18000 {
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@ -2070,23 +2042,29 @@ pcie2: pci@1c18000 {
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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phys = <&pcie2_lane>;
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phys = <&pcie2_phy>;
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phy-names = "pciephy";
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status = "disabled";
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};
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pcie2_phy: phy-wrapper@1c1c000 {
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pcie2_phy: phy@1c1c000 {
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compatible = "qcom,sc8180x-qmp-pcie-phy";
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reg = <0 0x1c1c000 0 0x1c0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0 0x01c1c000 0 0x1000>;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_2_CLKREF_CLK>,
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<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "refgen";
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<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
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<&gcc GCC_PCIE_2_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"refgen",
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"pipe";
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#clock-cells = <0>;
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clock-output-names = "pcie_3_pipe_clk";
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#phy-cells = <0>;
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resets = <&gcc GCC_PCIE_2_PHY_BCR>;
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reset-names = "phy";
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@ -2095,22 +2073,6 @@ pcie2_phy: phy-wrapper@1c1c000 {
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assigned-clock-rates = <100000000>;
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status = "disabled";
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pcie2_lane: phy@1c0e200 {
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reg = <0 0x1c1c200 0 0x170>, /* tx0 */
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<0 0x1c1c400 0 0x200>, /* rx0 */
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<0 0x1c1ca00 0 0x1f0>, /* pcs */
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<0 0x1c1c600 0 0x170>, /* tx1 */
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<0 0x1c1c800 0 0x200>, /* rx1 */
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<0 0x1c1ce00 0 0xf4>; /* pcs_com */
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clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
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clock-names = "pipe0";
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#clock-cells = <0>;
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clock-output-names = "pcie_2_pipe_clk";
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#phy-cells = <0>;
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};
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};
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ufs_mem_hc: ufshc@1d84000 {
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