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dmaengine: vdma: Fix race condition in Non-SG mode
When VDMA is configured in Non-sg mode Users can queue descriptors greater than h/w configured frames. Current driver allows the user to queue descriptors upto h/w configured. Which is wrong for non-sg mode configuration. This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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1 changed files with 19 additions and 6 deletions
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@ -209,6 +209,7 @@ struct xilinx_vdma_tx_descriptor {
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* @flush_on_fsync: Flush on Frame sync
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* @desc_pendingcount: Descriptor pending count
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* @ext_addr: Indicates 64 bit addressing is supported by dma channel
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* @desc_submitcount: Descriptor h/w submitted count
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*/
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struct xilinx_vdma_chan {
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struct xilinx_vdma_device *xdev;
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@ -233,6 +234,7 @@ struct xilinx_vdma_chan {
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bool flush_on_fsync;
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u32 desc_pendingcount;
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bool ext_addr;
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u32 desc_submitcount;
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};
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/**
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@ -716,9 +718,10 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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struct xilinx_vdma_tx_segment *segment, *last = NULL;
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int i = 0;
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list_for_each_entry(desc, &chan->pending_list, node) {
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segment = list_first_entry(&desc->segments,
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struct xilinx_vdma_tx_segment, node);
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if (chan->desc_submitcount < chan->num_frms)
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i = chan->desc_submitcount;
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list_for_each_entry(segment, &desc->segments, node) {
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if (chan->ext_addr)
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vdma_desc_write_64(chan,
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XILINX_VDMA_REG_START_ADDRESS_64(i++),
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@ -742,8 +745,17 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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vdma_desc_write(chan, XILINX_VDMA_REG_VSIZE, last->hw.vsize);
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}
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list_splice_tail_init(&chan->pending_list, &chan->active_list);
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chan->desc_pendingcount = 0;
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if (!chan->has_sg) {
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list_del(&desc->node);
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list_add_tail(&desc->node, &chan->active_list);
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chan->desc_submitcount++;
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chan->desc_pendingcount--;
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if (chan->desc_submitcount == chan->num_frms)
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chan->desc_submitcount = 0;
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} else {
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list_splice_tail_init(&chan->pending_list, &chan->active_list);
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chan->desc_pendingcount = 0;
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}
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}
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/**
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@ -927,7 +939,8 @@ static void append_desc_queue(struct xilinx_vdma_chan *chan,
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list_add_tail(&desc->node, &chan->pending_list);
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chan->desc_pendingcount++;
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if (unlikely(chan->desc_pendingcount > chan->num_frms)) {
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if (chan->has_sg &&
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unlikely(chan->desc_pendingcount > chan->num_frms)) {
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dev_dbg(chan->dev, "desc pendingcount is too high\n");
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chan->desc_pendingcount = chan->num_frms;
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}
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