mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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General cleanups for MSM/QCOM for 3.15
Split of the multiplatform support for the Qualcomm SoCs into a mach-qcom while we leave mach-msm as legacy support. Also, some smp and device tree related cleanups. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJS+VymAAoJEF9hYXeAcXzBoEsQAOdV4xhC7qcPZaNfoTytZPNz lQjtb5dJCu3rS8yzcaGlp3B8Eh2A0RpNlh37mtiex28X0oxdsKUco2sRI9e8bZ00 TmVW3eqk2nwEjGly4+22AVUBH2Yqp6eKwzmeeAVC3s9Y7IstjDYNeCBWnOXirXJr VAZ1DWFDkqbihTzdpm6yPxK8b9/zcIqwoDCcNlyv4AS15VvRzSCeJDf8ZWA8235n 44g/knBTeXUpdcTFCdD9jJPReHpVtIRiCxvGxzZ7acQLu05/C7xRx5rOY8LiY0G9 8YYKvr6UuYKsmLg0Z7/kqhcwLMAM+5tNhQ8AlotGIlGbK8PGD9Fq9deIXm/lgjIr NRXuJZFd4APyrkd345kRyoJkz+x21EBpLdOUDJ1RO5L8YPsgbsO60IUijzCoZzYj mcs0h8j98qnub6/2CXEeQf+4DlLYauUMyO8Hd6+5A+IWiYm14ifm6PWHNk2mtVgP tvw0qGEfb3TggzkdMD4c2CU7ANR89LCIS8NNWQEcXRwqWI1PaLZU73aYmQu8QAF5 dQ4/4Q/aZl+JJbo2QszsYlx/4WZ5sCUEnDIRBrZc8MzpPnamoXsLvzplcGJLVyBA jvTKVoE7MV3i+N4iIQD4hiwTOT2Iv0RxnYfhDX4LxKzgkVHU1pwegednnVZakxj1 ktwWQ4v9U/GAqp85oGHn =hwTa -----END PGP SIGNATURE----- Merge tag 'qcom-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/cleanup Merge "General cleanups for MSM/QCOM for 3.15" from Kumar Gala: Split of the multiplatform support for the Qualcomm SoCs into a mach-qcom while we leave mach-msm as legacy support. Also, some smp and device tree related cleanups. * tag 'qcom-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: qcom: Rename various msm prefixed functions to qcom clocksource: qcom: split building of legacy vs multiplatform support ARM: qcom: Split Qualcomm support into legacy and multiplatform clocksource: qcom: Move clocksource code out of mach-msm ARM: msm: kill off hotplug.c ARM: msm: Remove pen_release usage ARM: dts: msm: split out msm8660 and msm8960 soc into dts include Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
a671d255af
25 changed files with 240 additions and 370 deletions
|
@ -1167,6 +1167,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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W: http://www.arm.linux.org.uk/
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S: Maintained
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ARM/QUALCOMM SUPPORT
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M: Kumar Gala <galak@codeaurora.org>
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M: David Brown <davidb@codeaurora.org>
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: arch/arm/mach-qcom/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
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ARM/RADISYS ENP2611 MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -657,9 +657,8 @@ config ARCH_PXA
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help
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Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
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config ARCH_MSM_NODT
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bool "Qualcomm MSM"
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select ARCH_MSM
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config ARCH_MSM
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bool "Qualcomm MSM (non-multiplatform)"
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select ARCH_REQUIRE_GPIOLIB
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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@ -1005,6 +1004,8 @@ source "arch/arm/plat-pxa/Kconfig"
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source "arch/arm/mach-mmp/Kconfig"
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source "arch/arm/mach-qcom/Kconfig"
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source "arch/arm/mach-realview/Kconfig"
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source "arch/arm/mach-rockchip/Kconfig"
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@ -956,7 +956,7 @@ config DEBUG_STI_UART
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config DEBUG_MSM_UART
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bool
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depends on ARCH_MSM
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depends on ARCH_MSM || ARCH_QCOM
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config DEBUG_LL_INCLUDE
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string
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@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
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machine-$(CONFIG_ARCH_ORION5X) += orion5x
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machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
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machine-$(CONFIG_ARCH_PXA) += pxa
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machine-$(CONFIG_ARCH_QCOM) += qcom
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machine-$(CONFIG_ARCH_REALVIEW) += realview
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machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
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machine-$(CONFIG_ARCH_RPC) += rpc
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@ -119,9 +119,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
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kirkwood-ts219-6282.dtb
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dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
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dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
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dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-apq8074-dragonboard.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
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armada-370-mirabox.dtb \
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armada-370-netgear-rn102.dtb \
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@ -233,6 +230,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
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dra7-evm.dtb
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dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
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dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-apq8074-dragonboard.dtb
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dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
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ste-hrefprev60-stuib.dtb \
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ste-hrefprev60-tvk.dtb \
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@ -1,63 +1,6 @@
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/dts-v1/;
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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#include "qcom-msm8660.dtsi"
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/ {
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model = "Qualcomm MSM8660 SURF";
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compatible = "qcom,msm8660-surf", "qcom,msm8660";
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interrupt-parent = <&intc>;
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02080000 0x1000 >,
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< 0x02081000 0x1000 >;
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};
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timer@2000000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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msmgpio: gpio@800000 {
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compatible = "qcom,msm-gpio";
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reg = <0x00800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpio = <173>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8660";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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};
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serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 0x0>;
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clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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};
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63
arch/arm/boot/dts/qcom-msm8660.dtsi
Normal file
63
arch/arm/boot/dts/qcom-msm8660.dtsi
Normal file
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@ -0,0 +1,63 @@
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/dts-v1/;
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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/ {
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model = "Qualcomm MSM8660";
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02080000 0x1000 >,
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< 0x02081000 0x1000 >;
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};
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timer@2000000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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msmgpio: gpio@800000 {
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compatible = "qcom,msm-gpio";
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reg = <0x00800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpio = <173>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8660";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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};
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serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 0x0>;
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clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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};
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@ -1,70 +1,6 @@
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/dts-v1/;
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include "qcom-msm8960.dtsi"
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/ {
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model = "Qualcomm MSM8960 CDP";
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compatible = "qcom,msm8960-cdp", "qcom,msm8960";
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interrupt-parent = <&intc>;
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02000000 0x1000 >,
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< 0x02002000 0x1000 >;
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};
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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msmgpio: gpio@800000 {
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compatible = "qcom,msm-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpio = <150>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800000 0x4000>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8960";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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};
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clock-controller@4000000 {
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compatible = "qcom,mmcc-msm8960";
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reg = <0x4000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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serial@16440000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16440000 0x1000>,
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<0x16400000 0x1000>;
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interrupts = <0 154 0x0>;
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clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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};
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|
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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||||
};
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|
|
70
arch/arm/boot/dts/qcom-msm8960.dtsi
Normal file
70
arch/arm/boot/dts/qcom-msm8960.dtsi
Normal file
|
@ -0,0 +1,70 @@
|
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/dts-v1/;
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||||
|
||||
/include/ "skeleton.dtsi"
|
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|
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
|
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|
||||
/ {
|
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model = "Qualcomm MSM8960";
|
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compatible = "qcom,msm8960";
|
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interrupt-parent = <&intc>;
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|
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intc: interrupt-controller@2000000 {
|
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compatible = "qcom,msm-qgic2";
|
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interrupt-controller;
|
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#interrupt-cells = <3>;
|
||||
reg = < 0x02000000 0x1000 >,
|
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< 0x02002000 0x1000 >;
|
||||
};
|
||||
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
msmgpio: gpio@800000 {
|
||||
compatible = "qcom,msm-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpio = <150>;
|
||||
interrupts = <0 16 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800000 0x4000>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
};
|
||||
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
serial@16440000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <0 154 0x0>;
|
||||
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
};
|
||||
};
|
|
@ -1,50 +1,9 @@
|
|||
config ARCH_MSM
|
||||
bool
|
||||
|
||||
config ARCH_MSM_DT
|
||||
bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
|
||||
select ARCH_MSM
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKSRC_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
help
|
||||
Support for Qualcomm's devicetree based MSM systems.
|
||||
|
||||
if ARCH_MSM
|
||||
|
||||
menu "Qualcomm MSM SoC Selection"
|
||||
depends on ARCH_MSM_DT
|
||||
|
||||
config ARCH_MSM8X60
|
||||
bool "Enable support for MSM8X60"
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select HAVE_SMP
|
||||
select MSM_SCM if SMP
|
||||
select MSM_TIMER
|
||||
|
||||
config ARCH_MSM8960
|
||||
bool "Enable support for MSM8960"
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select HAVE_SMP
|
||||
select MSM_SCM if SMP
|
||||
select MSM_TIMER
|
||||
|
||||
config ARCH_MSM8974
|
||||
bool "Enable support for MSM8974"
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select HAVE_SMP
|
||||
select MSM_SCM if SMP
|
||||
|
||||
endmenu
|
||||
|
||||
choice
|
||||
prompt "Qualcomm MSM SoC Type"
|
||||
default ARCH_MSM7X00A
|
||||
depends on ARCH_MSM_NODT
|
||||
depends on ARCH_MSM
|
||||
|
||||
config ARCH_MSM7X00A
|
||||
bool "MSM7x00A / MSM7x01A"
|
||||
|
@ -54,7 +13,7 @@ config ARCH_MSM7X00A
|
|||
select MACH_TROUT if !MACH_HALIBUT
|
||||
select MSM_PROC_COMM
|
||||
select MSM_SMD
|
||||
select MSM_TIMER
|
||||
select CLKSRC_QCOM
|
||||
select MSM_SMD_PKG3
|
||||
|
||||
config ARCH_MSM7X30
|
||||
|
@ -66,7 +25,7 @@ config ARCH_MSM7X30
|
|||
select MSM_GPIOMUX
|
||||
select MSM_PROC_COMM
|
||||
select MSM_SMD
|
||||
select MSM_TIMER
|
||||
select CLKSRC_QCOM
|
||||
select MSM_VIC
|
||||
|
||||
config ARCH_QSD8X50
|
||||
|
@ -78,7 +37,7 @@ config ARCH_QSD8X50
|
|||
select MSM_GPIOMUX
|
||||
select MSM_PROC_COMM
|
||||
select MSM_SMD
|
||||
select MSM_TIMER
|
||||
select CLKSRC_QCOM
|
||||
select MSM_VIC
|
||||
|
||||
endchoice
|
||||
|
@ -99,7 +58,7 @@ config MSM_VIC
|
|||
bool
|
||||
|
||||
menu "Qualcomm MSM Board Type"
|
||||
depends on ARCH_MSM_NODT
|
||||
depends on ARCH_MSM
|
||||
|
||||
config MACH_HALIBUT
|
||||
depends on ARCH_MSM
|
||||
|
@ -153,7 +112,4 @@ config MSM_GPIOMUX
|
|||
config MSM_SCM
|
||||
bool
|
||||
|
||||
config MSM_TIMER
|
||||
bool
|
||||
|
||||
endif
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
obj-$(CONFIG_MSM_TIMER) += timer.o
|
||||
obj-$(CONFIG_MSM_PROC_COMM) += clock.o
|
||||
|
||||
obj-$(CONFIG_MSM_VIC) += irq-vic.o
|
||||
|
@ -14,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
|
|||
|
||||
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
|
||||
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
|
||||
obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
|
||||
|
||||
CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
|
||||
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
|
||||
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
|
||||
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
|
||||
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
|
||||
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
|
||||
obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
|
||||
obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
|
||||
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
|
||||
|
|
|
@ -24,7 +24,6 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
|
|||
unsigned int mtype, void *caller);
|
||||
|
||||
extern struct smp_operations msm_smp_ops;
|
||||
extern void msm_cpu_die(unsigned int cpu);
|
||||
|
||||
struct msm_mmc_platform_data;
|
||||
|
||||
|
|
|
@ -1,39 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-realview/headsmp.S
|
||||
*
|
||||
* Copyright (c) 2003 ARM Limited
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
/*
|
||||
* MSM specific entry point for secondary CPUs. This provides
|
||||
* a "holding pen" into which all secondary cores are held until we're
|
||||
* ready for them to initialise.
|
||||
*/
|
||||
ENTRY(msm_secondary_startup)
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #15
|
||||
adr r4, 1f
|
||||
ldmia r4, {r5, r6}
|
||||
sub r4, r4, r5
|
||||
add r6, r6, r4
|
||||
pen: ldr r7, [r6]
|
||||
cmp r7, r0
|
||||
bne pen
|
||||
|
||||
/*
|
||||
* we've been released from the holding pen: secondary_stack
|
||||
* should now contain the SVC stack for this core
|
||||
*/
|
||||
b secondary_startup
|
||||
ENDPROC(msm_secondary_startup)
|
||||
|
||||
.align
|
||||
1: .long .
|
||||
.long pen_release
|
|
@ -1,74 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2002 ARM Ltd.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static inline void cpu_enter_lowpower(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void cpu_leave_lowpower(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void platform_do_lowpower(unsigned int cpu)
|
||||
{
|
||||
/* Just enter wfi for now. TODO: Properly shut off the cpu. */
|
||||
for (;;) {
|
||||
/*
|
||||
* here's the WFI
|
||||
*/
|
||||
asm("wfi"
|
||||
:
|
||||
:
|
||||
: "memory", "cc");
|
||||
|
||||
if (pen_release == cpu_logical_map(cpu)) {
|
||||
/*
|
||||
* OK, proper wakeup, we're done
|
||||
*/
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* getting here, means that we have come out of WFI without
|
||||
* having been woken up - this shouldn't happen
|
||||
*
|
||||
* The trouble is, letting people know about this is not really
|
||||
* possible, since we are currently running incoherently, and
|
||||
* therefore cannot safely call printk() or anything else
|
||||
*/
|
||||
pr_debug("CPU%u: spurious wakeup call\n", cpu);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
* Called with IRQs disabled
|
||||
*/
|
||||
void __ref msm_cpu_die(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* we're ready for shutdown now, so do it
|
||||
*/
|
||||
cpu_enter_lowpower();
|
||||
platform_do_lowpower(cpu);
|
||||
|
||||
/*
|
||||
* bring this CPU back into the world of cache
|
||||
* coherency, and then restore interrupts
|
||||
*/
|
||||
cpu_leave_lowpower();
|
||||
}
|
33
arch/arm/mach-qcom/Kconfig
Normal file
33
arch/arm/mach-qcom/Kconfig
Normal file
|
@ -0,0 +1,33 @@
|
|||
config ARCH_QCOM
|
||||
bool "Qualcomm Support" if ARCH_MULTI_V7
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_GIC
|
||||
select CLKSRC_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_SMP
|
||||
select QCOM_SCM if SMP
|
||||
help
|
||||
Support for Qualcomm's devicetree based systems.
|
||||
|
||||
if ARCH_QCOM
|
||||
|
||||
menu "Qualcomm SoC Selection"
|
||||
|
||||
config ARCH_MSM8X60
|
||||
bool "Enable support for MSM8X60"
|
||||
select CLKSRC_QCOM
|
||||
|
||||
config ARCH_MSM8960
|
||||
bool "Enable support for MSM8960"
|
||||
select CLKSRC_QCOM
|
||||
|
||||
config ARCH_MSM8974
|
||||
bool "Enable support for MSM8974"
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
|
||||
endmenu
|
||||
|
||||
config QCOM_SCM
|
||||
bool
|
||||
|
||||
endif
|
5
arch/arm/mach-qcom/Makefile
Normal file
5
arch/arm/mach-qcom/Makefile
Normal file
|
@ -0,0 +1,5 @@
|
|||
obj-y := board.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o
|
||||
|
||||
CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
|
|
@ -1,4 +1,4 @@
|
|||
/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
|
||||
/* Copyright (c) 2010-2014 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -17,10 +17,9 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
extern struct smp_operations qcom_smp_ops;
|
||||
|
||||
static const char * const msm_dt_match[] __initconst = {
|
||||
"qcom,msm8660-fluid",
|
||||
static const char * const qcom_dt_match[] __initconst = {
|
||||
"qcom,msm8660-surf",
|
||||
"qcom,msm8960-cdp",
|
||||
NULL
|
||||
|
@ -31,11 +30,11 @@ static const char * const apq8074_dt_match[] __initconst = {
|
|||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
|
||||
.smp = smp_ops(msm_smp_ops),
|
||||
.dt_compat = msm_dt_match,
|
||||
DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)")
|
||||
.smp = smp_ops(qcom_smp_ops),
|
||||
.dt_compat = qcom_dt_match,
|
||||
MACHINE_END
|
||||
|
||||
DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)")
|
||||
DT_MACHINE_START(APQ_DT, "Qualcomm (Flattened Device Tree)")
|
||||
.dt_compat = apq8074_dt_match,
|
||||
MACHINE_END
|
|
@ -2,6 +2,7 @@
|
|||
* Copyright (C) 2002 ARM Ltd.
|
||||
* All Rights Reserved
|
||||
* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -12,41 +13,37 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "scm-boot.h"
|
||||
#include "common.h"
|
||||
|
||||
#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
|
||||
#define SCSS_CPU1CORE_RESET 0xD80
|
||||
#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
|
||||
|
||||
extern void msm_secondary_startup(void);
|
||||
extern void secondary_startup(void);
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static void __ref qcom_cpu_die(unsigned int cpu)
|
||||
{
|
||||
wfi();
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int get_core_count(void)
|
||||
{
|
||||
/* 1 + the PART[1:0] field of MIDR */
|
||||
return ((read_cpuid_id() >> 4) & 3) + 1;
|
||||
}
|
||||
|
||||
static void msm_secondary_init(unsigned int cpu)
|
||||
static void qcom_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* let the primary processor know we're out of the
|
||||
* pen, then head off into the C entry point
|
||||
*/
|
||||
pen_release = -1;
|
||||
smp_wmb();
|
||||
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
|
@ -57,7 +54,7 @@ static void msm_secondary_init(unsigned int cpu)
|
|||
static void prepare_cold_cpu(unsigned int cpu)
|
||||
{
|
||||
int ret;
|
||||
ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
|
||||
ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
|
||||
SCM_FLAG_COLDBOOT_CPU1);
|
||||
if (ret == 0) {
|
||||
void __iomem *sc1_base_ptr;
|
||||
|
@ -73,9 +70,8 @@ static void prepare_cold_cpu(unsigned int cpu)
|
|||
"address\n");
|
||||
}
|
||||
|
||||
static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
static int cold_boot_done;
|
||||
|
||||
/* Only need to bring cpu out of reset this way once */
|
||||
|
@ -90,17 +86,6 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/*
|
||||
* The secondary processor is waiting to be released from
|
||||
* the holding pen - release it, then wait for it to flag
|
||||
* that it has been released by resetting pen_release.
|
||||
*
|
||||
* Note that "pen_release" is the hardware CPU ID, whereas
|
||||
* "cpu" is Linux's internal ID.
|
||||
*/
|
||||
pen_release = cpu_logical_map(cpu);
|
||||
sync_cache_w(&pen_release);
|
||||
|
||||
/*
|
||||
* Send the secondary CPU a soft interrupt, thereby causing
|
||||
* the boot monitor to read the system wide flags register,
|
||||
|
@ -108,22 +93,13 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
*/
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
smp_rmb();
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return pen_release != -1 ? -ENOSYS : 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -132,7 +108,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
* does not support the ARM SCU, so just set the possible cpu mask to
|
||||
* NR_CPUS.
|
||||
*/
|
||||
static void __init msm_smp_init_cpus(void)
|
||||
static void __init qcom_smp_init_cpus(void)
|
||||
{
|
||||
unsigned int i, ncores = get_core_count();
|
||||
|
||||
|
@ -146,16 +122,16 @@ static void __init msm_smp_init_cpus(void)
|
|||
set_cpu_possible(i, true);
|
||||
}
|
||||
|
||||
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
|
||||
static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
}
|
||||
|
||||
struct smp_operations msm_smp_ops __initdata = {
|
||||
.smp_init_cpus = msm_smp_init_cpus,
|
||||
.smp_prepare_cpus = msm_smp_prepare_cpus,
|
||||
.smp_secondary_init = msm_secondary_init,
|
||||
.smp_boot_secondary = msm_boot_secondary,
|
||||
struct smp_operations qcom_smp_ops __initdata = {
|
||||
.smp_init_cpus = qcom_smp_init_cpus,
|
||||
.smp_prepare_cpus = qcom_smp_prepare_cpus,
|
||||
.smp_secondary_init = qcom_secondary_init,
|
||||
.smp_boot_secondary = qcom_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_die = msm_cpu_die,
|
||||
.cpu_die = qcom_cpu_die,
|
||||
#endif
|
||||
};
|
|
@ -140,3 +140,6 @@ config VF_PIT_TIMER
|
|||
bool
|
||||
help
|
||||
Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
|
||||
|
||||
config CLKSRC_QCOM
|
||||
bool
|
||||
|
|
|
@ -32,6 +32,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o
|
|||
obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
|
||||
obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
|
||||
obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
|
||||
obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
|
||||
|
||||
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
|
||||
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
|
@ -26,10 +26,6 @@
|
|||
#include <linux/of_irq.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define TIMER_MATCH_VAL 0x0000
|
||||
#define TIMER_COUNT_VAL 0x0004
|
||||
#define TIMER_ENABLE 0x0008
|
||||
|
@ -110,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
|
|||
return readl_relaxed(source_base + TIMER_COUNT_VAL);
|
||||
}
|
||||
|
||||
static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
|
||||
{
|
||||
/*
|
||||
* Shift timer count down by a constant due to unreliable lower bits
|
||||
* on some targets.
|
||||
*/
|
||||
return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
|
||||
}
|
||||
|
||||
static struct clocksource msm_clocksource = {
|
||||
.name = "dg_timer",
|
||||
.rating = 300,
|
||||
|
@ -232,7 +219,7 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
|
|||
sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
#ifdef CONFIG_ARCH_QCOM
|
||||
static void __init msm_dt_timer_init(struct device_node *np)
|
||||
{
|
||||
u32 freq;
|
||||
|
@ -285,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np)
|
|||
}
|
||||
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
|
||||
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
|
||||
#endif
|
||||
#else
|
||||
|
||||
static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
|
||||
u32 sts)
|
||||
|
@ -305,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
|
||||
{
|
||||
/*
|
||||
* Shift timer count down by a constant due to unreliable lower bits
|
||||
* on some targets.
|
||||
*/
|
||||
return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
|
||||
}
|
||||
|
||||
void __init msm7x01_timer_init(void)
|
||||
{
|
||||
struct clocksource *cs = &msm_clocksource;
|
||||
|
@ -331,3 +327,4 @@ void __init qsd8x50_timer_init(void)
|
|||
return;
|
||||
msm_timer_init(19200000 / 4, 32, 7, false);
|
||||
}
|
||||
#endif
|
Loading…
Reference in a new issue