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perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL
When counting a FRONTEND event, the MSR_PEBS_FRONTEND is not correctly
set on GNR and MTL p-core.
The umask value for the FRONTEND events is changed on GNR and MTL. The
new umask is missing in the extra_regs[] table.
Add a dedicated intel_gnr_extra_regs[] for GNR and MTL p-core.
Fixes: bc4000fdb0
("perf/x86/intel: Add Granite Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20230615173242.3726364-1-kan.liang@linux.intel.com
This commit is contained in:
parent
b50f26a448
commit
a6742cb90b
1 changed files with 14 additions and 1 deletions
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@ -349,6 +349,16 @@ static struct event_constraint intel_spr_event_constraints[] = {
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EVENT_CONSTRAINT_END
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};
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static struct extra_reg intel_gnr_extra_regs[] __read_mostly = {
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INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
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INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
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INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
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INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
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INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
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EVENT_EXTRA_END
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};
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EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
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EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
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@ -6496,6 +6506,7 @@ __init int intel_pmu_init(void)
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case INTEL_FAM6_SAPPHIRERAPIDS_X:
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case INTEL_FAM6_EMERALDRAPIDS_X:
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x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
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x86_pmu.extra_regs = intel_spr_extra_regs;
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fallthrough;
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case INTEL_FAM6_GRANITERAPIDS_X:
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case INTEL_FAM6_GRANITERAPIDS_D:
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@ -6506,7 +6517,8 @@ __init int intel_pmu_init(void)
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x86_pmu.event_constraints = intel_spr_event_constraints;
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x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
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x86_pmu.extra_regs = intel_spr_extra_regs;
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if (!x86_pmu.extra_regs)
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x86_pmu.extra_regs = intel_gnr_extra_regs;
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x86_pmu.limit_period = spr_limit_period;
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x86_pmu.pebs_ept = 1;
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x86_pmu.pebs_aliases = NULL;
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@ -6650,6 +6662,7 @@ __init int intel_pmu_init(void)
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pmu->pebs_constraints = intel_grt_pebs_event_constraints;
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pmu->extra_regs = intel_grt_extra_regs;
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if (is_mtl(boot_cpu_data.x86_model)) {
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x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_gnr_extra_regs;
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x86_pmu.pebs_latency_data = mtl_latency_data_small;
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extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
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mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
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