mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-27 12:57:53 +00:00
arm64: dts: Add Arm corstone1000 platform support
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Rui Miguel Silva
Sudeep Holla
parent
41e3958475
commit
a69d277460
4 changed files with 248 additions and 0 deletions
|
|
@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju
|
|||
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
|
||||
|
|
|
|||
51
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
Normal file
51
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 or MIT
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro Limited. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "corstone1000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
|
||||
compatible = "arm,corstone1000-fvp";
|
||||
|
||||
smsc: ethernet@4010000 {
|
||||
compatible = "smsc,lan91c111";
|
||||
reg = <0x40100000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <2>;
|
||||
};
|
||||
|
||||
vmmc_v3_3d: fixed_v3_3d {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc_supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sdmmc0: mmc@40300000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x40300000 0x1000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&vmmc_v3_3d>;
|
||||
clocks = <&smbclk>, <&refclk100mhz>;
|
||||
clock-names = "smclk", "apb_pclk";
|
||||
};
|
||||
|
||||
sdmmc1: mmc@50000000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x50000000 0x10000>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
max-frequency = <12000000>;
|
||||
vmmc-supply = <&vmmc_v3_3d>;
|
||||
clocks = <&smbclk>, <&refclk100mhz>;
|
||||
clock-names = "smclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
32
arch/arm64/boot/dts/arm/corstone1000-mps3.dts
Normal file
32
arch/arm64/boot/dts/arm/corstone1000-mps3.dts
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 or MIT
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro Limited. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "corstone1000.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM Corstone1000 FPGA MPS3 board";
|
||||
compatible = "arm,corstone1000-mps3";
|
||||
|
||||
smsc: ethernet@4010000 {
|
||||
compatible = "smsc,lan9220", "smsc,lan9115";
|
||||
reg = <0x40100000 0x10000>;
|
||||
phy-mode = "mii";
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <2>;
|
||||
smsc,irq-push-pull;
|
||||
};
|
||||
|
||||
usb_host: usb@40200000 {
|
||||
compatible = "nxp,usb-isp1763";
|
||||
reg = <0x40200000 0x100000>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-width = <16>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
164
arch/arm64/boot/dts/arm/corstone1000.dtsi
Normal file
164
arch/arm64/boot/dts/arm/corstone1000.dtsi
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 or MIT
|
||||
/*
|
||||
* Copyright (c) 2022, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2022, Linaro Limited. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@88200000 {
|
||||
device_type = "memory";
|
||||
reg = <0x88200000 0x77e00000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1c000000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1c010000 0x1000>,
|
||||
<0x1c02f000 0x2000>,
|
||||
<0x1c04f000 0x1000>,
|
||||
<0x1c06f000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-size = <0x80000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
};
|
||||
|
||||
refclk100mhz: refclk100mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smbclk: refclk24mhzx2 {
|
||||
/* Reference 24MHz clock x 2 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
clock-output-names = "smclk";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
uartclk: uartclk {
|
||||
/* UART clock - 50MHz */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
clock-output-names = "uartclk";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
timer@1a220000 {
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x1a220000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <50000000>;
|
||||
ranges;
|
||||
|
||||
frame@1a230000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x1a230000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@1a510000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1a510000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&refclk100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
uart1: serial@1a520000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1a520000 0x1000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&refclk100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
mhu_hse1: mailbox@1b820000 {
|
||||
compatible = "arm,mhuv2-tx", "arm,primecell";
|
||||
reg = <0x1b820000 0x1000>;
|
||||
clocks = <&refclk100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <2>;
|
||||
arm,mhuv2-protocols = <0 0>;
|
||||
secure-status = "okay"; /* secure-world-only */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mhu_seh1: mailbox@1b830000 {
|
||||
compatible = "arm,mhuv2-rx", "arm,primecell";
|
||||
reg = <0x1b830000 0x1000>;
|
||||
clocks = <&refclk100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <2>;
|
||||
arm,mhuv2-protocols = <0 0>;
|
||||
secure-status = "okay"; /* secure-world-only */
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue