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Merge tag 'amd-drm-next-5.12-2021-01-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

Browse source 
amd-drm-next-5.12-2021-01-20:

amdgpu:
- Fix non-x86 build
- W=1 fixes from Lee Jones
- Enable GPU reset on Navy Flounder
- Kernel doc fixes
- SMU workload profile fixes for APUs
- Display updates
- SR-IOV fixes
- Vangogh SMU feature enablment and bug fixes
- GPU reset support for Vangogh
- Misc cleanups

Conflicts:
	drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

Resolve the conflict by picking the initialization value from amd from
f03e80d2e8 ("drm/amd/display: Initialize stack variable") over the
one Linus picked in 61d791365b ("drm/amd/display: avoid
uninitialized variable warning"). It shouldn't matter.

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210120060951.22600-1-alexander.deucher@amd.com
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This commit is contained in:
Daniel Vetter 2021-01-20 13:08:18 +01:00
commit a6b8720c2f
141 changed files with 1941 additions and 1106 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
MAINTAINERS
View file

@ -907,7 +907,7 @@ AMD KFD
M: Felix Kuehling <Felix.Kuehling@amd.com>
L: amd-gfx@lists.freedesktop.org
S: Supported
T: git git://people.freedesktop.org/~agd5f/linux
T: git https://gitlab.freedesktop.org/agd5f/linux.git
F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
F: drivers/gpu/drm/amd/amdkfd/
F: drivers/gpu/drm/amd/include/cik_structs.h
@ -14821,7 +14821,7 @@ M: Alex Deucher <alexander.deucher@amd.com>
M: Christian König <christian.koenig@amd.com>
L: amd-gfx@lists.freedesktop.org
S: Supported
T: git git://people.freedesktop.org/~agd5f/linux
T: git https://gitlab.freedesktop.org/agd5f/linux.git
F: drivers/gpu/drm/amd/
F: drivers/gpu/drm/radeon/
F: include/uapi/drm/amdgpu_drm.h

2
drivers/gpu/drm/amd/amdgpu/Makefile
View file

@ -56,7 +56,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
amdgpu_fw_attestation.o
amdgpu_fw_attestation.o amdgpu_securedisplay.o
amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o

53
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
View file

@ -112,6 +112,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
union igp_info {
struct atom_integrated_system_info_v1_11 v11;
struct atom_integrated_system_info_v1_12 v12;
struct atom_integrated_system_info_v2_1 v21;
};
union umc_info {
@ -209,24 +210,42 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
if (adev->flags & AMD_IS_APU) {
igp_info = (union igp_info *)
(mode_info->atom_context->bios + data_offset);
switch (crev) {
case 11:
mem_channel_number = igp_info->v11.umachannelnumber;
/* channel width is 64 */
if (vram_width)
*vram_width = mem_channel_number * 64;
mem_type = igp_info->v11.memorytype;
if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
switch (frev) {
case 1:
switch (crev) {
case 11:
case 12:
mem_channel_number = igp_info->v11.umachannelnumber;
if (!mem_channel_number)
mem_channel_number = 1;
/* channel width is 64 */
if (vram_width)
*vram_width = mem_channel_number * 64;
mem_type = igp_info->v11.memorytype;
if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
break;
default:
return -EINVAL;
}
break;
case 12:
mem_channel_number = igp_info->v12.umachannelnumber;
/* channel width is 64 */
if (vram_width)
*vram_width = mem_channel_number * 64;
mem_type = igp_info->v12.memorytype;
if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
case 2:
switch (crev) {
case 1:
case 2:
mem_channel_number = igp_info->v21.umachannelnumber;
if (!mem_channel_number)
mem_channel_number = 1;
/* channel width is 64 */
if (vram_width)
*vram_width = mem_channel_number * 64;
mem_type = igp_info->v21.memorytype;
if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
break;
default:
return -EINVAL;
}
break;
default:
return -EINVAL;

3
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
View file

@ -35,6 +35,7 @@
#include "amdgpu_dm_debugfs.h"
#include "amdgpu_ras.h"
#include "amdgpu_rap.h"
#include "amdgpu_securedisplay.h"
#include "amdgpu_fw_attestation.h"
/**
@ -1669,6 +1670,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
amdgpu_rap_debugfs_init(adev);
amdgpu_securedisplay_debugfs_init(adev);
amdgpu_fw_attestation_debugfs_init(adev);
return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,

7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View file

@ -3119,7 +3119,10 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
*/
adev->gfx_timeout = msecs_to_jiffies(10000);
adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
if (amdgpu_sriov_vf(adev))
adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
else if (amdgpu_passthrough(adev))
adev->compute_timeout = msecs_to_jiffies(60000);
else
adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
@ -4208,6 +4211,8 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH:
break;
default:
goto disabled;

2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -1085,6 +1085,8 @@ static const struct pci_device_id pciidlist[] = {
/* Renoir */
{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
/* Navi12 */
{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},

7
drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
View file

@ -47,10 +47,9 @@ typedef struct FW_ATT_RECORD
uint16_t AttFwIdV2; /* V2 FW ID field */
uint32_t AttFWVersion; /* FW Version */
uint16_t AttFWActiveFunctionID; /* The VF ID (only in VF Attestation Table) */
uint16_t AttSource; /* FW source indicator */
uint16_t RecordValid; /* Indicates whether the record is a valid entry */
uint8_t AttFwTaId; /* Ta ID (only in TA Attestation Table) */
uint8_t Reserved;
uint8_t AttSource; /* FW source indicator */
uint8_t RecordValid; /* Indicates whether the record is a valid entry */
uint32_t AttFwTaId; /* Ta ID (only in TA Attestation Table) */
} FW_ATT_RECORD;
static ssize_t amdgpu_fw_attestation_debugfs_read(struct file *f,

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
View file

@ -209,6 +209,8 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
* amdgpu_ih_decode_iv_helper - decode an interrupt vector
*
* @adev: amdgpu_device pointer
* @ih: ih ring to process
* @entry: IV entry
*
* Decodes the interrupt vector at the current rptr
* position and also advance the position for for Vega10

191
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View file

@ -36,6 +36,7 @@
#include "psp_v12_0.h"
#include "amdgpu_ras.h"
#include "amdgpu_securedisplay.h"
static int psp_sysfs_init(struct amdgpu_device *adev);
static void psp_sysfs_fini(struct amdgpu_device *adev);
@ -1652,6 +1653,175 @@ int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
}
// RAP end
/* securedisplay start */
static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
{
int ret;
/*
* Allocate 16k memory aligned to 4k from Frame Buffer (local
* physical) for sa ta <-> Driver
*/
ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
&psp->securedisplay_context.securedisplay_shared_bo,
&psp->securedisplay_context.securedisplay_shared_mc_addr,
&psp->securedisplay_context.securedisplay_shared_buf);
return ret;
}
static int psp_securedisplay_load(struct psp_context *psp)
{
int ret;
struct psp_gfx_cmd_resp *cmd;
cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
if (!cmd)
return -ENOMEM;
memset(psp->fw_pri_buf, 0, PSP_1_MEG);
memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size);
psp_prep_ta_load_cmd_buf(cmd,
psp->fw_pri_mc_addr,
psp->ta_securedisplay_ucode_size,
psp->securedisplay_context.securedisplay_shared_mc_addr,
PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
if (ret)
goto failed;
psp->securedisplay_context.securedisplay_initialized = true;
psp->securedisplay_context.session_id = cmd->resp.session_id;
mutex_init(&psp->securedisplay_context.mutex);
failed:
kfree(cmd);
return ret;
}
static int psp_securedisplay_unload(struct psp_context *psp)
{
int ret;
struct psp_gfx_cmd_resp *cmd;
cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
if (!cmd)
return -ENOMEM;
psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id);
ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
kfree(cmd);
return ret;
}
static int psp_securedisplay_initialize(struct psp_context *psp)
{
int ret;
struct securedisplay_cmd *securedisplay_cmd;
/*
* TODO: bypass the initialize in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev))
return 0;
if (!psp->adev->psp.ta_securedisplay_ucode_size ||
!psp->adev->psp.ta_securedisplay_start_addr) {
dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
return 0;
}
if (!psp->securedisplay_context.securedisplay_initialized) {
ret = psp_securedisplay_init_shared_buf(psp);
if (ret)
return ret;
}
ret = psp_securedisplay_load(psp);
if (ret)
return ret;
psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
TA_SECUREDISPLAY_COMMAND__QUERY_TA);
ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
if (ret) {
psp_securedisplay_unload(psp);
amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
&psp->securedisplay_context.securedisplay_shared_mc_addr,
&psp->securedisplay_context.securedisplay_shared_buf);
psp->securedisplay_context.securedisplay_initialized = false;
dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
return -EINVAL;
}
if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
}
return 0;
}
static int psp_securedisplay_terminate(struct psp_context *psp)
{
int ret;
/*
* TODO:bypass the terminate in sriov for now
*/
if (amdgpu_sriov_vf(psp->adev))
return 0;
if (!psp->securedisplay_context.securedisplay_initialized)
return 0;
ret = psp_securedisplay_unload(psp);
if (ret)
return ret;
psp->securedisplay_context.securedisplay_initialized = false;
/* free securedisplay shared memory */
amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
&psp->securedisplay_context.securedisplay_shared_mc_addr,
&psp->securedisplay_context.securedisplay_shared_buf);
return ret;
}
int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
{
int ret;
if (!psp->securedisplay_context.securedisplay_initialized)
return -EINVAL;
if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
return -EINVAL;
mutex_lock(&psp->securedisplay_context.mutex);
ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id);
mutex_unlock(&psp->securedisplay_context.mutex);
return ret;
}
/* SECUREDISPLAY end */
static int psp_hw_start(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@ -2126,6 +2296,11 @@ static int psp_load_fw(struct amdgpu_device *adev)
if (ret)
dev_err(psp->adev->dev,
"RAP: Failed to initialize RAP\n");
ret = psp_securedisplay_initialize(psp);
if (ret)
dev_err(psp->adev->dev,
"SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
}
return 0;
@ -2176,6 +2351,7 @@ static int psp_hw_fini(void *handle)
if (psp->adev->psp.ta_fw) {
psp_ras_terminate(psp);
psp_securedisplay_terminate(psp);
psp_rap_terminate(psp);
psp_dtm_terminate(psp);
psp_hdcp_terminate(psp);
@ -2240,6 +2416,11 @@ static int psp_suspend(void *handle)
DRM_ERROR("Failed to terminate rap ta\n");
return ret;
}
ret = psp_securedisplay_terminate(psp);
if (ret) {
DRM_ERROR("Failed to terminate securedisplay ta\n");
return ret;
}
}
ret = psp_asd_unload(psp);
@ -2323,6 +2504,11 @@ static int psp_resume(void *handle)
if (ret)
dev_err(psp->adev->dev,
"RAP: Failed to initialize RAP\n");
ret = psp_securedisplay_initialize(psp);
if (ret)
dev_err(psp->adev->dev,
"SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
}
mutex_unlock(&adev->firmware.mutex);
@ -2629,6 +2815,11 @@ static int parse_ta_bin_descriptor(struct psp_context *psp,
psp->ta_rap_ucode_size = le32_to_cpu(desc->size_bytes);
psp->ta_rap_start_addr = ucode_start_addr;
break;
case TA_FW_TYPE_PSP_SECUREDISPLAY:
psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version);
psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes);
psp->ta_securedisplay_start_addr = ucode_start_addr;
break;
default:
dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
break;

17
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
View file

@ -30,6 +30,7 @@
#include "ta_xgmi_if.h"
#include "ta_ras_if.h"
#include "ta_rap_if.h"
#include "ta_secureDisplay_if.h"
#define PSP_FENCE_BUFFER_SIZE 0x1000
#define PSP_CMD_BUFFER_SIZE 0x1000
@ -40,6 +41,7 @@
#define PSP_HDCP_SHARED_MEM_SIZE 0x4000
#define PSP_DTM_SHARED_MEM_SIZE 0x4000
#define PSP_RAP_SHARED_MEM_SIZE 0x4000
#define PSP_SECUREDISPLAY_SHARED_MEM_SIZE 0x4000
#define PSP_SHARED_MEM_SIZE 0x4000
#define PSP_FW_NAME_LEN 0x24
@ -171,6 +173,15 @@ struct psp_rap_context {
struct mutex mutex;
};
struct psp_securedisplay_context {
bool securedisplay_initialized;
uint32_t session_id;
struct amdgpu_bo *securedisplay_shared_bo;
uint64_t securedisplay_shared_mc_addr;
void *securedisplay_shared_buf;
struct mutex mutex;
};
#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
#define GDDR6_MEM_TRAINING_OFFSET 0x8000
@ -298,12 +309,17 @@ struct psp_context
uint32_t ta_rap_ucode_size;
uint8_t *ta_rap_start_addr;
uint32_t ta_securedisplay_ucode_version;
uint32_t ta_securedisplay_ucode_size;
uint8_t *ta_securedisplay_start_addr;
struct psp_asd_context asd_context;
struct psp_xgmi_context xgmi_context;
struct psp_ras_context ras;
struct psp_hdcp_context hdcp_context;
struct psp_dtm_context dtm_context;
struct psp_rap_context rap_context;
struct psp_securedisplay_context securedisplay_context;
struct mutex mutex;
struct psp_memory_training_context mem_train_ctx;
};
@ -380,6 +396,7 @@ int psp_ras_trigger_error(struct psp_context *psp,
int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
int psp_rlc_autoload_start(struct psp_context *psp);

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View file

@ -846,7 +846,7 @@ static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
dev_warn(adev->dev, "Failed to allow XGMI power down");
if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
dev_warn(adev->dev, "Failed to allow df cstate");
return ret;

176
drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c Normal file
View file

@ -0,0 +1,176 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#include <linux/debugfs.h>
#include <linux/pm_runtime.h>
#include "amdgpu.h"
#include "amdgpu_securedisplay.h"
/**
* DOC: AMDGPU SECUREDISPLAY debugfs test interface
*
* how to use?
* echo opcode <value> > <debugfs_dir>/dri/xxx/securedisplay_test
* eg. echo 1 > <debugfs_dir>/dri/xxx/securedisplay_test
* eg. echo 2 phy_id > <debugfs_dir>/dri/xxx/securedisplay_test
*
* opcode:
* 1：Query whether TA is responding used only for validation pupose
* 2: Send region of Interest and CRC value to I2C. (uint32)phy_id is
* send to determine which DIO scratch register should be used to get
* ROI and receive i2c_buf as the output.
*
* You can refer more detail from header file ta_securedisplay_if.h
*
*/
void psp_securedisplay_parse_resp_status(struct psp_context *psp,
enum ta_securedisplay_status status)
{
switch (status) {
case TA_SECUREDISPLAY_STATUS__SUCCESS:
break;
case TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE:
dev_err(psp->adev->dev, "Secure display: Generic Failure.");
break;
case TA_SECUREDISPLAY_STATUS__INVALID_PARAMETER:
dev_err(psp->adev->dev, "Secure display: Invalid Parameter.");
break;
case TA_SECUREDISPLAY_STATUS__NULL_POINTER:
dev_err(psp->adev->dev, "Secure display: Null Pointer.");
break;
case TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to write to I2C.");
break;
case TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to Read DIO Scratch Register.");
break;
case TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR:
dev_err(psp->adev->dev, "Secure display: Failed to Read CRC");
break;
default:
dev_err(psp->adev->dev, "Secure display: Failed to parse status: %d\n", status);
}
}
void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedisplay_cmd **cmd,
enum ta_securedisplay_command command_id)
{
*cmd = (struct securedisplay_cmd *)psp->securedisplay_context.securedisplay_shared_buf;
memset(*cmd, 0, sizeof(struct securedisplay_cmd));
(*cmd)->status = TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE;
(*cmd)->cmd_id = command_id;
}
static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
struct psp_context *psp = &adev->psp;
struct securedisplay_cmd *securedisplay_cmd;
struct drm_device *dev = adev_to_drm(adev);
uint32_t phy_id;
uint32_t op;
int i;
char str[64];
char i2c_output[256];
int ret;
if (*pos || size > sizeof(str) - 1)
return -EINVAL;
memset(str, 0, sizeof(str));
ret = copy_from_user(str, buf, size);
if (ret)
return -EFAULT;
ret = pm_runtime_get_sync(dev->dev);
if (ret < 0) {
pm_runtime_put_autosuspend(dev->dev);
return ret;
}
if (size < 3)
sscanf(str, "%u ", &op);
else
sscanf(str, "%u %u", &op, &phy_id);
switch (op) {
case 1:
psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
TA_SECUREDISPLAY_COMMAND__QUERY_TA);
ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
if (!ret) {
if (securedisplay_cmd->status == TA_SECUREDISPLAY_STATUS__SUCCESS)
dev_info(adev->dev, "SECUREDISPLAY: query securedisplay TA ret is 0x%X\n",
securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
else
psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
}
break;
case 2:
psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_id;
ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
if (!ret) {
if (securedisplay_cmd->status == TA_SECUREDISPLAY_STATUS__SUCCESS) {
memset(i2c_output, 0, sizeof(i2c_output));
for (i = 0; i < TA_SECUREDISPLAY_I2C_BUFFER_SIZE; i++)
sprintf(i2c_output, "%s 0x%X", i2c_output,
securedisplay_cmd->securedisplay_out_message.send_roi_crc.i2c_buf[i]);
dev_info(adev->dev, "SECUREDISPLAY: I2C buffer out put is :%s\n", i2c_output);
} else {
psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
}
}
break;
default:
dev_err(adev->dev, "Invalid input: %s\n", str);
}
pm_runtime_mark_last_busy(dev->dev);
pm_runtime_put_autosuspend(dev->dev);
return size;
}
static const struct file_operations amdgpu_securedisplay_debugfs_ops = {
.owner = THIS_MODULE,
.read = NULL,
.write = amdgpu_securedisplay_debugfs_write,
.llseek = default_llseek
};
void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
if (!adev->psp.securedisplay_context.securedisplay_initialized)
return;
debugfs_create_file("securedisplay_test", S_IWUSR, adev_to_drm(adev)->primary->debugfs_root,
adev, &amdgpu_securedisplay_debugfs_ops);
#endif
}

36
drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h Normal file
View file

@ -0,0 +1,36 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#ifndef _AMDGPU_SECUREDISPLAY_H
#define _AMDGPU_SECUREDISPLAY_H
#include "amdgpu.h"
#include "ta_secureDisplay_if.h"
void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev);
void psp_securedisplay_parse_resp_status(struct psp_context *psp,
enum ta_securedisplay_status status);
void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedisplay_cmd **cmd,
enum ta_securedisplay_command command_id);
#endif

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
View file

@ -122,6 +122,9 @@ struct ta_firmware_header_v1_0 {
uint32_t ta_dtm_ucode_version;
uint32_t ta_dtm_offset_bytes;
uint32_t ta_dtm_size_bytes;
uint32_t ta_securedisplay_ucode_version;
uint32_t ta_securedisplay_offset_bytes;
uint32_t ta_securedisplay_size_bytes;
};
enum ta_fw_type {
@ -132,6 +135,7 @@ enum ta_fw_type {
TA_FW_TYPE_PSP_HDCP,
TA_FW_TYPE_PSP_DTM,
TA_FW_TYPE_PSP_RAP,
TA_FW_TYPE_PSP_SECUREDISPLAY,
};
struct ta_fw_bin_desc {

1
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
View file

@ -573,6 +573,7 @@ void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
DRM_INFO("clean up the vf2pf work item\n");
flush_delayed_work(&adev->virt.vf2pf_work);
cancel_delayed_work_sync(&adev->virt.vf2pf_work);
adev->virt.vf2pf_update_interval_ms = 0;
}
}

48
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View file

@ -98,6 +98,10 @@
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
@ -159,6 +163,9 @@
#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@ -3323,6 +3330,7 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
{
@ -7191,6 +7199,9 @@ static int gfx_v10_0_hw_init(void *handle)
if (adev->asic_type == CHIP_SIENNA_CICHLID)
gfx_v10_3_program_pbb_mode(adev);
if (adev->asic_type >= CHIP_SIENNA_CICHLID)
gfx_v10_3_set_power_brake_sequence(adev);
return r;
}
@ -7376,8 +7387,16 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex);
clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
switch (adev->asic_type) {
case CHIP_VANGOGH:
clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
break;
default:
clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
break;
}
mutex_unlock(&adev->gfx.gpu_clock_mutex);
amdgpu_gfx_off_ctrl(adev, true);
return clock;
@ -9168,6 +9187,31 @@ static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
}
}
static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
{
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
(0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
(0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
(0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
(0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
(0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
(0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
(0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
(0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
(0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
(0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
}
const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_GFX,

1
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
View file

@ -255,6 +255,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
if (!down_read_trylock(&adev->reset_sem))
return;
amdgpu_virt_fini_data_exchange(adev);
atomic_set(&adev->in_gpu_reset, 1);
do {

1
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
View file

@ -276,6 +276,7 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
if (!down_read_trylock(&adev->reset_sem))
return;
amdgpu_virt_fini_data_exchange(adev);
atomic_set(&adev->in_gpu_reset, 1);
do {

46
drivers/gpu/drm/amd/amdgpu/nv.c
View file

@ -335,6 +335,38 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
return ret;
}
static int nv_asic_mode2_reset(struct amdgpu_device *adev)
{
u32 i;
int ret = 0;
amdgpu_atombios_scratch_regs_engine_hung(adev, true);
/* disable BM */
pci_clear_master(adev->pdev);
amdgpu_device_cache_pci_state(adev->pdev);
ret = amdgpu_dpm_mode2_reset(adev);
if (ret)
dev_err(adev->dev, "GPU mode2 reset failed\n");
amdgpu_device_load_pci_state(adev->pdev);
/* wait for asic to come out of reset */
for (i = 0; i < adev->usec_timeout; i++) {
u32 memsize = adev->nbio.funcs->get_memsize(adev);
if (memsize != 0xffffffff)
break;
udelay(1);
}
amdgpu_atombios_scratch_regs_engine_hung(adev, false);
return ret;
}
static bool nv_asic_supports_baco(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
@ -351,6 +383,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
struct smu_context *smu = &adev->smu;
if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
amdgpu_reset_method == AMD_RESET_METHOD_BACO)
return amdgpu_reset_method;
@ -359,6 +392,8 @@ nv_asic_reset_method(struct amdgpu_device *adev)
amdgpu_reset_method);
switch (adev->asic_type) {
case CHIP_VANGOGH:
return AMD_RESET_METHOD_MODE2;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
@ -376,7 +411,8 @@ static int nv_asic_reset(struct amdgpu_device *adev)
int ret = 0;
struct smu_context *smu = &adev->smu;
if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
switch (nv_asic_reset_method(adev)) {
case AMD_RESET_METHOD_BACO:
dev_info(adev->dev, "BACO reset\n");
ret = smu_baco_enter(smu);
@ -385,9 +421,15 @@ static int nv_asic_reset(struct amdgpu_device *adev)
ret = smu_baco_exit(smu);
if (ret)
return ret;
} else {
break;
case AMD_RESET_METHOD_MODE2:
dev_info(adev->dev, "MODE2 reset\n");
ret = nv_asic_mode2_reset(adev);
break;
default:
dev_info(adev->dev, "MODE1 reset\n");
ret = nv_asic_mode1_reset(adev);
break;
}
return ret;

12
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
View file

@ -92,8 +92,6 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
(uint8_t *)ta_hdr +
le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
adev->psp.ta_dtm_ucode_version =
le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
adev->psp.ta_dtm_ucode_size =
@ -101,6 +99,16 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
adev->psp.ta_dtm_start_addr =
(uint8_t *)adev->psp.ta_hdcp_start_addr +
le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
adev->psp.ta_securedisplay_ucode_version =
le32_to_cpu(ta_hdr->ta_securedisplay_ucode_version);
adev->psp.ta_securedisplay_ucode_size =
le32_to_cpu(ta_hdr->ta_securedisplay_size_bytes);
adev->psp.ta_securedisplay_start_addr =
(uint8_t *)adev->psp.ta_hdcp_start_addr +
le32_to_cpu(ta_hdr->ta_securedisplay_offset_bytes);
adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
}
return 0;

3
drivers/gpu/drm/amd/amdgpu/soc15.c
View file

@ -1204,7 +1204,8 @@ static int soc15_common_early_init(void *handle)
break;
case CHIP_RENOIR:
adev->asic_funcs = &soc15_asic_funcs;
if (adev->pdev->device == 0x1636)
if ((adev->pdev->device == 0x1636) ||
(adev->pdev->device == 0x164c))
adev->apu_flags |= AMD_APU_IS_RENOIR;
else
adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;

154
drivers/gpu/drm/amd/amdgpu/ta_secureDisplay_if.h Normal file
View file

@ -0,0 +1,154 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _TA_SECUREDISPLAY_IF_H
#define _TA_SECUREDISPLAY_IF_H
/** Secure Display related enumerations */
/**********************************************************/
/** @enum ta_securedisplay_command
* Secure Display Command ID
*/
enum ta_securedisplay_command {
/* Query whether TA is responding used only for validation purpose */
TA_SECUREDISPLAY_COMMAND__QUERY_TA = 1,
/* Send region of Interest and CRC value to I2C */
TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC = 2,
/* Maximum Command ID */
TA_SECUREDISPLAY_COMMAND__MAX_ID = 0x7FFFFFFF,
};
/** @enum ta_securedisplay_status
* Secure Display status returns in shared buffer status
*/
enum ta_securedisplay_status {
TA_SECUREDISPLAY_STATUS__SUCCESS = 0x00, /* Success */
TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE = 0x01, /* Generic Failure */
TA_SECUREDISPLAY_STATUS__INVALID_PARAMETER = 0x02, /* Invalid Parameter */
TA_SECUREDISPLAY_STATUS__NULL_POINTER = 0x03, /* Null Pointer*/
TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR = 0x04, /* Fail to Write to I2C */
TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR = 0x05, /*Fail Read DIO Scratch Register*/
TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR = 0x06, /* Fail to Read CRC*/
TA_SECUREDISPLAY_STATUS__MAX = 0x7FFFFFFF,/* Maximum Value for status*/
};
/** @enum ta_securedisplay_max_phy
* Physical ID number to use for reading corresponding DIO Scratch register for ROI
*/
enum ta_securedisplay_max_phy {
TA_SECUREDISPLAY_PHY0 = 0,
TA_SECUREDISPLAY_PHY1 = 1,
TA_SECUREDISPLAY_PHY2 = 2,
TA_SECUREDISPLAY_PHY3 = 3,
TA_SECUREDISPLAY_MAX_PHY = 4,
};
/** @enum ta_securedisplay_ta_query_cmd_ret
* A predefined specific reteurn value which is 0xAB only used to validate
* communication to Secure Display TA is functional.
* This value is used to validate whether TA is responding successfully
*/
enum ta_securedisplay_ta_query_cmd_ret {
/* This is a value to validate if TA is loaded successfully */
TA_SECUREDISPLAY_QUERY_CMD_RET = 0xAB,
};
/** @enum ta_securedisplay_buffer_size
* I2C Buffer size which contains 8 bytes of ROI (X start, X end, Y start, Y end)
* and 6 bytes of CRC( R,G,B) and 1 byte for physical ID
*/
enum ta_securedisplay_buffer_size {
/* 15 bytes = 8 byte (ROI) + 6 byte(CRC) + 1 byte(phy_id) */
TA_SECUREDISPLAY_I2C_BUFFER_SIZE = 15,
};
/** Input/output structures for Secure Display commands */
/**********************************************************/
/**
* Input structures
*/
/** @struct ta_securedisplay_send_roi_crc_input
* Physical ID to determine which DIO scratch register should be used to get ROI
*/
struct ta_securedisplay_send_roi_crc_input {
uint32_t phy_id; /* Physical ID */
};
/** @union ta_securedisplay_cmd_input
* Input buffer
*/
union ta_securedisplay_cmd_input {
/* send ROI and CRC input buffer format */
struct ta_securedisplay_send_roi_crc_input send_roi_crc;
uint32_t reserved[4];
};
/**
* Output structures
*/
/** @struct ta_securedisplay_query_ta_output
* Output buffer format for query TA whether TA is responding used only for validation purpose
*/
struct ta_securedisplay_query_ta_output {
/* return value from TA when it is queried for validation purpose only */
uint32_t query_cmd_ret;
};
/** @struct ta_securedisplay_send_roi_crc_output
* Output buffer format for send ROI CRC command which will pass I2c buffer created inside TA
* and used to write to I2C used only for validation purpose
*/
struct ta_securedisplay_send_roi_crc_output {
uint8_t i2c_buf[TA_SECUREDISPLAY_I2C_BUFFER_SIZE]; /* I2C buffer */
uint8_t reserved;
};
/** @union ta_securedisplay_cmd_output
* Output buffer
*/
union ta_securedisplay_cmd_output {
/* Query TA output buffer format used only for validation purpose*/
struct ta_securedisplay_query_ta_output query_ta;
/* Send ROI CRC output buffer format used only for validation purpose */
struct ta_securedisplay_send_roi_crc_output send_roi_crc;
uint32_t reserved[4];
};
/** @struct securedisplay_cmd
* Secure Display Command which is shared buffer memory
*/
struct securedisplay_cmd {
uint32_t cmd_id; /* +0 Bytes Command ID */
enum ta_securedisplay_status status; /* +4 Bytes Status of Secure Display TA */
uint32_t reserved[2]; /* +8 Bytes Reserved */
union ta_securedisplay_cmd_input securedisplay_in_message; /* +16 Bytes Input Buffer */
union ta_securedisplay_cmd_output securedisplay_out_message;/* +32 Bytes Output Buffer */
/**@note Total 48 Bytes */
};
#endif //_TA_SECUREDISPLAY_IF_H

5
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
View file

@ -88,7 +88,7 @@ static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
* vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
*
* @adev: amdgpu_device pointer
* @ih: amdgpu_ih_ring pointet
* @ih: amdgpu_ih_ring pointer
* @enable: true - enable the interrupts, false - disable the interrupts
*
* Toggle the interrupt ring buffer (VEGA20)
@ -367,6 +367,7 @@ static void vega20_ih_irq_disable(struct amdgpu_device *adev)
* vega20_ih_get_wptr - get the IH ring buffer wptr
*
* @adev: amdgpu_device pointer
* @ih: amdgpu_ih_ring pointer
*
* Get the IH ring buffer wptr from either the register
* or the writeback memory buffer (VEGA20). Also check for
@ -414,6 +415,7 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
* vega20_ih_irq_rearm - rearm IRQ if lost
*
* @adev: amdgpu_device pointer
* @ih: amdgpu_ih_ring pointer
*
*/
static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
@ -439,6 +441,7 @@ static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
* vega20_ih_set_rptr - set the IH ring buffer rptr
*
* @adev: amdgpu_device pointer
* @ih: amdgpu_ih_ring pointer
*
* Set the IH ring buffer rptr.
*/

11
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
View file

@ -1040,11 +1040,14 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
(struct crat_subtype_iolink *)sub_type_hdr);
if (ret < 0)
return ret;
crat_table->length += (sub_type_hdr->length * entries);
crat_table->total_entries += entries;
sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
sub_type_hdr->length * entries);
if (entries) {
crat_table->length += (sub_type_hdr->length * entries);
crat_table->total_entries += entries;
sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
sub_type_hdr->length * entries);
}
#else
pr_info("IO link not available for non x86 platforms\n");
#endif

152
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -938,41 +938,6 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
}
#endif
#ifdef CONFIG_DEBUG_FS
static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
{
dm->crc_win_x_start_property =
drm_property_create_range(adev_to_drm(dm->adev),
DRM_MODE_PROP_ATOMIC,
"AMD_CRC_WIN_X_START", 0, U16_MAX);
if (!dm->crc_win_x_start_property)
return -ENOMEM;
dm->crc_win_y_start_property =
drm_property_create_range(adev_to_drm(dm->adev),
DRM_MODE_PROP_ATOMIC,
"AMD_CRC_WIN_Y_START", 0, U16_MAX);
if (!dm->crc_win_y_start_property)
return -ENOMEM;
dm->crc_win_x_end_property =
drm_property_create_range(adev_to_drm(dm->adev),
DRM_MODE_PROP_ATOMIC,
"AMD_CRC_WIN_X_END", 0, U16_MAX);
if (!dm->crc_win_x_end_property)
return -ENOMEM;
dm->crc_win_y_end_property =
drm_property_create_range(adev_to_drm(dm->adev),
DRM_MODE_PROP_ATOMIC,
"AMD_CRC_WIN_Y_END", 0, U16_MAX);
if (!dm->crc_win_y_end_property)
return -ENOMEM;
return 0;
}
#endif
static int amdgpu_dm_init(struct amdgpu_device *adev)
{
struct dc_init_data init_data;
@ -1119,10 +1084,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
dc_init_callbacks(adev->dm.dc, &init_params);
}
#endif
#ifdef CONFIG_DEBUG_FS
if (create_crtc_crc_properties(&adev->dm))
DRM_ERROR("amdgpu: failed to create crc property.\n");
#endif
if (amdgpu_dm_initialize_drm_device(adev)) {
DRM_ERROR(
@ -1816,6 +1777,11 @@ static int dm_suspend(void *handle)
if (amdgpu_in_reset(adev)) {
mutex_lock(&dm->dc_lock);
#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_allow_idle_optimizations(adev->dm.dc, false);
#endif
dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
@ -5383,64 +5349,12 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
state->crc_src = cur->crc_src;
state->cm_has_degamma = cur->cm_has_degamma;
state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
#ifdef CONFIG_DEBUG_FS
state->crc_window = cur->crc_window;
#endif
/* TODO Duplicate dc_stream after objects are stream object is flattened */
return &state->base;
}
#ifdef CONFIG_DEBUG_FS
static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state,
struct drm_property *property,
uint64_t val)
{
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_crtc_state *dm_new_state =
to_dm_crtc_state(crtc_state);
if (property == adev->dm.crc_win_x_start_property)
dm_new_state->crc_window.x_start = val;
else if (property == adev->dm.crc_win_y_start_property)
dm_new_state->crc_window.y_start = val;
else if (property == adev->dm.crc_win_x_end_property)
dm_new_state->crc_window.x_end = val;
else if (property == adev->dm.crc_win_y_end_property)
dm_new_state->crc_window.y_end = val;
else
return -EINVAL;
return 0;
}
static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
const struct drm_crtc_state *state,
struct drm_property *property,
uint64_t *val)
{
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_crtc_state *dm_state =
to_dm_crtc_state(state);
if (property == adev->dm.crc_win_x_start_property)
*val = dm_state->crc_window.x_start;
else if (property == adev->dm.crc_win_y_start_property)
*val = dm_state->crc_window.y_start;
else if (property == adev->dm.crc_win_x_end_property)
*val = dm_state->crc_window.x_end;
else if (property == adev->dm.crc_win_y_end_property)
*val = dm_state->crc_window.y_end;
else
return -EINVAL;
return 0;
}
#endif
static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
{
enum dc_irq_source irq_source;
@ -5483,6 +5397,10 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
return -EBUSY;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (amdgpu_in_reset(adev))
return 0;
mutex_lock(&dm->dc_lock);
if (enable)
@ -5499,6 +5417,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
mutex_unlock(&dm->dc_lock);
#endif
return 0;
}
@ -5527,10 +5446,6 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
.enable_vblank = dm_enable_vblank,
.disable_vblank = dm_disable_vblank,
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
#ifdef CONFIG_DEBUG_FS
.atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
.atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
#endif
};
static enum drm_connector_status
@ -6746,25 +6661,6 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
return 0;
}
#ifdef CONFIG_DEBUG_FS
static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
struct amdgpu_crtc *acrtc)
{
drm_object_attach_property(&acrtc->base.base,
dm->crc_win_x_start_property,
0);
drm_object_attach_property(&acrtc->base.base,
dm->crc_win_y_start_property,
0);
drm_object_attach_property(&acrtc->base.base,
dm->crc_win_x_end_property,
0);
drm_object_attach_property(&acrtc->base.base,
dm->crc_win_y_end_property,
0);
}
#endif
static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
struct drm_plane *plane,
uint32_t crtc_index)
@ -6812,9 +6708,7 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
true, MAX_COLOR_LUT_ENTRIES);
drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
#ifdef CONFIG_DEBUG_FS
attach_crtc_crc_properties(dm, acrtc);
#endif
return 0;
fail:
@ -8451,7 +8345,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
*/
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
bool configure_crc = false;
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
@ -8461,27 +8354,20 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
dc_stream_retain(dm_new_crtc_state->stream);
acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
manage_dm_interrupts(adev, acrtc, true);
}
if (IS_ENABLED(CONFIG_DEBUG_FS) && new_crtc_state->active &&
amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
#ifdef CONFIG_DEBUG_FS
/**
* Frontend may have changed so reapply the CRC capture
* settings for the stream.
*/
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {
if (!old_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))
configure_crc = true;
} else {
if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
configure_crc = true;
}
if (configure_crc)
if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
amdgpu_dm_crtc_configure_crc_source(
crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);
crtc, dm_new_crtc_state,
dm_new_crtc_state->crc_src);
}
#endif
}
}

47
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
View file

@ -58,10 +58,10 @@
/* Forward declarations */
struct amdgpu_device;
struct drm_device;
struct amdgpu_dm_irq_handler_data;
struct dc;
struct amdgpu_bo;
struct dmub_srv;
struct dc_plane_state;
struct common_irq_params {
struct amdgpu_device *adev;
@ -337,38 +337,12 @@ struct amdgpu_display_manager {
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
/**
* @active_vblank_irq_count
* @active_vblank_irq_count:
*
* number of currently active vblank irqs
*/
uint32_t active_vblank_irq_count;
#ifdef CONFIG_DEBUG_FS
/**
* @crc_win_x_start_property:
*
* X start of the crc calculation window
*/
struct drm_property *crc_win_x_start_property;
/**
* @crc_win_y_start_property:
*
* Y start of the crc calculation window
*/
struct drm_property *crc_win_y_start_property;
/**
* @crc_win_x_end_property:
*
* X end of the crc calculation window
*/
struct drm_property *crc_win_x_end_property;
/**
* @crc_win_y_end_property:
*
* Y end of the crc calculation window
*/
struct drm_property *crc_win_y_end_property;
#endif
/**
* @mst_encoders:
*
@ -445,25 +419,11 @@ struct amdgpu_dm_connector {
extern const struct amdgpu_ip_block_version dm_ip_block;
struct amdgpu_framebuffer;
struct amdgpu_display_manager;
struct dc_validation_set;
struct dc_plane_state;
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *dc_state;
};
#ifdef CONFIG_DEBUG_FS
struct crc_rec {
uint16_t x_start;
uint16_t y_start;
uint16_t x_end;
uint16_t y_end;
};
#endif
struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream_state *stream;
@ -486,9 +446,6 @@ struct dm_crtc_state {
struct dc_info_packet vrr_infopacket;
int abm_level;
#ifdef CONFIG_DEBUG_FS
struct crc_rec crc_window;
#endif
};
#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)

54
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
View file

@ -81,41 +81,6 @@ const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
return pipe_crc_sources;
}
static void amdgpu_dm_set_crc_window_default(struct dm_crtc_state *dm_crtc_state)
{
dm_crtc_state->crc_window.x_start = 0;
dm_crtc_state->crc_window.y_start = 0;
dm_crtc_state->crc_window.x_end = 0;
dm_crtc_state->crc_window.y_end = 0;
}
bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
{
bool ret = true;
if ((dm_crtc_state->crc_window.x_start != 0) ||
(dm_crtc_state->crc_window.y_start != 0) ||
(dm_crtc_state->crc_window.x_end != 0) ||
(dm_crtc_state->crc_window.y_end != 0))
ret = false;
return ret;
}
bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
struct dm_crtc_state *dm_old_crtc_state)
{
bool ret = false;
if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) ||
(dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) ||
(dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) ||
(dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
ret = true;
return ret;
}
int
amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
size_t *values_cnt)
@ -140,7 +105,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
struct dc_stream_state *stream_state = dm_crtc_state->stream;
bool enable = amdgpu_dm_is_valid_crc_source(source);
int ret = 0;
struct crc_params *crc_window = NULL, tmp_window;
/* Configuration will be deferred to stream enable. */
if (!stream_state)
@ -150,24 +114,8 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
/* Enable CRTC CRC generation if necessary. */
if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
if (!enable)
amdgpu_dm_set_crc_window_default(dm_crtc_state);
if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
crc_window = &tmp_window;
tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
}
if (!dc_stream_configure_crc(stream_state->ctx->dc,
stream_state, crc_window, enable, enable)) {
stream_state, NULL, enable, enable)) {
ret = -EINVAL;
goto unlock;
}

5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
View file

@ -46,13 +46,10 @@ static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source
}
/* amdgpu_dm_crc.c */
bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
struct dm_crtc_state *dm_old_crtc_state);
#ifdef CONFIG_DEBUG_FS
int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
struct dm_crtc_state *dm_crtc_state,
enum amdgpu_dm_pipe_crc_source source);
#ifdef CONFIG_DEBUG_FS
int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
const char *src_name,

4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View file

@ -691,7 +691,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
return size;
}
/**
/*
* Returns the DMCUB tracebuffer contents.
* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
*/
@ -735,7 +735,7 @@ static int dmub_tracebuffer_show(struct seq_file *m, void *data)
return 0;
}
/**
/*
* Returns the DMCUB firmware state contents.
* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
*/

9
drivers/gpu/drm/amd/display/dc/basics/conversion.c
View file

@ -73,12 +73,9 @@ uint16_t fixed_point_to_int_frac(
return result;
}
/**
* convert_float_matrix
* This converts a double into HW register spec defined format S2D13.
* @param :
* @return None
*/
/*
* convert_float_matrix - This converts a double into HW register spec defined format S2D13.
*/
void convert_float_matrix(
uint16_t *matrix,
struct fixed31_32 *flt,

20
drivers/gpu/drm/amd/display/dc/basics/dc_common.c
View file

@ -49,20 +49,24 @@ bool is_rgb_cspace(enum dc_color_space output_color_space)
}
}
bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
return true;
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))
return true;
if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))
return true;
return false;
}
bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
return true;
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))
return true;
if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))
return true;
return false;
}
@ -71,9 +75,13 @@ bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
return true;
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))
return true;
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))
return true;
if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))
return true;
if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))
return true;
return false;
}

4
drivers/gpu/drm/amd/display/dc/basics/dc_common.h
View file

@ -30,9 +30,9 @@
bool is_rgb_cspace(enum dc_color_space output_color_space);
bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

119
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
View file

@ -911,11 +911,11 @@ static enum bp_result get_ss_info_from_tbl(
* ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1,
* there is only one entry for each signal /ss id. However, there is
* no planning of supporting multiple spread Sprectum entry for EverGreen
* @param [in] this
* @param [in] signal, ASSignalType to be converted to info index
* @param [in] index, number of entries that match the converted info index
* @param [out] ss_info, sprectrum information structure,
* @return Bios parser result code
* @dcb: pointer to the DC BIOS
* @signal: ASSignalType to be converted to info index
* @index: number of entries that match the converted info index
* @ss_info: sprectrum information structure,
* return: Bios parser result code
*/
static enum bp_result bios_parser_get_spread_spectrum_info(
struct dc_bios *dcb,
@ -985,10 +985,10 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
* There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or
* SS_Info.
*
* @param this
* @param id, spread sprectrum info index
* @param pSSinfo, sprectrum information structure,
* @return Bios parser result code
* @bp: pointer to the BIOS parser
* @id: spread sprectrum info index
* @ss_info: sprectrum information structure,
* return: BIOS parser result code
*/
static enum bp_result get_ss_info_from_tbl(
struct bios_parser *bp,
@ -1011,9 +1011,10 @@ static enum bp_result get_ss_info_from_tbl(
* from the VBIOS
* There will not be multiple entry for Ver 2.1
*
* @param id, spread sprectrum info index
* @param pSSinfo, sprectrum information structure,
* @return Bios parser result code
* @bp: pointer to the Bios parser
* @id: spread sprectrum info index
* @info: sprectrum information structure,
* return: Bios parser result code
*/
static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
struct bios_parser *bp,
@ -1076,9 +1077,10 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
* of entries that matches the id
* for, the SS_Info table, there should not be more than 1 entry match.
*
* @param [in] id, spread sprectrum id
* @param [out] pSSinfo, sprectrum information structure,
* @return Bios parser result code
* @bp: pointer to the Bios parser
* @id: spread sprectrum id
* @ss_info: sprectrum information structure,
* return: Bios parser result code
*/
static enum bp_result get_ss_info_from_ss_info_table(
struct bios_parser *bp,
@ -1451,16 +1453,14 @@ static enum bp_result get_embedded_panel_info_v1_3(
}
/**
* bios_parser_get_encoder_cap_info
* bios_parser_get_encoder_cap_info - get encoder capability
* information of input object id
*
* @brief
* Get encoder capability information of input object id
*
* @param object_id, Object id
* @param object_id, encoder cap information structure
*
* @return Bios parser result code
* @dcb: pointer to the DC BIOS
* @object_id: object id
* @info: encoder cap information structure
*
* return: Bios parser result code
*/
static enum bp_result bios_parser_get_encoder_cap_info(
struct dc_bios *dcb,
@ -1490,17 +1490,12 @@ static enum bp_result bios_parser_get_encoder_cap_info(
}
/**
* get_encoder_cap_record
* get_encoder_cap_record - Get encoder cap record for the object
*
* @brief
* Get encoder cap record for the object
*
* @param object, ATOM object
*
* @return atom encoder cap record
*
* @note
* search all records to find the ATOM_ENCODER_CAP_RECORD_V2 record
* @bp: pointer to the BIOS parser
* @object: ATOM object
* return: atom encoder cap record
* note: search all records to find the ATOM_ENCODER_CAP_RECORD_V2 record
*/
static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
struct bios_parser *bp,
@ -1557,8 +1552,9 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
* Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from
* the VBIOS that match the SSid (to be converted from signal)
*
* @param[in] signal, ASSignalType to be converted to SSid
* @return number of SS Entry that match the signal
* @dcb: pointer to the DC BIOS
* @signal: ASSignalType to be converted to SSid
* return: number of SS Entry that match the signal
*/
static uint32_t bios_parser_get_ss_entry_number(
struct dc_bios *dcb,
@ -1608,10 +1604,10 @@ static uint32_t bios_parser_get_ss_entry_number(
* get_ss_entry_number_from_ss_info_tbl
* Get Number of spread spectrum entry from the SS_Info table from the VBIOS.
*
* @note There can only be one entry for each id for SS_Info Table
*
* @param [in] id, spread spectrum id
* @return number of SS Entry that match the id
* @bp: pointer to the BIOS parser
* @id: spread spectrum id
* return: number of SS Entry that match the id
* note: There can only be one entry for each id for SS_Info Table
*/
static uint32_t get_ss_entry_number_from_ss_info_tbl(
struct bios_parser *bp,
@ -1679,8 +1675,9 @@ static uint32_t get_ss_entry_number_from_ss_info_tbl(
* There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or
* SS_Info.
*
* @param id, spread sprectrum info index
* @return Bios parser result code
* @bp: pointer to the BIOS parser
* @id: spread sprectrum info index
* return: Bios parser result code
*/
static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id)
{
@ -1696,8 +1693,9 @@ static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id)
* Ver 2.1 from the VBIOS
* There will not be multiple entry for Ver 2.1
*
* @param id, spread sprectrum info index
* @return number of SS Entry that match the id
* @bp: pointer to the BIOS parser
* @id: spread sprectrum info index
* return: number of SS Entry that match the id
*/
static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
struct bios_parser *bp,
@ -1731,8 +1729,9 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
* Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of
* the VBIOS that matches id
*
* @param[in] id, spread sprectrum id
* @return number of SS Entry that match the id
* @bp: pointer to the BIOS parser
* @id: spread sprectrum id
* return: number of SS Entry that match the id
*/
static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
struct bios_parser *bp,
@ -1767,10 +1766,11 @@ static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
* bios_parser_get_gpio_pin_info
* Get GpioPin information of input gpio id
*
* @param gpio_id, GPIO ID
* @param info, GpioPin information structure
* @return Bios parser result code
* @note
* @dcb: pointer to the DC BIOS
* @gpio_id: GPIO ID
* @info: GpioPin information structure
* return: Bios parser result code
* note:
* to get the GPIO PIN INFO, we need:
* 1. get the GPIO_ID from other object table, see GetHPDInfo()
* 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA
@ -2197,13 +2197,10 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
}
/**
* bios_parser_set_scratch_critical_state
*
* @brief
* update critical state bit in VBIOS scratch register
*
* @param
* bool - to set or reset state
* bios_parser_set_scratch_critical_state - update critical state
* bit in VBIOS scratch register
* @dcb: pointer to the DC BIOS
* @state: set or reset state
*/
static void bios_parser_set_scratch_critical_state(
struct dc_bios *dcb,
@ -2222,7 +2219,7 @@ static void bios_parser_set_scratch_critical_state(
* bios_parser *bp - [in]BIOS parser handler to get master data table
* integrated_info *info - [out] store and output integrated info
*
* @return
* return:
* enum bp_result - BP_RESULT_OK if information is available,
* BP_RESULT_BADBIOSTABLE otherwise.
*/
@ -2372,7 +2369,7 @@ static enum bp_result get_integrated_info_v8(
* bios_parser *bp - [in]BIOS parser handler to get master data table
* integrated_info *info - [out] store and output integrated info
*
* @return
* return:
* enum bp_result - BP_RESULT_OK if information is available,
* BP_RESULT_BADBIOSTABLE otherwise.
*/
@ -2509,7 +2506,7 @@ static enum bp_result get_integrated_info_v9(
* bios_parser *bp - [in]BIOS parser handler to get master data table
* integrated_info *info - [out] store and output integrated info
*
* @return
* return:
* enum bp_result - BP_RESULT_OK if information is available,
* BP_RESULT_BADBIOSTABLE otherwise.
*/
@ -2585,7 +2582,7 @@ static struct integrated_info *bios_parser_create_integrated_info(
return NULL;
}
enum bp_result update_slot_layout_info(
static enum bp_result update_slot_layout_info(
struct dc_bios *dcb,
unsigned int i,
struct slot_layout_info *slot_layout_info,
@ -2689,7 +2686,7 @@ enum bp_result update_slot_layout_info(
}
enum bp_result get_bracket_layout_record(
static enum bp_result get_bracket_layout_record(
struct dc_bios *dcb,
unsigned int bracket_layout_id,
struct slot_layout_info *slot_layout_info)

29
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View file

@ -485,10 +485,11 @@ static struct atom_hpd_int_record *get_hpd_record(
* bios_parser_get_gpio_pin_info
* Get GpioPin information of input gpio id
*
* @param gpio_id, GPIO ID
* @param info, GpioPin information structure
* @return Bios parser result code
* @note
* @dcb: pointer to the DC BIOS
* @gpio_id: GPIO ID
* @info: GpioPin information structure
* return: Bios parser result code
* note:
* to get the GPIO PIN INFO, we need:
* 1. get the GPIO_ID from other object table, see GetHPDInfo()
* 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
@ -801,11 +802,11 @@ static enum bp_result get_ss_info_v4_2(
* ver 3.1,
* there is only one entry for each signal /ss id. However, there is
* no planning of supporting multiple spread Sprectum entry for EverGreen
* @param [in] this
* @param [in] signal, ASSignalType to be converted to info index
* @param [in] index, number of entries that match the converted info index
* @param [out] ss_info, sprectrum information structure,
* @return Bios parser result code
* @dcb: pointer to the DC BIOS
* @signal: ASSignalType to be converted to info index
* @index: number of entries that match the converted info index
* @ss_info: sprectrum information structure,
* return: Bios parser result code
*/
static enum bp_result bios_parser_get_spread_spectrum_info(
struct dc_bios *dcb,
@ -1196,13 +1197,11 @@ static bool bios_parser_is_accelerated_mode(
}
/**
* bios_parser_set_scratch_critical_state
* bios_parser_set_scratch_critical_state - update critical state bit
* in VBIOS scratch register
*
* @brief
* update critical state bit in VBIOS scratch register
*
* @param
* bool - to set or reset state
* @dcb: pointer to the DC BIO
* @state: set or reset state
*/
static void bios_parser_set_scratch_critical_state(
struct dc_bios *dcb,

20
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
View file

@ -114,18 +114,14 @@ bool dal_cmd_table_helper_controller_id_to_atom(
}
/**
* translate_transmitter_bp_to_atom
*
* @brief
* Translate the Transmitter to the corresponding ATOM BIOS value
*
* @param
* input transmitter
* output digitalTransmitter
* // =00: Digital Transmitter1 ( UNIPHY linkAB )
* // =01: Digital Transmitter2 ( UNIPHY linkCD )
* // =02: Digital Transmitter3 ( UNIPHY linkEF )
*/
* translate_transmitter_bp_to_atom - Translate the Transmitter to the
* corresponding ATOM BIOS value
* @t: transmitter
* returns: output digitalTransmitter
* // =00: Digital Transmitter1 ( UNIPHY linkAB )
* // =01: Digital Transmitter2 ( UNIPHY linkCD )
* // =02: Digital Transmitter3 ( UNIPHY linkEF )
*/
uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
enum transmitter t)
{

20
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
View file

@ -128,18 +128,14 @@ bool dal_cmd_table_helper_controller_id_to_atom2(
}
/**
* translate_transmitter_bp_to_atom
*
* @brief
* Translate the Transmitter to the corresponding ATOM BIOS value
*
* @param
* input transmitter
* output digitalTransmitter
* // =00: Digital Transmitter1 ( UNIPHY linkAB )
* // =01: Digital Transmitter2 ( UNIPHY linkCD )
* // =02: Digital Transmitter3 ( UNIPHY linkEF )
*/
* translate_transmitter_bp_to_atom2 - Translate the Transmitter to the
* corresponding ATOM BIOS value
* @t: transmitter
* returns: digitalTransmitter
* // =00: Digital Transmitter1 ( UNIPHY linkAB )
* // =01: Digital Transmitter2 ( UNIPHY linkCD )
* // =02: Digital Transmitter3 ( UNIPHY linkEF )
*/
uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
enum transmitter t)
{

13
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
View file

@ -106,7 +106,6 @@ static void calculate_bandwidth(
bool lpt_enabled;
enum bw_defines sclk_message;
enum bw_defines yclk_message;
enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
enum bw_defines tiling_mode[maximum_number_of_surfaces];
enum bw_defines surface_type[maximum_number_of_surfaces];
enum bw_defines voltage;
@ -792,12 +791,8 @@ static void calculate_bandwidth(
data->v_filter_init[i] = bw_add(data->v_filter_init[i], bw_int_to_fixed(1));
}
if (data->stereo_mode[i] == bw_def_top_bottom) {
v_filter_init_mode[i] = bw_def_manual;
data->v_filter_init[i] = bw_min2(data->v_filter_init[i], bw_int_to_fixed(4));
}
else {
v_filter_init_mode[i] = bw_def_auto;
}
if (data->stereo_mode[i] == bw_def_top_bottom) {
data->num_lines_at_frame_start = bw_int_to_fixed(1);
}
@ -2730,7 +2725,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
}
/**
/*
* Compare calculated (required) clocks against the clocks available at
* maximum voltage (max Performance Level).
*/
@ -3001,13 +2996,12 @@ static bool all_displays_in_sync(const struct pipe_ctx pipe[],
return true;
}
/**
/*
* Return:
* true - Display(s) configuration supported.
* In this case 'calcs_output' contains data for HW programming
* false - Display(s) configuration not supported (not enough bandwidth).
*/
bool bw_calcs(struct dc_context *ctx,
const struct bw_calcs_dceip *dceip,
const struct bw_calcs_vbios *vbios,
@ -3028,7 +3022,7 @@ bool bw_calcs(struct dc_context *ctx,
calcs_output->all_displays_in_sync = false;
if (data->number_of_displays != 0) {
uint8_t yclk_lvl, sclk_lvl;
uint8_t yclk_lvl;
struct bw_fixed high_sclk = vbios->high_sclk;
struct bw_fixed mid1_sclk = vbios->mid1_sclk;
struct bw_fixed mid2_sclk = vbios->mid2_sclk;
@ -3049,7 +3043,6 @@ bool bw_calcs(struct dc_context *ctx,
calculate_bandwidth(dceip, vbios, data);
yclk_lvl = data->y_clk_level;
sclk_lvl = data->sclk_level;
calcs_output->nbp_state_change_enable =
data->nbp_state_change_enable;

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
View file

@ -257,8 +257,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
if (update_dppclk || update_dispclk)
dcn20_update_clocks_update_dentist(clk_mgr);
// always update dtos unless clock is lowered and not safe to lower
if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
}
}

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
View file

@ -103,7 +103,7 @@ int dcn301_smu_send_msg_with_param(
/* Trigger the message transaction by writing the message ID */
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
result = dcn301_smu_wait_for_response(clk_mgr, 10, 1000);
result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
ASSERT(result == VBIOSSMC_Result_OK);

48
drivers/gpu/drm/amd/display/dc/core/dc.c
View file

@ -284,20 +284,16 @@ static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
}
/**
*****************************************************************************
* Function: dc_stream_adjust_vmin_vmax
* dc_stream_adjust_vmin_vmax:
*
* @brief
* Looks up the pipe context of dc_stream_state and updates the
* vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
* Rate, which is a power-saving feature that targets reducing panel
* refresh rate while the screen is static
* Looks up the pipe context of dc_stream_state and updates the
* vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
* Rate, which is a power-saving feature that targets reducing panel
* refresh rate while the screen is static
*
* @param [in] dc: dc reference
* @param [in] stream: Initial dc stream state
* @param [in] adjust: Updated parameters for vertical_total_min and
* vertical_total_max
*****************************************************************************
* @dc: dc reference
* @stream: Initial dc stream state
* @adjust: Updated parameters for vertical_total_min and vertical_total_max
*/
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct dc_stream_state *stream,
@ -355,6 +351,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
* @dc: DC Object
* @stream: The stream to configure CRC on.
* @enable: Enable CRC if true, disable otherwise.
* @crc_window: CRC window (x/y start/end) information
* @continuous: Capture CRC on every frame if true. Otherwise, only capture
* once.
*
@ -420,7 +417,9 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
* dc_stream_get_crc() - Get CRC values for the given stream.
* @dc: DC object
* @stream: The DC stream state of the stream to get CRCs from.
* @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
* @r_cr: CRC value for the first of the 3 channels stored here.
* @g_y: CRC value for the second of the 3 channels stored here.
* @b_cb: CRC value for the third of the 3 channels stored here.
*
* dc_stream_configure_crc needs to be called beforehand to enable CRCs.
* Return false if stream is not found, or if CRCs are not enabled.
@ -803,7 +802,8 @@ static void disable_all_writeback_pipes_for_stream(
stream->writeback_info[i].wb_enabled = false;
}
void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
struct dc_stream_state *stream, bool lock)
{
int i = 0;
@ -2011,7 +2011,7 @@ static enum surface_update_type check_update_surfaces_for_stream(
return overall_type;
}
/**
/*
* dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
*
* See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
@ -2265,6 +2265,9 @@ static void copy_stream_update_to_stream(struct dc *dc,
if (update->dither_option)
stream->dither_option = *update->dither_option;
if (update->pending_test_pattern)
stream->test_pattern = *update->pending_test_pattern;
/* update current stream with writeback info */
if (update->wb_update) {
int i;
@ -2361,6 +2364,15 @@ static void commit_planes_do_stream_update(struct dc *dc,
}
}
if (stream_update->pending_test_pattern) {
dc_link_dp_set_test_pattern(stream->link,
stream->test_pattern.type,
stream->test_pattern.color_space,
stream->test_pattern.p_link_settings,
stream->test_pattern.p_custom_pattern,
stream->test_pattern.cust_pattern_size);
}
/* Full fe update*/
if (update_type == UPDATE_TYPE_FAST)
continue;
@ -2814,7 +2826,7 @@ enum dc_irq_source dc_interrupt_to_irq_source(
return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
}
/**
/*
* dc_interrupt_set() - Enable/disable an AMD hw interrupt source
*/
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
@ -2948,7 +2960,7 @@ static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink
return true;
}
/**
/*
* dc_link_add_remote_sink() - Create a sink and attach it to an existing link
*
* EDID length is in bytes
@ -3011,7 +3023,7 @@ struct dc_sink *dc_link_add_remote_sink(
return NULL;
}
/**
/*
* dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
*
* Note that this just removes the struct dc_sink - it doesn't

62
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View file

@ -203,9 +203,21 @@ static bool program_hpd_filter(const struct dc_link *link)
return result;
}
bool dc_link_wait_for_t12(struct dc_link *link)
{
if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
link->dc->hwss.edp_wait_for_T12(link);
return true;
}
return false;
}
/**
* dc_link_detect_sink() - Determine if there is a sink connected
*
* @link: pointer to the dc link
* @type: Returned connection type
* Does not detect downstream devices, such as MST sinks
* or display connected through active dongles
@ -342,7 +354,7 @@ static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
return SIGNAL_TYPE_NONE;
}
/**
/*
* dc_link_is_dp_sink_present() - Check if there is a native DP
* or passive DP-HDMI dongle connected
*/
@ -596,8 +608,6 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
dc_process_hdcp_msg(signal, link, &msg22);
if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
msg14.data = &link->hdcp_caps.bcaps.raw;
msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
@ -605,7 +615,7 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
msg14.link = HDCP_LINK_PRIMARY;
msg14.max_retries = 5;
status = dc_process_hdcp_msg(signal, link, &msg14);
dc_process_hdcp_msg(signal, link, &msg14);
}
}
@ -830,7 +840,7 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
return false;
}
/**
/*
* dc_link_detect() - Detect if a sink is attached to a given link
*
* link->local_sink is created or destroyed as needed.
@ -1065,9 +1075,6 @@ static bool dc_link_detect_helper(struct dc_link *link,
break;
}
if (link->local_sink->edid_caps.panel_patch.disable_fec)
link->ctx->dc->debug.disable_fec = true;
// Check if edid is the same
if ((prev_sink) &&
(edid_status == EDID_THE_SAME || edid_status == EDID_OK))
@ -1366,13 +1373,17 @@ static bool dc_link_construct(struct dc_link *link,
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
struct panel_cntl_init_data panel_cntl_init_data = { 0 };
struct integrated_info info = {{{ 0 }}};
struct integrated_info *info;
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
DC_LOGGER_INIT(dc_ctx->logger);
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
goto create_fail;
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
@ -1534,12 +1545,12 @@ static bool dc_link_construct(struct dc_link *link,
}
if (bios->integrated_info)
info = *bios->integrated_info;
memcpy(info, bios->integrated_info, sizeof(*info));
/* Look for channel mapping corresponding to connector and device tag */
for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
struct external_display_path *path =
&info.ext_disp_conn_info.path[i];
&info->ext_disp_conn_info.path[i];
if (path->device_connector_id.enum_id == link->link_id.enum_id &&
path->device_connector_id.id == link->link_id.id &&
@ -1586,6 +1597,8 @@ static bool dc_link_construct(struct dc_link *link,
link->hpd_gpio = NULL;
}
kfree(info);
return false;
}
@ -3396,10 +3409,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
}
/**
*****************************************************************************
* Function: dc_link_enable_hpd_filter
*
* @brief
* dc_link_enable_hpd_filter:
* If enable is true, programs HPD filter on associated HPD line using
* delay_on_disconnect/delay_on_connect values dependent on
* link->connector_signal
@ -3407,9 +3417,8 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
* If enable is false, programs HPD filter on associated HPD line with no
* delays on connect or disconnect
*
* @param [in] link: pointer to the dc link
* @param [in] enable: boolean specifying whether to enable hbd
*****************************************************************************
* @link: pointer to the dc link
* @enable: boolean specifying whether to enable hbd
*/
void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
{
@ -3635,7 +3644,7 @@ uint32_t dc_link_bandwidth_kbps(
link_bw_kbps *= 8; /* 8 bits per byte*/
link_bw_kbps *= link_setting->lane_count;
if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
if (dc_link_should_enable_fec(link)) {
/* Account for FEC overhead.
* We have to do it based on caps,
* and not based on FEC being set ready,
@ -3687,3 +3696,18 @@ bool dc_link_is_fec_supported(const struct dc_link *link)
!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
}
bool dc_link_should_enable_fec(const struct dc_link *link)
{
bool is_fec_disable = false;
bool ret = false;
if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
link->local_sink &&
link->local_sink->edid_caps.panel_patch.disable_fec)
is_fec_disable = true;
if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
ret = true;
return ret;
}

59
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View file

@ -3707,7 +3707,7 @@ bool detect_dp_sink_caps(struct dc_link *link)
/* TODO save sink caps in link->sink */
}
enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
{
enum dc_link_rate link_rate;
// LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
@ -3992,7 +3992,7 @@ bool dc_link_dp_set_test_pattern(
unsigned int cust_pattern_size)
{
struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
struct pipe_ctx *pipe_ctx = &pipes[0];
struct pipe_ctx *pipe_ctx = NULL;
unsigned int lane;
unsigned int i;
unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
@ -4002,12 +4002,18 @@ bool dc_link_dp_set_test_pattern(
memset(&training_pattern, 0, sizeof(training_pattern));
for (i = 0; i < MAX_PIPES; i++) {
if (pipes[i].stream == NULL)
continue;
if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
pipe_ctx = &pipes[i];
break;
}
}
if (pipe_ctx == NULL)
return false;
/* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
if (link->test_pattern_enabled && test_pattern ==
DP_TEST_PATTERN_VIDEO_MODE) {
@ -4339,7 +4345,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
struct link_encoder *link_enc = link->link_enc;
uint8_t fec_config = 0;
if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
if (!dc_link_should_enable_fec(link))
return;
if (link_enc->funcs->fec_set_ready &&
@ -4374,7 +4380,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
{
struct link_encoder *link_enc = link->link_enc;
if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
if (!dc_link_should_enable_fec(link))
return;
if (link_enc->funcs->fec_set_enable &&
@ -4400,25 +4406,40 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
void dpcd_set_source_specific_data(struct dc_link *link)
{
if (!link->dc->vendor_signature.is_valid) {
enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
struct dpcd_amd_signature amd_signature;
amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
amd_signature.device_id_byte1 =
(uint8_t)(link->ctx->asic_id.chip_id);
amd_signature.device_id_byte2 =
(uint8_t)(link->ctx->asic_id.chip_id >> 8);
memset(&amd_signature.zero, 0, 4);
amd_signature.dce_version =
(uint8_t)(link->ctx->dce_version);
amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
struct dpcd_amd_signature amd_signature = {0};
struct dpcd_amd_device_id amd_device_id = {0};
core_link_write_dpcd(link, DP_SOURCE_OUI,
amd_device_id.device_id_byte1 =
(uint8_t)(link->ctx->asic_id.chip_id);
amd_device_id.device_id_byte2 =
(uint8_t)(link->ctx->asic_id.chip_id >> 8);
amd_device_id.dce_version =
(uint8_t)(link->ctx->dce_version);
amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
core_link_read_dpcd(link, DP_SOURCE_OUI,
(uint8_t *)(&amd_signature),
sizeof(amd_signature));
if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
(amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
(amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
core_link_write_dpcd(link, DP_SOURCE_OUI,
(uint8_t *)(&amd_signature),
sizeof(amd_signature));
}
core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
(uint8_t *)(&amd_device_id),
sizeof(amd_device_id));
if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
link->dc->caps.min_horizontal_blanking_period != 0) {

42
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View file

@ -1117,7 +1117,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
* We also need to make sure pipe_ctx->plane_res.scl_data.h_active uses the
* original h_border_left value in its calculation.
*/
int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
static int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
{
int store_h_border_left = pipe_ctx->stream->timing.h_border_left;
@ -1128,8 +1128,8 @@ int shift_border_left_to_dst(struct pipe_ctx *pipe_ctx)
return store_h_border_left;
}
void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
int store_h_border_left)
static void restore_border_left_from_dst(struct pipe_ctx *pipe_ctx,
int store_h_border_left)
{
pipe_ctx->stream->dst.x -= store_h_border_left;
pipe_ctx->stream->timing.h_border_left = store_h_border_left;
@ -1697,7 +1697,7 @@ static bool are_stream_backends_same(
return true;
}
/**
/*
* dc_is_stream_unchanged() - Compare two stream states for equivalence.
*
* Checks if there a difference between the two states
@ -1718,7 +1718,7 @@ bool dc_is_stream_unchanged(
return true;
}
/**
/*
* dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
*/
bool dc_is_stream_scaling_unchanged(
@ -1833,7 +1833,7 @@ static struct audio *find_first_free_audio(
return 0;
}
/**
/*
* dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
*/
enum dc_status dc_add_stream_to_ctx(
@ -1860,7 +1860,7 @@ enum dc_status dc_add_stream_to_ctx(
return res;
}
/**
/*
* dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
*/
enum dc_status dc_remove_stream_from_ctx(
@ -2075,6 +2075,20 @@ static int acquire_resource_from_hw_enabled_state(
return -1;
}
static void mark_seamless_boot_stream(
const struct dc *dc,
struct dc_stream_state *stream)
{
struct dc_bios *dcb = dc->ctx->dc_bios;
/* TODO: Check Linux */
if (dc->config.allow_seamless_boot_optimization &&
!dcb->funcs->is_accelerated_mode(dcb)) {
if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
stream->apply_seamless_boot_optimization = true;
}
}
enum dc_status resource_map_pool_resources(
const struct dc *dc,
struct dc_state *context,
@ -2085,22 +2099,20 @@ enum dc_status resource_map_pool_resources(
struct dc_context *dc_ctx = dc->ctx;
struct pipe_ctx *pipe_ctx = NULL;
int pipe_idx = -1;
struct dc_bios *dcb = dc->ctx->dc_bios;
calculate_phy_pix_clks(stream);
/* TODO: Check Linux */
if (dc->config.allow_seamless_boot_optimization &&
!dcb->funcs->is_accelerated_mode(dcb)) {
if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing))
stream->apply_seamless_boot_optimization = true;
}
mark_seamless_boot_stream(dc, stream);
if (stream->apply_seamless_boot_optimization)
if (stream->apply_seamless_boot_optimization) {
pipe_idx = acquire_resource_from_hw_enabled_state(
&context->res_ctx,
pool,
stream);
if (pipe_idx < 0)
/* hw resource was assigned to other stream */
stream->apply_seamless_boot_optimization = false;
}
if (pipe_idx < 0)
/* acquire new resources */

5
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View file

@ -244,7 +244,7 @@ struct dc_stream_status *dc_stream_get_status(
}
#ifndef TRIM_FSFT
/**
/*
* dc_optimize_timing_for_fsft() - dc to optimize timing
*/
bool dc_optimize_timing_for_fsft(
@ -260,8 +260,7 @@ bool dc_optimize_timing_for_fsft(
}
#endif
/**
/*
* dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
*/
bool dc_stream_set_cursor_attributes(

2
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
View file

@ -115,7 +115,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
return plane_state;
}
/**
/*
*****************************************************************************
* Function: dc_plane_get_status
*

3
drivers/gpu/drm/amd/display/dc/dc.h
View file

@ -42,7 +42,7 @@
#include "inc/hw/dmcu.h"
#include "dml/display_mode_lib.h"
#define DC_VER "3.2.116"
#define DC_VER "3.2.118"
#define MAX_SURFACES 3
#define MAX_PLANES 6
@ -484,7 +484,6 @@ struct dc_debug_options {
bool performance_trace;
bool az_endpoint_mute_only;
bool always_use_regamma;
bool p010_mpo_support;
bool recovery_enabled;
bool avoid_vbios_exec_table;
bool scl_reset_length10;

3
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
View file

@ -451,6 +451,9 @@ struct dpcd_amd_signature {
uint8_t AMD_IEEE_TxSignature_byte1;
uint8_t AMD_IEEE_TxSignature_byte2;
uint8_t AMD_IEEE_TxSignature_byte3;
};
struct dpcd_amd_device_id {
uint8_t device_id_byte1;
uint8_t device_id_byte2;
uint8_t zero[4];

1
drivers/gpu/drm/amd/display/dc/dc_helper.c
View file

@ -34,6 +34,7 @@
#include "dc.h"
#include "dc_dmub_srv.h"
#include "reg_helper.h"
static inline void submit_dmub_read_modify_write(
struct dc_reg_helper_state *offload,

8
drivers/gpu/drm/amd/display/dc/dc_link.h
View file

@ -259,6 +259,13 @@ enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link);
bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss);
/*
* On eDP links this function call will stall until T12 has elapsed.
* If the panel is not in power off state, this function will return
* immediately.
*/
bool dc_link_wait_for_t12(struct dc_link *link);
enum dc_status read_hpd_rx_irq_data(
struct dc_link *link,
union hpd_irq_data *irq_data);
@ -369,5 +376,6 @@ uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing);
bool dc_link_is_fec_supported(const struct dc_link *link);
bool dc_link_should_enable_fec(const struct dc_link *link);
#endif /* DC_LINK_H_ */

11
drivers/gpu/drm/amd/display/dc/dc_stream.h
View file

@ -130,6 +130,14 @@ union stream_update_flags {
uint32_t raw;
};
struct test_pattern {
enum dp_test_pattern type;
enum dp_test_pattern_color_space color_space;
struct link_training_settings const *p_link_settings;
unsigned char const *p_custom_pattern;
unsigned int cust_pattern_size;
};
struct dc_stream_state {
// sink is deprecated, new code should not reference
// this pointer
@ -227,6 +235,8 @@ struct dc_stream_state {
uint32_t stream_id;
bool is_dsc_enabled;
struct test_pattern test_pattern;
union stream_update_flags update_flags;
};
@ -261,6 +271,7 @@ struct dc_stream_update {
struct dc_dsc_config *dsc_config;
struct dc_transfer_func *func_shaper;
struct dc_3dlut *lut3d_func;
struct test_pattern *pending_test_pattern;
};
bool dc_is_stream_unchanged(

2
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
View file

@ -868,7 +868,7 @@ void dce_aud_wall_dto_setup(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
void dce60_aud_wall_dto_setup(
static void dce60_aud_wall_dto_setup(
struct audio *audio,
enum signal_type signal,
const struct audio_crtc_info *crtc_info,

8
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
View file

@ -388,12 +388,6 @@ static enum aux_channel_operation_result get_channel_status(
}
}
enum i2caux_engine_type get_engine_type(
const struct dce_aux *engine)
{
return I2CAUX_ENGINE_TYPE_AUX;
}
static bool acquire(
struct dce_aux *engine,
struct ddc *ddc)
@ -582,7 +576,7 @@ int dce_aux_transfer_raw(struct ddc_service *ddc,
*operation_result = get_channel_status(aux_engine, &returned_bytes);
if (*operation_result == AUX_CHANNEL_OPERATION_SUCCEEDED) {
int bytes_replied = 0;
int __maybe_unused bytes_replied = 0;
bytes_replied = read_channel_reply(aux_engine, payload->length,
payload->data, payload->reply,
&status);

1
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
View file

@ -124,7 +124,6 @@ struct dce110_aux_registers {
AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

57
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View file

@ -113,20 +113,19 @@ static const struct spread_spectrum_data *get_ss_data_entry(
}
/**
* Function: calculate_fb_and_fractional_fb_divider
* calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
* feedback dividers values
*
* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
* @calc_pll_cs: Pointer to clock source information
* @target_pix_clk_100hz: Desired frequency in 100 Hz
* @ref_divider: Reference divider (already known)
* @post_divider: Post Divider (already known)
* @feedback_divider_param: Pointer where to store
* calculated feedback divider value
* @fract_feedback_divider_param: Pointer where to store
* calculated fract feedback divider value
*
*PARAMETERS:
* targetPixelClock Desired frequency in 100 Hz
* ref_divider Reference divider (already known)
* postDivider Post Divider (already known)
* feedback_divider_param Pointer where to store
* calculated feedback divider value
* fract_feedback_divider_param Pointer where to store
* calculated fract feedback divider value
*
*RETURNS:
* return:
* It fills the locations pointed by feedback_divider_param
* and fract_feedback_divider_param
* It returns - true if feedback divider not 0
@ -175,22 +174,22 @@ static bool calculate_fb_and_fractional_fb_divider(
}
/**
*calc_fb_divider_checking_tolerance
*
*DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
* for passed Reference and Post divider, checking for tolerance.
*PARAMETERS:
* pll_settings Pointer to structure
* ref_divider Reference divider (already known)
* postDivider Post Divider (already known)
* tolerance Tolerance for Calculated Pixel Clock to be within
*
*RETURNS:
* It fills the PLLSettings structure with PLL Dividers values
* if calculated values are within required tolerance
* It returns - true if error is within tolerance
* - false if error is not within tolerance
*/
* calc_fb_divider_checking_tolerance - Calculates Feedback and
* Fractional Feedback divider values
* for passed Reference and Post divider,
* checking for tolerance.
* @calc_pll_cs: Pointer to clock source information
* @pll_settings: Pointer to PLL settings
* @ref_divider: Reference divider (already known)
* @post_divider: Post Divider (already known)
* @tolerance: Tolerance for Calculated Pixel Clock to be within
*
* return:
* It fills the PLLSettings structure with PLL Dividers values
* if calculated values are within required tolerance
* It returns - true if error is within tolerance
* - false if error is not within tolerance
*/
static bool calc_fb_divider_checking_tolerance(
struct calc_pll_clock_source *calc_pll_cs,
struct pll_settings *pll_settings,
@ -460,7 +459,7 @@ static bool pll_adjust_pix_clk(
return false;
}
/**
/*
* Calculate PLL Dividers for given Clock Value.
* First will call VBIOS Adjust Exec table to check if requested Pixel clock
* will be Adjusted based on usage.

6
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
View file

@ -65,13 +65,17 @@
//Register access policy version
#define mmMP0_SMN_C2PMSG_91 0x1609B
#if defined(CONFIG_DRM_AMD_DC_DCN)
static const uint32_t abm_gain_stepsize = 0x0060;
#endif
static bool dce_dmcu_init(struct dmcu *dmcu)
{
// Do nothing
return true;
}
bool dce_dmcu_load_iram(struct dmcu *dmcu,
static bool dce_dmcu_load_iram(struct dmcu *dmcu,
unsigned int start_offset,
const char *src,
unsigned int bytes)

2
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
View file

@ -317,6 +317,4 @@ struct dmcu *dcn21_dmcu_create(
void dce_dmcu_destroy(struct dmcu **dmcu);
static const uint32_t abm_gain_stepsize = 0x0060;
#endif /* _DCE_ABM_H_ */

4
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
View file

@ -435,7 +435,7 @@ struct dce_i2c_hw *acquire_i2c_hw_engine(
return dce_i2c_hw;
}
enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result(
static enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result(
struct dce_i2c_hw *dce_i2c_hw,
uint32_t timeout,
enum i2c_channel_operation_result expected_result)
@ -502,7 +502,7 @@ static uint32_t get_transaction_timeout_hw(
return period_timeout * num_of_clock_stretches;
}
bool dce_i2c_hw_engine_submit_payload(
static bool dce_i2c_hw_engine_submit_payload(
struct dce_i2c_hw *dce_i2c_hw,
struct i2c_payload *payload,
bool middle_of_transaction,

9
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
View file

@ -339,7 +339,7 @@ static bool start_sync_sw(
return false;
}
void dce_i2c_sw_engine_set_speed(
static void dce_i2c_sw_engine_set_speed(
struct dce_i2c_sw *engine,
uint32_t speed)
{
@ -353,7 +353,7 @@ void dce_i2c_sw_engine_set_speed(
engine->clock_delay = 12;
}
bool dce_i2c_sw_engine_acquire_engine(
static bool dce_i2c_sw_engine_acquire_engine(
struct dce_i2c_sw *engine,
struct ddc *ddc)
{
@ -397,7 +397,7 @@ bool dce_i2c_engine_acquire_sw(
void dce_i2c_sw_engine_submit_channel_request(
static void dce_i2c_sw_engine_submit_channel_request(
struct dce_i2c_sw *engine,
struct i2c_request_transaction_data *req)
{
@ -440,7 +440,8 @@ void dce_i2c_sw_engine_submit_channel_request(
I2C_CHANNEL_OPERATION_SUCCEEDED :
I2C_CHANNEL_OPERATION_FAILED;
}
bool dce_i2c_sw_engine_submit_payload(
static bool dce_i2c_sw_engine_submit_payload(
struct dce_i2c_sw *engine,
struct i2c_payload *payload,
bool middle_of_transaction)

9
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
View file

@ -1197,7 +1197,7 @@ void dce110_link_encoder_enable_dp_mst_output(
#if defined(CONFIG_DRM_AMD_DC_SI)
/* enables DP PHY output */
void dce60_link_encoder_enable_dp_output(
static void dce60_link_encoder_enable_dp_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source)
@ -1236,7 +1236,7 @@ void dce60_link_encoder_enable_dp_output(
}
/* enables DP PHY output in MST mode */
void dce60_link_encoder_enable_dp_mst_output(
static void dce60_link_encoder_enable_dp_mst_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source)
@ -1426,7 +1426,7 @@ void dce110_link_encoder_dp_set_phy_pattern(
#if defined(CONFIG_DRM_AMD_DC_SI)
/* set DP PHY test and training patterns */
void dce60_link_encoder_dp_set_phy_pattern(
static void dce60_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc,
const struct encoder_set_dp_phy_pattern_param *param)
{
@ -1503,7 +1503,6 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
const struct link_mst_stream_allocation_table *table)
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
uint32_t value0 = 0;
uint32_t value1 = 0;
uint32_t value2 = 0;
uint32_t slots = 0;
@ -1604,7 +1603,7 @@ void dce110_link_encoder_update_mst_stream_allocation_table(
do {
udelay(10);
value0 = REG_READ(DP_MSE_SAT_UPDATE);
REG_READ(DP_MSE_SAT_UPDATE);
REG_GET(DP_MSE_SAT_UPDATE,
DP_MSE_SAT_UPDATE, &value1);

24
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
View file

@ -97,7 +97,7 @@ enum {
/**
/*
* set_truncation
* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
* 2) enable truncation
@ -142,7 +142,7 @@ static void set_truncation(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
/**
/*
* dce60_set_truncation
* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
* 2) enable truncation
@ -183,7 +183,7 @@ static void dce60_set_truncation(
}
#endif
/**
/*
* set_spatial_dither
* 1) set spatial dithering mode: pattern of seed
* 2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
@ -291,7 +291,7 @@ static void set_spatial_dither(
FMT_SPATIAL_DITHER_EN, 1);
}
/**
/*
* SetTemporalDither (Frame Modulation)
* 1) set temporal dither depth
* 2) select pattern: from hard-coded pattern or programmable pattern
@ -355,7 +355,7 @@ static void set_temporal_dither(
FMT_TEMPORAL_DITHER_EN, 1);
}
/**
/*
* Set Clamping
* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
* 1 for 8 bpc
@ -415,7 +415,7 @@ void dce110_opp_set_clamping(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
/**
/*
* Set Clamping for DCE6 parts
* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
* 1 for 8 bpc
@ -424,7 +424,7 @@ void dce110_opp_set_clamping(
* 7 for programable
* 2) Enable clamp if Limited range requested
*/
void dce60_opp_set_clamping(
static void dce60_opp_set_clamping(
struct dce110_opp *opp110,
const struct clamping_and_pixel_encoding_params *params)
{
@ -465,7 +465,7 @@ void dce60_opp_set_clamping(
}
#endif
/**
/*
* set_pixel_encoding
*
* Set Pixel Encoding
@ -501,7 +501,7 @@ static void set_pixel_encoding(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
/**
/*
* dce60_set_pixel_encoding
* DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL reg
* Set Pixel Encoding
@ -545,7 +545,7 @@ void dce110_opp_program_bit_depth_reduction(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
void dce60_opp_program_bit_depth_reduction(
static void dce60_opp_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params)
{
@ -568,7 +568,7 @@ void dce110_opp_program_clamping_and_pixel_encoding(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
void dce60_opp_program_clamping_and_pixel_encoding(
static void dce60_opp_program_clamping_and_pixel_encoding(
struct output_pixel_processor *opp,
const struct clamping_and_pixel_encoding_params *params)
{
@ -678,7 +678,7 @@ void dce110_opp_program_fmt(
}
#if defined(CONFIG_DRM_AMD_DC_SI)
void dce60_opp_program_fmt(
static void dce60_opp_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)

2
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
View file

@ -111,7 +111,6 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
@ -219,7 +218,6 @@ enum dce110_opp_reg_type {
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\

8
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
View file

@ -50,16 +50,16 @@ static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_c
{
uint64_t current_backlight;
uint32_t round_result;
uint32_t pwm_period_cntl, bl_period, bl_int_count;
uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
uint32_t bl_period, bl_int_count;
uint32_t bl_pwm, fractional_duty_cycle_en;
uint32_t bl_period_mask, bl_pwm_mask;
struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
REG_READ(BL_PWM_PERIOD_CNTL);
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
REG_READ(BL_PWM_CNTL);
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);

3
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
View file

@ -67,7 +67,6 @@ static void dce110_update_generic_info_packet(
uint32_t packet_index,
const struct dc_info_packet *info_packet)
{
uint32_t regval;
/* TODOFPGA Figure out a proper number for max_retries polling for lock
* use 50 for now.
*/
@ -99,7 +98,7 @@ static void dce110_update_generic_info_packet(
}
/* choose which generic packet to use */
{
regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
REG_READ(AFMT_VBI_PACKET_CONTROL);
REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
AFMT_GENERIC_INDEX, packet_index);
}

15
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
View file

@ -493,7 +493,6 @@ static void dce60_transform_set_scaler(
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
bool is_scaling_required;
bool filter_updated = false;
const uint16_t *coeffs_v, *coeffs_h;
/*Use whole line buffer memory always*/
@ -558,7 +557,6 @@ static void dce60_transform_set_scaler(
xfm_dce->filter_v = coeffs_v;
xfm_dce->filter_h = coeffs_h;
filter_updated = true;
}
}
@ -1037,34 +1035,23 @@ static void dce60_transform_set_pixel_storage_depth(
const struct bit_depth_reduction_params *bit_depth_params)
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
int pixel_depth, expan_mode;
enum dc_color_depth color_depth;
switch (depth) {
case LB_PIXEL_DEPTH_18BPP:
color_depth = COLOR_DEPTH_666;
pixel_depth = 2;
expan_mode = 1;
break;
case LB_PIXEL_DEPTH_24BPP:
color_depth = COLOR_DEPTH_888;
pixel_depth = 1;
expan_mode = 1;
break;
case LB_PIXEL_DEPTH_30BPP:
color_depth = COLOR_DEPTH_101010;
pixel_depth = 0;
expan_mode = 1;
break;
case LB_PIXEL_DEPTH_36BPP:
color_depth = COLOR_DEPTH_121212;
pixel_depth = 3;
expan_mode = 0;
break;
default:
color_depth = COLOR_DEPTH_101010;
pixel_depth = 0;
expan_mode = 1;
BREAK_TO_DEBUGGER();
break;
}
@ -1113,7 +1100,7 @@ static void program_gamut_remap(
}
/**
/*
*****************************************************************************
* Function: dal_transform_wide_gamut_set_gamut_remap
*

22
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
View file

@ -31,7 +31,7 @@
#define MAX_PIPES 6
/**
/*
* Convert dmcub psr state to dmcu psr state.
*/
static enum dc_psr_state convert_psr_state(uint32_t raw_state)
@ -74,7 +74,7 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
return state;
}
/**
/*
* Get PSR state from firmware.
*/
static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
@ -90,7 +90,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
*state = convert_psr_state(raw_state);
}
/**
/*
* Set PSR version.
*/
static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream)
@ -121,7 +121,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
return true;
}
/**
/*
* Enable/Disable PSR.
*/
static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
@ -170,7 +170,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
}
}
/**
/*
* Set PSR level.
*/
static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
@ -194,7 +194,7 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
dc_dmub_srv_wait_idle(dc->dmub_srv);
}
/**
/*
* Setup PSR by programming phy registers and sending psr hw context values to firmware.
*/
static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
@ -277,7 +277,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
return true;
}
/**
/*
* Send command to PSR to force static ENTER and ignore all state changes until exit
*/
static void dmub_psr_force_static(struct dmub_psr *dmub)
@ -294,7 +294,7 @@ static void dmub_psr_force_static(struct dmub_psr *dmub)
dc_dmub_srv_wait_idle(dc->dmub_srv);
}
/**
/*
* Get PSR residency from firmware.
*/
static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency)
@ -316,7 +316,7 @@ static const struct dmub_psr_funcs psr_funcs = {
.psr_get_residency = dmub_psr_get_residency,
};
/**
/*
* Construct PSR object.
*/
static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
@ -325,7 +325,7 @@ static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
psr->funcs = &psr_funcs;
}
/**
/*
* Allocate and initialize PSR object.
*/
struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
@ -342,7 +342,7 @@ struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
return psr;
}
/**
/*
* Deallocate PSR object.
*/
void dmub_psr_destroy(struct dmub_psr **dmub)

2
drivers/gpu/drm/amd/display/dc/dce100/Makefile
View file

@ -23,6 +23,8 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
CFLAGS_$(AMDDALPATH)/dc/dce100/dce100_resource.o = $(call cc-disable-warning, override-init)
DCE100 = dce100_resource.o dce100_hw_sequencer.o
AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))

18
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View file

@ -58,6 +58,8 @@
#include "dce/dce_abm.h"
#include "dce/dce_i2c.h"
#include "dce100_resource.h"
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
@ -611,7 +613,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
};
struct link_encoder *dce100_link_encoder_create(
static struct link_encoder *dce100_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@ -650,7 +652,7 @@ static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_
return &panel_cntl->base;
}
struct output_pixel_processor *dce100_opp_create(
static struct output_pixel_processor *dce100_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -665,7 +667,7 @@ struct output_pixel_processor *dce100_opp_create(
return &opp->base;
}
struct dce_aux *dce100_aux_engine_create(
static struct dce_aux *dce100_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -703,7 +705,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
struct dce_i2c_hw *dce100_i2c_hw_create(
static struct dce_i2c_hw *dce100_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -718,7 +720,7 @@ struct dce_i2c_hw *dce100_i2c_hw_create(
return dce_i2c_hw;
}
struct clock_source *dce100_clock_source_create(
static struct clock_source *dce100_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@ -742,7 +744,7 @@ struct clock_source *dce100_clock_source_create(
return NULL;
}
void dce100_clock_source_destroy(struct clock_source **clk_src)
static void dce100_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@ -831,7 +833,7 @@ static enum dc_status build_mapped_resource(
return DC_OK;
}
bool dce100_validate_bandwidth(
static bool dce100_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@ -876,7 +878,7 @@ static bool dce100_validate_surface_sets(
return true;
}
enum dc_status dce100_validate_global(
static enum dc_status dce100_validate_global(
struct dc *dc,
struct dc_state *context)
{

2
drivers/gpu/drm/amd/display/dc/dce110/Makefile
View file

@ -23,6 +23,8 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
CFLAGS_$(AMDDALPATH)/dc/dce110/dce110_resource.o = $(call cc-disable-warning, override-init)
DCE110 = dce110_timing_generator.o \
dce110_compressor.o dce110_hw_sequencer.o dce110_resource.o \
dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \

55
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
View file

@ -412,36 +412,6 @@ void dce110_compressor_destroy(struct compressor **compressor)
*compressor = NULL;
}
bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info,
struct fbc_requested_compressed_size size)
{
bool result = false;
unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
get_max_support_fbc_buffersize(&max_x, &max_y);
if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
/*
* For DCE11 here use Max HW supported size: HW Support up to 3840x2400 resolution
* or 18000 chunks.
*/
size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4; /* (For FBC when LPT not supported). */
size.preferred_size_alignment = size.min_size_alignment = 0x100; /* For FBC when LPT not supported */
size.bits.preferred_must_be_framebuffer_pool = 1;
size.bits.min_must_be_framebuffer_pool = 1;
result = true;
}
/*
* Maybe to add registry key support with optional size here to override above
* for debugging purposes
*/
return result;
}
void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
{
*max_x = FBC_MAX_X;
@ -455,31 +425,6 @@ void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
*/
}
unsigned int controller_id_to_index(enum controller_id controller_id)
{
unsigned int index = 0;
switch (controller_id) {
case CONTROLLER_ID_D0:
index = 0;
break;
case CONTROLLER_ID_D1:
index = 1;
break;
case CONTROLLER_ID_D2:
index = 2;
break;
case CONTROLLER_ID_D3:
index = 3;
break;
default:
break;
}
return index;
}
static const struct compressor_funcs dce110_compressor_funcs = {
.power_up_fbc = dce110_compressor_power_up_fbc,
.enable_fbc = dce110_compressor_enable_fbc,

33
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file

@ -921,6 +921,37 @@ void dce110_edp_power_control(
}
}
void dce110_edp_wait_for_T12(
struct dc_link *link)
{
struct dc_context *ctx = link->ctx;
if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
!= CONNECTOR_ID_EDP) {
BREAK_TO_DEBUGGER();
return;
}
if (!link->panel_cntl)
return;
if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
link->link_trace.time_stamp.edp_poweroff != 0) {
unsigned int t12_duration = 500; // Default T12 as per spec
unsigned long long current_ts = dm_get_timestamp(ctx);
unsigned long long time_since_edp_poweroff_ms =
div64_u64(dm_get_elapse_time_in_ns(
ctx,
current_ts,
link->link_trace.time_stamp.edp_poweroff), 1000000);
t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
if (time_since_edp_poweroff_ms < t12_duration)
msleep(t12_duration - time_since_edp_poweroff_ms);
}
}
/*todo: cloned in stream enc, fix*/
/*
* @brief
@ -1628,7 +1659,7 @@ static struct dc_link *get_edp_link_with_sink(
return link;
}
/**
/*
* When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
* 1. Power down all DC HW blocks
* 2. Disable VGA engine on all controllers

17
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
View file

@ -34,6 +34,7 @@
#include "inc/dce_calcs.h"
#include "dce/dce_mem_input.h"
#include "dce110_mem_input_v.h"
static void set_flip_control(
struct dce_mem_input *mem_input110,
@ -468,7 +469,7 @@ static void program_pixel_format(
}
}
bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
static bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
{
struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
uint32_t value;
@ -483,7 +484,7 @@ bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
return false;
}
bool dce_mem_input_v_program_surface_flip_and_addr(
static bool dce_mem_input_v_program_surface_flip_and_addr(
struct mem_input *mem_input,
const struct dc_plane_address *address,
bool flip_immediate)
@ -560,7 +561,7 @@ static const unsigned int *get_dvmm_hw_setting(
}
}
void dce_mem_input_v_program_pte_vm(
static void dce_mem_input_v_program_pte_vm(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@ -633,7 +634,7 @@ void dce_mem_input_v_program_pte_vm(
dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value);
}
void dce_mem_input_v_program_surface_config(
static void dce_mem_input_v_program_surface_config(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@ -919,7 +920,7 @@ static void program_nbp_watermark_c(
marks);
}
void dce_mem_input_v_program_display_marks(
static void dce_mem_input_v_program_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
@ -942,7 +943,7 @@ void dce_mem_input_v_program_display_marks(
}
void dce_mem_input_program_chroma_display_marks(
static void dce_mem_input_program_chroma_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
@ -963,7 +964,7 @@ void dce_mem_input_program_chroma_display_marks(
stutter);
}
void dce110_allocate_mem_input_v(
static void dce110_allocate_mem_input_v(
struct mem_input *mi,
uint32_t h_total,/* for current stream */
uint32_t v_total,/* for current stream */
@ -1005,7 +1006,7 @@ void dce110_allocate_mem_input_v(
}
void dce110_free_mem_input_v(
static void dce110_free_mem_input_v(
struct mem_input *mi,
uint32_t total_stream_num)
{

17
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View file

@ -715,7 +715,7 @@ static struct output_pixel_processor *dce110_opp_create(
return &opp->base;
}
struct dce_aux *dce110_aux_engine_create(
static struct dce_aux *dce110_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -753,7 +753,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
struct dce_i2c_hw *dce110_i2c_hw_create(
static struct dce_i2c_hw *dce110_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -768,7 +768,7 @@ struct dce_i2c_hw *dce110_i2c_hw_create(
return dce_i2c_hw;
}
struct clock_source *dce110_clock_source_create(
static struct clock_source *dce110_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@ -792,7 +792,7 @@ struct clock_source *dce110_clock_source_create(
return NULL;
}
void dce110_clock_source_destroy(struct clock_source **clk_src)
static void dce110_clock_source_destroy(struct clock_source **clk_src)
{
struct dce110_clk_src *dce110_clk_src;
@ -1034,8 +1034,8 @@ static bool dce110_validate_bandwidth(
return result;
}
enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
struct dc_caps *caps)
static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
struct dc_caps *caps)
{
if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
@ -1089,7 +1089,7 @@ static bool dce110_validate_surface_sets(
return true;
}
enum dc_status dce110_validate_global(
static enum dc_status dce110_validate_global(
struct dc *dc,
struct dc_state *context)
{
@ -1272,7 +1272,6 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
/* update the public caps to indicate an underlay is available */
ctx->dc->caps.max_slave_planes = 1;
ctx->dc->caps.max_slave_planes = 1;
return true;
}
@ -1333,7 +1332,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
1000);
}
const struct resource_caps *dce110_resource_cap(
static const struct resource_caps *dce110_resource_cap(
struct hw_asic_id *asic_id)
{
if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))

76
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
View file

@ -75,7 +75,7 @@ static void dce110_timing_generator_apply_front_porch_workaround(
}
}
/**
/*
*****************************************************************************
* Function: is_in_vertical_blank
*
@ -116,7 +116,7 @@ void dce110_timing_generator_set_early_control(
dm_write_reg(tg->ctx, address, regval);
}
/**
/*
* Enable CRTC
* Enable CRTC - call ASIC Control Object to enable Timing generator.
*/
@ -175,7 +175,7 @@ void dce110_timing_generator_program_blank_color(
dm_write_reg(tg->ctx, addr, value);
}
/**
/*
*****************************************************************************
* Function: disable_stereo
*
@ -226,7 +226,7 @@ static void disable_stereo(struct timing_generator *tg)
}
#endif
/**
/*
* disable_crtc - call ASIC Control Object to disable Timing generator.
*/
bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
@ -247,11 +247,10 @@ bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
return result == BP_RESULT_OK;
}
/**
* program_horz_count_by_2
* Programs DxCRTC_HORZ_COUNT_BY2_EN - 1 for DVI 30bpp mode, 0 otherwise
*
*/
/*
* program_horz_count_by_2
* Programs DxCRTC_HORZ_COUNT_BY2_EN - 1 for DVI 30bpp mode, 0 otherwise
*/
static void program_horz_count_by_2(
struct timing_generator *tg,
const struct dc_crtc_timing *timing)
@ -273,7 +272,7 @@ static void program_horz_count_by_2(
CRTC_REG(mmCRTC_COUNT_CONTROL), regval);
}
/**
/*
* program_timing_generator
* Program CRTC Timing Registers - DxCRTC_H_*, DxCRTC_V_*, Pixel repetition.
* Call ASIC Control Object to program Timings.
@ -352,7 +351,7 @@ bool dce110_timing_generator_program_timing_generator(
return result == BP_RESULT_OK;
}
/**
/*
*****************************************************************************
* Function: set_drr
*
@ -521,7 +520,7 @@ uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)
return field;
}
/**
/*
*****************************************************************************
* Function: dce110_timing_generator_get_position
*
@ -557,7 +556,7 @@ void dce110_timing_generator_get_position(struct timing_generator *tg,
CRTC_VERT_COUNT_NOM);
}
/**
/*
*****************************************************************************
* Function: get_crtc_scanoutpos
*
@ -1106,11 +1105,11 @@ void dce110_timing_generator_set_test_pattern(
}
}
/**
* dce110_timing_generator_validate_timing
* The timing generators support a maximum display size of is 8192 x 8192 pixels,
* including both active display and blanking periods. Check H Total and V Total.
*/
/*
* dce110_timing_generator_validate_timing
* The timing generators support a maximum display size of is 8192 x 8192 pixels,
* including both active display and blanking periods. Check H Total and V Total.
*/
bool dce110_timing_generator_validate_timing(
struct timing_generator *tg,
const struct dc_crtc_timing *timing,
@ -1167,9 +1166,9 @@ bool dce110_timing_generator_validate_timing(
return true;
}
/**
* Wait till we are at the beginning of VBlank.
*/
/*
* Wait till we are at the beginning of VBlank.
*/
void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg)
{
/* We want to catch beginning of VBlank here, so if the first try are
@ -1191,9 +1190,9 @@ void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg)
}
}
/**
* Wait till we are in VActive (anywhere in VActive)
*/
/*
* Wait till we are in VActive (anywhere in VActive)
*/
void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg)
{
while (dce110_timing_generator_is_in_vertical_blank(tg)) {
@ -1204,7 +1203,7 @@ void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg)
}
}
/**
/*
*****************************************************************************
* Function: dce110_timing_generator_setup_global_swap_lock
*
@ -1215,7 +1214,6 @@ void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg)
* @param [in] gsl_params: setup data
*****************************************************************************
*/
void dce110_timing_generator_setup_global_swap_lock(
struct timing_generator *tg,
const struct dcp_gsl_params *gsl_params)
@ -1351,10 +1349,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
/* Restore DCP_GSL_PURPOSE_SURFACE_FLIP */
{
uint32_t value_crtc_vtotal;
value_crtc_vtotal = dm_read_reg(tg->ctx,
CRTC_REG(mmCRTC_V_TOTAL));
dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_V_TOTAL));
set_reg_field_value(value,
0,
@ -1385,7 +1380,7 @@ void dce110_timing_generator_tear_down_global_swap_lock(
dm_write_reg(tg->ctx, address, value);
}
/**
/*
*****************************************************************************
* Function: is_counter_moving
*
@ -1767,7 +1762,7 @@ void dce110_timing_generator_disable_reset_trigger(
dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
}
/**
/*
*****************************************************************************
* @brief
* Checks whether CRTC triggered reset occurred
@ -1794,7 +1789,7 @@ bool dce110_timing_generator_did_triggered_reset_occur(
return (force || vert_sync);
}
/**
/*
* dce110_timing_generator_disable_vga
* Turn OFF VGA Mode and Timing - DxVGA_CONTROL
* VGA Mode and VGA Timing is used by VBIOS on CRT Monitors;
@ -1840,14 +1835,13 @@ void dce110_timing_generator_disable_vga(
dm_write_reg(tg->ctx, addr, value);
}
/**
* set_overscan_color_black
*
* @param :black_color is one of the color space
* :this routine will set overscan black color according to the color space.
* @return none
*/
/*
* set_overscan_color_black
*
* @param :black_color is one of the color space
* :this routine will set overscan black color according to the color space.
* @return none
*/
void dce110_timing_generator_set_overscan_color_black(
struct timing_generator *tg,
const struct tg_color *color)

19
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
View file

@ -46,17 +46,16 @@
*
**********************************************************************************/
/**
* Enable CRTCV
*/
/*
* Enable CRTCV
*/
static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
{
/*
* Set MASTER_UPDATE_MODE to 0
* This is needed for DRR, and also suggested to be default value by Syed.
*/
* Set MASTER_UPDATE_MODE to 0
* This is needed for DRR, and also suggested to be default value by Syed.
*/
uint32_t value;
value = 0;
@ -209,9 +208,9 @@ static void dce110_timing_generator_v_wait_for_vblank(struct timing_generator *t
}
}
/**
* Wait till we are in VActive (anywhere in VActive)
*/
/*
* Wait till we are in VActive (anywhere in VActive)
*/
static void dce110_timing_generator_v_wait_for_vactive(struct timing_generator *tg)
{
while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {

19
drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
View file

@ -217,16 +217,15 @@ static bool setup_scaling_configuration(
return is_scaling_needed;
}
/**
* Function:
* void program_overscan
*
* Purpose: Programs overscan border
* Input: overscan
*
* Output:
void
*/
/*
* Function:
* void program_overscan
*
* Purpose: Programs overscan border
* Input: overscan
*
* Output: void
*/
static void program_overscan(
struct dce_transform *xfm_dce,
const struct scaler_data *data)

2
drivers/gpu/drm/amd/display/dc/dce112/Makefile
View file

@ -23,6 +23,8 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
CFLAGS_$(AMDDALPATH)/dc/dce112/dce112_resource.o = $(call cc-disable-warning, override-init)
DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
dce112_resource.o

20
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View file

@ -59,7 +59,9 @@
#include "dce/dce_11_2_sh_mask.h"
#include "dce100/dce100_resource.h"
#define DC_LOGGER \
#include "dce112_resource.h"
#define DC_LOGGER \
dc->ctx->logger
#ifndef mmDP_DPHY_INTERNAL_CTRL
@ -617,7 +619,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_TPS4_CAPABLE = true
};
struct link_encoder *dce112_link_encoder_create(
static struct link_encoder *dce112_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@ -671,7 +673,7 @@ static struct input_pixel_processor *dce112_ipp_create(
return &ipp->base;
}
struct output_pixel_processor *dce112_opp_create(
static struct output_pixel_processor *dce112_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -686,7 +688,7 @@ struct output_pixel_processor *dce112_opp_create(
return &opp->base;
}
struct dce_aux *dce112_aux_engine_create(
static struct dce_aux *dce112_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -724,7 +726,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
struct dce_i2c_hw *dce112_i2c_hw_create(
static struct dce_i2c_hw *dce112_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -739,7 +741,7 @@ struct dce_i2c_hw *dce112_i2c_hw_create(
return dce_i2c_hw;
}
struct clock_source *dce112_clock_source_create(
static struct clock_source *dce112_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@ -763,7 +765,7 @@ struct clock_source *dce112_clock_source_create(
return NULL;
}
void dce112_clock_source_destroy(struct clock_source **clk_src)
static void dce112_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@ -1024,7 +1026,7 @@ enum dc_status dce112_add_stream_to_ctx(
return result;
}
enum dc_status dce112_validate_global(
static enum dc_status dce112_validate_global(
struct dc *dc,
struct dc_state *context)
{
@ -1202,7 +1204,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
}
const struct resource_caps *dce112_resource_cap(
static const struct resource_caps *dce112_resource_cap(
struct hw_asic_id *asic_id)
{
if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||

2
drivers/gpu/drm/amd/display/dc/dce120/Makefile
View file

@ -24,6 +24,8 @@
# It provides the control and status of HW CRTC block.
CFLAGS_$(AMDDALPATH)/dc/dce120/dce120_resource.o = $(call cc-disable-warning, override-init)
DCE120 = dce120_resource.o dce120_timing_generator.o \
dce120_hw_sequencer.o

2
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
View file

@ -50,6 +50,7 @@ struct dce120_hw_seq_reg_offsets {
uint32_t crtc;
};
#if 0
static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
{
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
@ -79,7 +80,6 @@ static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
/*******************************************************************************
* Private definitions
******************************************************************************/
#if 0
static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
{
uint32_t addr;

6
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View file

@ -423,7 +423,7 @@ static const struct dce110_clk_src_mask cs_mask = {
CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
};
struct output_pixel_processor *dce120_opp_create(
static struct output_pixel_processor *dce120_opp_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -437,7 +437,7 @@ struct output_pixel_processor *dce120_opp_create(
ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
return &opp->base;
}
struct dce_aux *dce120_aux_engine_create(
static struct dce_aux *dce120_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -475,7 +475,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
struct dce_i2c_hw *dce120_i2c_hw_create(
static struct dce_i2c_hw *dce120_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{

99
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
View file

@ -69,7 +69,7 @@
#define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \
CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
/**
/*
*****************************************************************************
* Function: is_in_vertical_blank
*
@ -98,7 +98,7 @@ static bool dce120_timing_generator_is_in_vertical_blank(
/* determine if given timing can be supported by TG */
bool dce120_timing_generator_validate_timing(
static bool dce120_timing_generator_validate_timing(
struct timing_generator *tg,
const struct dc_crtc_timing *timing,
enum signal_type signal)
@ -125,7 +125,7 @@ bool dce120_timing_generator_validate_timing(
return true;
}
bool dce120_tg_validate_timing(struct timing_generator *tg,
static bool dce120_tg_validate_timing(struct timing_generator *tg,
const struct dc_crtc_timing *timing)
{
return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
@ -133,7 +133,7 @@ bool dce120_tg_validate_timing(struct timing_generator *tg,
/******** HW programming ************/
/* Disable/Enable Timing Generator */
bool dce120_timing_generator_enable_crtc(struct timing_generator *tg)
static bool dce120_timing_generator_enable_crtc(struct timing_generator *tg)
{
enum bp_result result;
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -153,7 +153,7 @@ bool dce120_timing_generator_enable_crtc(struct timing_generator *tg)
return result == BP_RESULT_OK;
}
void dce120_timing_generator_set_early_control(
static void dce120_timing_generator_set_early_control(
struct timing_generator *tg,
uint32_t early_cntl)
{
@ -166,7 +166,7 @@ void dce120_timing_generator_set_early_control(
/**************** TG current status ******************/
/* return the current frame counter. Used by Linux kernel DRM */
uint32_t dce120_timing_generator_get_vblank_counter(
static uint32_t dce120_timing_generator_get_vblank_counter(
struct timing_generator *tg)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -181,7 +181,7 @@ uint32_t dce120_timing_generator_get_vblank_counter(
}
/* Get current H and V position */
void dce120_timing_generator_get_crtc_position(
static void dce120_timing_generator_get_crtc_position(
struct timing_generator *tg,
struct crtc_position *position)
{
@ -207,7 +207,7 @@ void dce120_timing_generator_get_crtc_position(
}
/* wait until TG is in beginning of vertical blank region */
void dce120_timing_generator_wait_for_vblank(struct timing_generator *tg)
static void dce120_timing_generator_wait_for_vblank(struct timing_generator *tg)
{
/* We want to catch beginning of VBlank here, so if the first try are
* in VBlank, we might be very close to Active, in this case wait for
@ -229,7 +229,7 @@ void dce120_timing_generator_wait_for_vblank(struct timing_generator *tg)
}
/* wait until TG is in beginning of active region */
void dce120_timing_generator_wait_for_vactive(struct timing_generator *tg)
static void dce120_timing_generator_wait_for_vactive(struct timing_generator *tg)
{
while (dce120_timing_generator_is_in_vertical_blank(tg)) {
if (!tg->funcs->is_counter_moving(tg)) {
@ -242,7 +242,7 @@ void dce120_timing_generator_wait_for_vactive(struct timing_generator *tg)
/*********** Timing Generator Synchronization routines ****/
/* Setups Global Swap Lock group, TimingServer or TimingClient*/
void dce120_timing_generator_setup_global_swap_lock(
static void dce120_timing_generator_setup_global_swap_lock(
struct timing_generator *tg,
const struct dcp_gsl_params *gsl_params)
{
@ -279,7 +279,7 @@ void dce120_timing_generator_setup_global_swap_lock(
}
/* Clear all the register writes done by setup_global_swap_lock */
void dce120_timing_generator_tear_down_global_swap_lock(
static void dce120_timing_generator_tear_down_global_swap_lock(
struct timing_generator *tg)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -300,7 +300,7 @@ void dce120_timing_generator_tear_down_global_swap_lock(
}
/* Reset slave controllers on master VSync */
void dce120_timing_generator_enable_reset_trigger(
static void dce120_timing_generator_enable_reset_trigger(
struct timing_generator *tg,
int source)
{
@ -347,7 +347,7 @@ void dce120_timing_generator_enable_reset_trigger(
}
/* disabling trigger-reset */
void dce120_timing_generator_disable_reset_trigger(
static void dce120_timing_generator_disable_reset_trigger(
struct timing_generator *tg)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -367,7 +367,7 @@ void dce120_timing_generator_disable_reset_trigger(
}
/* Checks whether CRTC triggered reset occurred */
bool dce120_timing_generator_did_triggered_reset_occur(
static bool dce120_timing_generator_did_triggered_reset_occur(
struct timing_generator *tg)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -384,7 +384,7 @@ bool dce120_timing_generator_did_triggered_reset_occur(
/******** Stuff to move to other virtual HW objects *****************/
/* Move to enable accelerated mode */
void dce120_timing_generator_disable_vga(struct timing_generator *tg)
static void dce120_timing_generator_disable_vga(struct timing_generator *tg)
{
uint32_t offset = 0;
uint32_t value = 0;
@ -425,7 +425,7 @@ void dce120_timing_generator_disable_vga(struct timing_generator *tg)
}
/* TODO: Should we move it to transform */
/* Fully program CRTC timing in timing generator */
void dce120_timing_generator_program_blanking(
static void dce120_timing_generator_program_blanking(
struct timing_generator *tg,
const struct dc_crtc_timing *timing)
{
@ -485,7 +485,7 @@ void dce120_timing_generator_program_blanking(
/* TODO: Should we move it to opp? */
/* Combine with below and move YUV/RGB color conversion to SW layer */
void dce120_timing_generator_program_blank_color(
static void dce120_timing_generator_program_blank_color(
struct timing_generator *tg,
const struct tg_color *black_color)
{
@ -498,7 +498,7 @@ void dce120_timing_generator_program_blank_color(
CRTC_BLACK_COLOR_R_CR, black_color->color_r_cr);
}
/* Combine with above and move YUV/RGB color conversion to SW layer */
void dce120_timing_generator_set_overscan_color_black(
static void dce120_timing_generator_set_overscan_color_black(
struct timing_generator *tg,
const struct tg_color *color)
{
@ -540,7 +540,7 @@ void dce120_timing_generator_set_overscan_color_black(
*/
}
void dce120_timing_generator_set_drr(
static void dce120_timing_generator_set_drr(
struct timing_generator *tg,
const struct drr_params *params)
{
@ -589,50 +589,7 @@ void dce120_timing_generator_set_drr(
}
}
/**
*****************************************************************************
* Function: dce120_timing_generator_get_position
*
* @brief
* Returns CRTC vertical/horizontal counters
*
* @param [out] position
*****************************************************************************
*/
void dce120_timing_generator_get_position(struct timing_generator *tg,
struct crtc_position *position)
{
uint32_t value;
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
value = dm_read_reg_soc15(
tg->ctx,
mmCRTC0_CRTC_STATUS_POSITION,
tg110->offsets.crtc);
position->horizontal_count = get_reg_field_value(
value,
CRTC0_CRTC_STATUS_POSITION,
CRTC_HORZ_COUNT);
position->vertical_count = get_reg_field_value(
value,
CRTC0_CRTC_STATUS_POSITION,
CRTC_VERT_COUNT);
value = dm_read_reg_soc15(
tg->ctx,
mmCRTC0_CRTC_NOM_VERT_POSITION,
tg110->offsets.crtc);
position->nominal_vcount = get_reg_field_value(
value,
CRTC0_CRTC_NOM_VERT_POSITION,
CRTC_VERT_COUNT_NOM);
}
void dce120_timing_generator_get_crtc_scanoutpos(
static void dce120_timing_generator_get_crtc_scanoutpos(
struct timing_generator *tg,
uint32_t *v_blank_start,
uint32_t *v_blank_end,
@ -661,7 +618,7 @@ void dce120_timing_generator_get_crtc_scanoutpos(
*v_position = position.vertical_count;
}
void dce120_timing_generator_enable_advanced_request(
static void dce120_timing_generator_enable_advanced_request(
struct timing_generator *tg,
bool enable,
const struct dc_crtc_timing *timing)
@ -699,7 +656,7 @@ void dce120_timing_generator_enable_advanced_request(
value);
}
void dce120_tg_program_blank_color(struct timing_generator *tg,
static void dce120_tg_program_blank_color(struct timing_generator *tg,
const struct tg_color *black_color)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -722,7 +679,7 @@ void dce120_tg_program_blank_color(struct timing_generator *tg,
value);
}
void dce120_tg_set_overscan_color(struct timing_generator *tg,
static void dce120_tg_set_overscan_color(struct timing_generator *tg,
const struct tg_color *overscan_color)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -749,7 +706,7 @@ static void dce120_tg_program_timing(struct timing_generator *tg,
dce120_timing_generator_program_blanking(tg, timing);
}
bool dce120_tg_is_blanked(struct timing_generator *tg)
static bool dce120_tg_is_blanked(struct timing_generator *tg)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t value = dm_read_reg_soc15(
@ -770,7 +727,7 @@ bool dce120_tg_is_blanked(struct timing_generator *tg)
return false;
}
void dce120_tg_set_blank(struct timing_generator *tg,
static void dce120_tg_set_blank(struct timing_generator *tg,
bool enable_blanking)
{
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
@ -789,7 +746,7 @@ void dce120_tg_set_blank(struct timing_generator *tg,
bool dce120_tg_validate_timing(struct timing_generator *tg,
const struct dc_crtc_timing *timing);
void dce120_tg_wait_for_state(struct timing_generator *tg,
static void dce120_tg_wait_for_state(struct timing_generator *tg,
enum crtc_state state)
{
switch (state) {
@ -806,7 +763,7 @@ void dce120_tg_wait_for_state(struct timing_generator *tg,
}
}
void dce120_tg_set_colors(struct timing_generator *tg,
static void dce120_tg_set_colors(struct timing_generator *tg,
const struct tg_color *blank_color,
const struct tg_color *overscan_color)
{
@ -833,7 +790,7 @@ static void dce120_timing_generator_set_static_screen_control(
CRTC_STATIC_SCREEN_FRAME_COUNT, num_frames);
}
void dce120_timing_generator_set_test_pattern(
static void dce120_timing_generator_set_test_pattern(
struct timing_generator *tg,
/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
* because this is not DP-specific (which is probably somewhere in DP

2
drivers/gpu/drm/amd/display/dc/dce60/Makefile
View file

@ -23,6 +23,8 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
CFLAGS_AMDDALPATH)/dc/dce60/dce60_resource.o = $(call cc-disable-warning, override-init)
DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
dce60_resource.o

18
drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
View file

@ -60,6 +60,8 @@
#include "dce/dce_i2c.h"
/* TODO remove this include */
#include "dce60_resource.h"
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_6_0_d.h"
#include "gmc/gmc_6_0_sh_mask.h"
@ -519,7 +521,7 @@ static struct output_pixel_processor *dce60_opp_create(
return &opp->base;
}
struct dce_aux *dce60_aux_engine_create(
static struct dce_aux *dce60_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -557,7 +559,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
struct dce_i2c_hw *dce60_i2c_hw_create(
static struct dce_i2c_hw *dce60_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst)
{
@ -573,7 +575,7 @@ struct dce_i2c_hw *dce60_i2c_hw_create(
return dce_i2c_hw;
}
struct dce_i2c_sw *dce60_i2c_sw_create(
static struct dce_i2c_sw *dce60_i2c_sw_create(
struct dc_context *ctx)
{
struct dce_i2c_sw *dce_i2c_sw =
@ -707,7 +709,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_TPS3_CAPABLE = true
};
struct link_encoder *dce60_link_encoder_create(
static struct link_encoder *dce60_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dce110_link_encoder *enc110 =
@ -746,7 +748,7 @@ static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_d
return &panel_cntl->base;
}
struct clock_source *dce60_clock_source_create(
static struct clock_source *dce60_clock_source_create(
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
@ -770,7 +772,7 @@ struct clock_source *dce60_clock_source_create(
return NULL;
}
void dce60_clock_source_destroy(struct clock_source **clk_src)
static void dce60_clock_source_destroy(struct clock_source **clk_src)
{
kfree(TO_DCE110_CLK_SRC(*clk_src));
*clk_src = NULL;
@ -860,7 +862,7 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool)
}
}
bool dce60_validate_bandwidth(
static bool dce60_validate_bandwidth(
struct dc *dc,
struct dc_state *context,
bool fast_validate)
@ -905,7 +907,7 @@ static bool dce60_validate_surface_sets(
return true;
}
enum dc_status dce60_validate_global(
static enum dc_status dce60_validate_global(
struct dc *dc,
struct dc_state *context)
{

4
drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
View file

@ -189,8 +189,8 @@ static bool dce60_is_tg_enabled(struct timing_generator *tg)
return field == 1;
}
bool dce60_configure_crc(struct timing_generator *tg,
const struct crc_params *params)
static bool dce60_configure_crc(struct timing_generator *tg,
const struct crc_params *params)
{
/* Cannot configure crc on a CRTC that is disabled */
if (!dce60_is_tg_enabled(tg))

2
drivers/gpu/drm/amd/display/dc/dce80/Makefile
View file

@ -23,6 +23,8 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
CFLAGS_$(AMDDALPATH)/dc/dce80/dce80_resource.o = $(call cc-disable-warning, override-init)
DCE80 = dce80_timing_generator.o dce80_hw_sequencer.o \
dce80_resource.o

2
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View file

@ -60,6 +60,8 @@
#include "dce/dce_i2c.h"
/* TODO remove this include */
#include "dce80_resource.h"
#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_7_1_d.h"
#include "gmc/gmc_7_1_sh_mask.h"

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
View file

@ -577,7 +577,7 @@ void dpp1_power_on_degamma_lut(
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
REG_SET(CM_MEM_PWR_CTRL, 0,
SHARED_MEM_PWR_DIS, power_on == true ? 0:1);
SHARED_MEM_PWR_DIS, power_on ? 0:1);
}

36
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View file

@ -2624,7 +2624,7 @@ static void dcn10_update_dchubp_dpp(
hws->funcs.update_plane_addr(dc, pipe_ctx);
if (is_pipe_tree_visible(pipe_ctx))
hubp->funcs->set_blank(hubp, false);
dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
}
void dcn10_blank_pixel_data(
@ -3135,13 +3135,16 @@ void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
return;
}
static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
static struct pipe_ctx *get_pipe_ctx_by_hubp_inst(struct dc_state *context, int mpcc_inst)
{
int i;
for (i = 0; i < res_pool->pipe_count; i++) {
if (res_pool->hubps[i]->inst == mpcc_inst)
return res_pool->hubps[i];
for (i = 0; i < MAX_PIPES; i++) {
if (context->res_ctx.pipe_ctx[i].plane_res.hubp
&& context->res_ctx.pipe_ctx[i].plane_res.hubp->inst == mpcc_inst) {
return &context->res_ctx.pipe_ctx[i];
}
}
ASSERT(false);
return NULL;
@ -3164,11 +3167,23 @@ void dcn10_wait_for_mpcc_disconnect(
for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
struct pipe_ctx *restore_bottom_pipe;
struct pipe_ctx *restore_top_pipe;
struct pipe_ctx *inst_pipe_ctx = get_pipe_ctx_by_hubp_inst(dc->current_state, mpcc_inst);
ASSERT(inst_pipe_ctx);
res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
hubp->funcs->set_blank(hubp, true);
/*
* Set top and bottom pipes NULL, as we don't want
* to blank those pipes when disconnecting from MPCC
*/
restore_bottom_pipe = inst_pipe_ctx->bottom_pipe;
restore_top_pipe = inst_pipe_ctx->top_pipe;
inst_pipe_ctx->top_pipe = inst_pipe_ctx->bottom_pipe = NULL;
dc->hwss.set_hubp_blank(dc, inst_pipe_ctx, true);
inst_pipe_ctx->top_pipe = restore_top_pipe;
inst_pipe_ctx->bottom_pipe = restore_bottom_pipe;
}
}
@ -3721,3 +3736,10 @@ void dcn10_get_clock(struct dc *dc,
dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
}
void dcn10_set_hubp_blank(const struct dc *dc,
struct pipe_ctx *pipe_ctx,
bool blank_enable)
{
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, blank_enable);
}

5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
View file

@ -163,6 +163,8 @@ void dcn10_wait_for_mpcc_disconnect(
void dce110_edp_backlight_control(
struct dc_link *link,
bool enable);
void dce110_edp_wait_for_T12(
struct dc_link *link);
void dce110_edp_power_control(
struct dc_link *link,
bool power_up);
@ -202,5 +204,8 @@ void dcn10_wait_for_pending_cleared(struct dc *dc,
struct dc_state *context);
void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
void dcn10_verify_allow_pstate_change_high(struct dc *dc);
void dcn10_set_hubp_blank(const struct dc *dc,
struct pipe_ctx *pipe_ctx,
bool blank_enable);
#endif /* __DC_HWSS_DCN10_H__ */

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
View file

@ -79,6 +79,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.set_backlight_level = dce110_set_backlight_level,
.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
.set_pipe = dce110_set_pipe,
.set_hubp_blank = dcn10_set_hubp_blank,
};
static const struct hwseq_private_funcs dcn10_private_funcs = {

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
View file

@ -470,7 +470,7 @@ void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
uint32_t val = 0;
uint32_t val = 0xf;
if (opp_id < MAX_OPP && REG(MUX[opp_id]))
REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);

11
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
View file

@ -659,6 +659,16 @@ void optc1_unlock(struct timing_generator *optc)
OTG_MASTER_UPDATE_LOCK, 0);
}
bool optc1_is_locked(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t locked;
REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked);
return (locked == 1);
}
void optc1_get_position(struct timing_generator *optc,
struct crtc_position *position)
{
@ -1513,6 +1523,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
.enable_crtc_reset = optc1_enable_crtc_reset,
.disable_reset_trigger = optc1_disable_reset_trigger,
.lock = optc1_lock,
.is_locked = optc1_is_locked,
.unlock = optc1_unlock,
.enable_optc_clock = optc1_enable_optc_clock,
.set_drr = optc1_set_drr,

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
View file

@ -638,6 +638,7 @@ void optc1_set_blank(struct timing_generator *optc,
bool enable_blanking);
bool optc1_is_blanked(struct timing_generator *optc);
bool optc1_is_locked(struct timing_generator *optc);
void optc1_program_blank_color(
struct timing_generator *optc,

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View file

@ -608,8 +608,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_pplib_clock_request = false,
.disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,
.force_single_disp_pipe_split = true,
.pipe_split_policy = MPC_SPLIT_AVOID,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.voltage_align_fclk = true,
.disable_stereo_support = true,

12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View file

@ -1570,8 +1570,8 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.enable)
hubp->funcs->set_blank(hubp, false);
if (is_pipe_tree_visible(pipe_ctx))
dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
}
@ -1765,6 +1765,14 @@ void dcn20_post_unlock_program_front_end(
}
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
if (pipe->vtp_locked) {
dc->hwss.set_hubp_blank(dc, pipe, true);
pipe->vtp_locked = false;
}
}
/* WA to apply WM setting*/
if (hwseq->wa.DEGVIDCN21)
dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
View file

@ -94,6 +94,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
#endif
.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
.set_hubp_blank = dcn10_set_hubp_blank,
};
static const struct hwseq_private_funcs dcn20_private_funcs = {

1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
View file

@ -99,6 +99,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
#endif
.is_abm_supported = dcn21_is_abm_supported,
.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
.set_hubp_blank = dcn10_set_hubp_blank,
};
static const struct hwseq_private_funcs dcn21_private_funcs = {

7
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c
View file

@ -133,7 +133,6 @@ static void dpp3_power_on_gamcor_lut(
struct dpp *dpp_base,
bool power_on)
{
uint32_t power_status;
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
@ -143,12 +142,6 @@ static void dpp3_power_on_gamcor_lut(
} else
REG_SET(CM_MEM_PWR_CTRL, 0,
GAMCOR_MEM_PWR_DIS, power_on == true ? 0:1);
REG_GET(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, &power_status);
if (power_status != 0)
BREAK_TO_DEBUGGER();
}
void dpp3_program_cm_dealpha(

1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
View file

@ -62,6 +62,7 @@
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\

70
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View file

@ -836,6 +836,53 @@ void dcn30_hardware_release(struct dc *dc)
dc->res_pool->hubbub, true, true);
}
void dcn30_set_hubp_blank(const struct dc *dc,
struct pipe_ctx *pipe_ctx,
bool blank_enable)
{
struct pipe_ctx *mpcc_pipe;
struct pipe_ctx *odm_pipe;
if (blank_enable) {
struct plane_resource *plane_res = &pipe_ctx->plane_res;
struct stream_resource *stream_res = &pipe_ctx->stream_res;
/* Wait for enter vblank */
stream_res->tg->funcs->wait_for_state(stream_res->tg, CRTC_STATE_VBLANK);
/* Blank HUBP to allow p-state during blank on all timings */
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true);
/* Confirm hubp in blank */
ASSERT(plane_res->hubp->funcs->hubp_in_blank(plane_res->hubp));
/* Toggle HUBP_DISABLE */
plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, true);
plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, false);
for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) {
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true);
/* Confirm hubp in blank */
ASSERT(mpcc_pipe->plane_res.hubp->funcs->hubp_in_blank(mpcc_pipe->plane_res.hubp));
/* Toggle HUBP_DISABLE */
mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, true);
mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, false);
}
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, true);
/* Confirm hubp in blank */
ASSERT(odm_pipe->plane_res.hubp->funcs->hubp_in_blank(odm_pipe->plane_res.hubp));
/* Toggle HUBP_DISABLE */
odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, true);
odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, false);
}
} else {
pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false);
for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false);
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, false);
}
}
void dcn30_set_disp_pattern_generator(const struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum controller_dp_test_pattern test_pattern,
@ -844,6 +891,25 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
const struct tg_color *solid_color,
int width, int height, int offset)
{
pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
color_space, color_depth, solid_color, width, height, offset);
struct stream_resource *stream_res = &pipe_ctx->stream_res;
if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {
pipe_ctx->vtp_locked = false;
/* turning on DPG */
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
color_depth, solid_color, width, height, offset);
/* Defer hubp blank if tg is locked */
if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) {
if (stream_res->tg->funcs->is_locked(stream_res->tg))
pipe_ctx->vtp_locked = true;
else
dc->hwss.set_hubp_blank(dc, pipe_ctx, true);
}
} else {
dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
/* turning off DPG */
stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,
color_depth, solid_color, width, height, offset);
}
}

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