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soundwire: qcom: add auto enumeration support

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Qualcomm SoundWire controller supports Auto Enumeration of the
devices within the IP. This patch enables support for this feature.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20210330144719.13284-9-srinivas.kandagatla@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Srinivas Kandagatla 2021-03-30 15:47:18 +01:00 committed by Vinod Koul
parent 01ad444e3b
commit a6e6581942
1 changed files with 81 additions and 5 deletions
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86
drivers/soundwire/qcom.c
View file

@ -57,6 +57,8 @@
#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
#define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
#define SWRM_ENUMERATOR_CFG_ADDR 0x500
#define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
#define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
@ -143,6 +145,7 @@ struct qcom_swrm_ctrl {
enum sdw_slave_status status[SDW_MAX_DEVICES];
int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
u32 slave_status;
};
struct qcom_swrm_data {
@ -343,6 +346,7 @@ static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
int i;
ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
ctrl->slave_status = val;
for (i = 0; i < SDW_MAX_DEVICES; i++) {
u32 s;
@ -353,10 +357,74 @@ static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
}
}
static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
struct sdw_slave *slave, int devnum)
{
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
u32 status;
ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
status &= SWRM_MCP_SLV_STATUS_MASK;
if (status == SDW_SLAVE_ATTACHED) {
if (slave)
slave->dev_num = devnum;
mutex_lock(&bus->bus_lock);
set_bit(devnum, bus->assigned);
mutex_unlock(&bus->bus_lock);
}
}
static int qcom_swrm_enumerate(struct sdw_bus *bus)
{
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
struct sdw_slave *slave, *_s;
struct sdw_slave_id id;
u32 val1, val2;
bool found;
u64 addr;
int i;
char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
for (i = 1; i <= SDW_MAX_DEVICES; i++) {
/*SCP_Devid5 - Devid 4*/
ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
/*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
if (!val1 && !val2)
break;
addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
((u64)buf1[0] << 40);
sdw_extract_slave_id(bus, addr, &id);
found = false;
/* Now compare with entries */
list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
if (sdw_compare_devid(slave, id) == 0) {
qcom_swrm_set_slave_dev_num(bus, slave, i);
found = true;
break;
}
}
if (!found) {
qcom_swrm_set_slave_dev_num(bus, NULL, i);
sdw_slave_add(bus, &id, NULL);
}
}
return 0;
}
static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
{
struct qcom_swrm_ctrl *swrm = dev_id;
u32 value, intr_sts, intr_sts_masked;
u32 value, intr_sts, intr_sts_masked, slave_status;
u32 i;
u8 devnum = 0;
int ret = IRQ_HANDLED;
@ -385,8 +453,15 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
__func__);
qcom_swrm_get_device_status(swrm);
sdw_handle_slave_status(&swrm->bus, swrm->status);
swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
if (swrm->slave_status == slave_status) {
dev_err(swrm->dev, "Slave status not changed %x\n",
slave_status);
} else {
qcom_swrm_get_device_status(swrm);
qcom_swrm_enumerate(&swrm->bus);
sdw_handle_slave_status(&swrm->bus, swrm->status);
}
break;
case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
dev_err_ratelimited(swrm->dev,
@ -473,8 +548,8 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
/* Disable Auto enumeration */
ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);
/* Enable Auto enumeration */
ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
/* Mask soundwire interrupts */
@ -508,6 +583,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
SWRM_INTERRUPT_STATUS_RMSK);
}
ctrl->slave_status = 0;
return 0;
}