[PATCH] md: RAID6: clean up CPUID and FPU enter/exit code
- Use kernel_fpu_begin() and kernel_fpu_end() - Use boot_cpu_has() for feature testing even in userspace Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Neil Brown <neilb@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
H. Peter Anvin
Linus Torvalds
parent
64a742bc61
commit
a723406c4a
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@ -30,14 +30,8 @@ const struct raid6_mmx_constants {
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static int raid6_have_mmx(void)
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{
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#ifdef __KERNEL__
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/* Not really "boot_cpu" but "all_cpus" */
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return boot_cpu_has(X86_FEATURE_MMX);
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#else
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/* User space test code */
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u32 features = cpuid_features();
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return ( (features & (1<<23)) == (1<<23) );
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#endif
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}
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/*
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@ -48,13 +42,12 @@ static void raid6_mmx1_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_mmx_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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raid6_before_mmx(&sa);
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kernel_fpu_begin();
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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@ -78,7 +71,7 @@ static void raid6_mmx1_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("pxor %mm4,%mm4");
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}
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raid6_after_mmx(&sa);
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_mmxx1 = {
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@ -96,13 +89,12 @@ static void raid6_mmx2_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_mmx_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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raid6_before_mmx(&sa);
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kernel_fpu_begin();
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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@ -137,7 +129,7 @@ static void raid6_mmx2_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("movq %%mm6,%0" : "=m" (q[d+8]));
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}
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raid6_after_mmx(&sa);
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_mmxx2 = {
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@ -33,16 +33,10 @@ extern const struct raid6_mmx_constants {
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static int raid6_have_sse1_or_mmxext(void)
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{
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#ifdef __KERNEL__
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/* Not really boot_cpu but "all_cpus" */
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return boot_cpu_has(X86_FEATURE_MMX) &&
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(boot_cpu_has(X86_FEATURE_XMM) ||
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boot_cpu_has(X86_FEATURE_MMXEXT));
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#else
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/* User space test code - this incorrectly breaks on some Athlons */
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u32 features = cpuid_features();
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return ( (features & (5<<23)) == (5<<23) );
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#endif
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}
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/*
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@ -53,14 +47,12 @@ static void raid6_sse11_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_mmx_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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/* This is really MMX code, not SSE */
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raid6_before_mmx(&sa);
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kernel_fpu_begin();
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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@ -94,8 +86,8 @@ static void raid6_sse11_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("movntq %%mm4,%0" : "=m" (q[d]));
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}
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raid6_after_mmx(&sa);
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse1x1 = {
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@ -113,13 +105,12 @@ static void raid6_sse12_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_mmx_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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raid6_before_mmx(&sa);
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kernel_fpu_begin();
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asm volatile("movq %0,%%mm0" : : "m" (raid6_mmx_constants.x1d));
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asm volatile("pxor %mm5,%mm5"); /* Zero temp */
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@ -157,8 +148,8 @@ static void raid6_sse12_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("movntq %%mm6,%0" : "=m" (q[d+8]));
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}
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raid6_after_mmx(&sa);
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asm volatile("sfence" : :: "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse1x2 = {
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@ -30,17 +30,11 @@ static const struct raid6_sse_constants {
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static int raid6_have_sse2(void)
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{
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#ifdef __KERNEL__
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/* Not really boot_cpu but "all_cpus" */
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return boot_cpu_has(X86_FEATURE_MMX) &&
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boot_cpu_has(X86_FEATURE_FXSR) &&
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boot_cpu_has(X86_FEATURE_XMM) &&
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boot_cpu_has(X86_FEATURE_XMM2);
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#else
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/* User space test code */
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u32 features = cpuid_features();
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return ( (features & (15<<23)) == (15<<23) );
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#endif
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}
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/*
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@ -51,13 +45,12 @@ static void raid6_sse21_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_sse_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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raid6_before_sse2(&sa);
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kernel_fpu_begin();
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asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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@ -93,8 +86,8 @@ static void raid6_sse21_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("pxor %xmm4,%xmm4");
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}
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raid6_after_sse2(&sa);
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse2x1 = {
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@ -112,13 +105,12 @@ static void raid6_sse22_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_sse_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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raid6_before_sse2(&sa);
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kernel_fpu_begin();
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asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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@ -156,8 +148,8 @@ static void raid6_sse22_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("movntdq %%xmm6,%0" : "=m" (q[d+16]));
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}
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raid6_after_sse2(&sa);
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse2x2 = {
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@ -179,13 +171,12 @@ static void raid6_sse24_gen_syndrome(int disks, size_t bytes, void **ptrs)
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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raid6_sse16_save_t sa;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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raid6_before_sse16(&sa);
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kernel_fpu_begin();
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asm volatile("movdqa %0,%%xmm0" :: "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm2,%xmm2"); /* P[0] */
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@ -256,8 +247,9 @@ static void raid6_sse24_gen_syndrome(int disks, size_t bytes, void **ptrs)
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asm volatile("movntdq %%xmm14,%0" : "=m" (q[d+48]));
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asm volatile("pxor %xmm14,%xmm14");
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}
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asm volatile("sfence" : : : "memory");
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raid6_after_sse16(&sa);
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse2x4 = {
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@ -21,224 +21,40 @@
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#if defined(__i386__) || defined(__x86_64__)
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#ifdef __x86_64__
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typedef struct {
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unsigned int fsave[27];
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unsigned long cr0;
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} raid6_mmx_save_t __attribute__((aligned(16)));
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/* N.B.: For SSE we only save %xmm0-%xmm7 even for x86-64, since
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the code doesn't know about the additional x86-64 registers */
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typedef struct {
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unsigned int sarea[8*4+2];
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unsigned long cr0;
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} raid6_sse_save_t __attribute__((aligned(16)));
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/* This is for x86-64-specific code which uses all 16 XMM registers */
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typedef struct {
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unsigned int sarea[16*4+2];
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unsigned long cr0;
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} raid6_sse16_save_t __attribute__((aligned(16)));
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/* On x86-64 the stack *SHOULD* be 16-byte aligned, but currently this
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is buggy in the kernel and it's only 8-byte aligned in places, so
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we need to do this anyway. Sigh. */
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#define SAREA(x) ((unsigned int *)((((unsigned long)&(x)->sarea)+15) & ~15))
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#else /* __i386__ */
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typedef struct {
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unsigned int fsave[27];
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unsigned long cr0;
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} raid6_mmx_save_t;
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/* On i386, the stack is only 8-byte aligned, but SSE requires 16-byte
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alignment. The +3 is so we have the slack space to manually align
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a properly-sized area correctly. */
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typedef struct {
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unsigned int sarea[8*4+3];
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unsigned long cr0;
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} raid6_sse_save_t;
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/* Find the 16-byte aligned save area */
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#define SAREA(x) ((unsigned int *)((((unsigned long)&(x)->sarea)+15) & ~15))
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#endif
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#ifdef __KERNEL__ /* Real code */
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/* Note: %cr0 is 32 bits on i386 and 64 bits on x86-64 */
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static inline unsigned long raid6_get_fpu(void)
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{
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unsigned long cr0;
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preempt_disable();
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asm volatile("mov %%cr0,%0 ; clts" : "=r" (cr0));
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return cr0;
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}
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static inline void raid6_put_fpu(unsigned long cr0)
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{
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asm volatile("mov %0,%%cr0" : : "r" (cr0));
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preempt_enable();
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}
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#include <asm/i387.h>
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#else /* Dummy code for user space testing */
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static inline unsigned long raid6_get_fpu(void)
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static inline void kernel_fpu_begin(void)
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{
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return 0xf00ba6;
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}
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static inline void raid6_put_fpu(unsigned long cr0)
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static inline void kernel_fpu_end(void)
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{
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(void)cr0;
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}
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#endif
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#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions
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* (fast save and restore) */
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#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
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static inline void raid6_before_mmx(raid6_mmx_save_t *s)
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/* Should work well enough on modern CPUs for testing */
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static inline int boot_cpu_has(int flag)
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{
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s->cr0 = raid6_get_fpu();
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asm volatile("fsave %0 ; fwait" : "=m" (s->fsave[0]));
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u32 eax = (flag >> 5) ? 0x80000001 : 1;
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u32 edx;
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asm volatile("cpuid"
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: "+a" (eax), "=d" (edx)
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: : "ecx", "ebx");
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return (edx >> (flag & 31)) & 1;
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}
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static inline void raid6_after_mmx(raid6_mmx_save_t *s)
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{
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asm volatile("frstor %0" : : "m" (s->fsave[0]));
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raid6_put_fpu(s->cr0);
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}
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static inline void raid6_before_sse(raid6_sse_save_t *s)
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{
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unsigned int *rsa = SAREA(s);
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s->cr0 = raid6_get_fpu();
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asm volatile("movaps %%xmm0,%0" : "=m" (rsa[0]));
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asm volatile("movaps %%xmm1,%0" : "=m" (rsa[4]));
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asm volatile("movaps %%xmm2,%0" : "=m" (rsa[8]));
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asm volatile("movaps %%xmm3,%0" : "=m" (rsa[12]));
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asm volatile("movaps %%xmm4,%0" : "=m" (rsa[16]));
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asm volatile("movaps %%xmm5,%0" : "=m" (rsa[20]));
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asm volatile("movaps %%xmm6,%0" : "=m" (rsa[24]));
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asm volatile("movaps %%xmm7,%0" : "=m" (rsa[28]));
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}
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static inline void raid6_after_sse(raid6_sse_save_t *s)
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{
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unsigned int *rsa = SAREA(s);
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asm volatile("movaps %0,%%xmm0" : : "m" (rsa[0]));
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asm volatile("movaps %0,%%xmm1" : : "m" (rsa[4]));
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asm volatile("movaps %0,%%xmm2" : : "m" (rsa[8]));
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asm volatile("movaps %0,%%xmm3" : : "m" (rsa[12]));
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asm volatile("movaps %0,%%xmm4" : : "m" (rsa[16]));
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asm volatile("movaps %0,%%xmm5" : : "m" (rsa[20]));
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asm volatile("movaps %0,%%xmm6" : : "m" (rsa[24]));
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asm volatile("movaps %0,%%xmm7" : : "m" (rsa[28]));
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raid6_put_fpu(s->cr0);
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}
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static inline void raid6_before_sse2(raid6_sse_save_t *s)
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{
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unsigned int *rsa = SAREA(s);
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s->cr0 = raid6_get_fpu();
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asm volatile("movdqa %%xmm0,%0" : "=m" (rsa[0]));
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asm volatile("movdqa %%xmm1,%0" : "=m" (rsa[4]));
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asm volatile("movdqa %%xmm2,%0" : "=m" (rsa[8]));
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asm volatile("movdqa %%xmm3,%0" : "=m" (rsa[12]));
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asm volatile("movdqa %%xmm4,%0" : "=m" (rsa[16]));
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asm volatile("movdqa %%xmm5,%0" : "=m" (rsa[20]));
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asm volatile("movdqa %%xmm6,%0" : "=m" (rsa[24]));
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asm volatile("movdqa %%xmm7,%0" : "=m" (rsa[28]));
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}
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static inline void raid6_after_sse2(raid6_sse_save_t *s)
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{
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unsigned int *rsa = SAREA(s);
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asm volatile("movdqa %0,%%xmm0" : : "m" (rsa[0]));
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asm volatile("movdqa %0,%%xmm1" : : "m" (rsa[4]));
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asm volatile("movdqa %0,%%xmm2" : : "m" (rsa[8]));
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asm volatile("movdqa %0,%%xmm3" : : "m" (rsa[12]));
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asm volatile("movdqa %0,%%xmm4" : : "m" (rsa[16]));
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asm volatile("movdqa %0,%%xmm5" : : "m" (rsa[20]));
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asm volatile("movdqa %0,%%xmm6" : : "m" (rsa[24]));
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asm volatile("movdqa %0,%%xmm7" : : "m" (rsa[28]));
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raid6_put_fpu(s->cr0);
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}
|
||||
|
||||
#ifdef __x86_64__
|
||||
|
||||
static inline void raid6_before_sse16(raid6_sse16_save_t *s)
|
||||
{
|
||||
unsigned int *rsa = SAREA(s);
|
||||
|
||||
s->cr0 = raid6_get_fpu();
|
||||
|
||||
asm volatile("movdqa %%xmm0,%0" : "=m" (rsa[0]));
|
||||
asm volatile("movdqa %%xmm1,%0" : "=m" (rsa[4]));
|
||||
asm volatile("movdqa %%xmm2,%0" : "=m" (rsa[8]));
|
||||
asm volatile("movdqa %%xmm3,%0" : "=m" (rsa[12]));
|
||||
asm volatile("movdqa %%xmm4,%0" : "=m" (rsa[16]));
|
||||
asm volatile("movdqa %%xmm5,%0" : "=m" (rsa[20]));
|
||||
asm volatile("movdqa %%xmm6,%0" : "=m" (rsa[24]));
|
||||
asm volatile("movdqa %%xmm7,%0" : "=m" (rsa[28]));
|
||||
asm volatile("movdqa %%xmm8,%0" : "=m" (rsa[32]));
|
||||
asm volatile("movdqa %%xmm9,%0" : "=m" (rsa[36]));
|
||||
asm volatile("movdqa %%xmm10,%0" : "=m" (rsa[40]));
|
||||
asm volatile("movdqa %%xmm11,%0" : "=m" (rsa[44]));
|
||||
asm volatile("movdqa %%xmm12,%0" : "=m" (rsa[48]));
|
||||
asm volatile("movdqa %%xmm13,%0" : "=m" (rsa[52]));
|
||||
asm volatile("movdqa %%xmm14,%0" : "=m" (rsa[56]));
|
||||
asm volatile("movdqa %%xmm15,%0" : "=m" (rsa[60]));
|
||||
}
|
||||
|
||||
static inline void raid6_after_sse16(raid6_sse16_save_t *s)
|
||||
{
|
||||
unsigned int *rsa = SAREA(s);
|
||||
|
||||
asm volatile("movdqa %0,%%xmm0" : : "m" (rsa[0]));
|
||||
asm volatile("movdqa %0,%%xmm1" : : "m" (rsa[4]));
|
||||
asm volatile("movdqa %0,%%xmm2" : : "m" (rsa[8]));
|
||||
asm volatile("movdqa %0,%%xmm3" : : "m" (rsa[12]));
|
||||
asm volatile("movdqa %0,%%xmm4" : : "m" (rsa[16]));
|
||||
asm volatile("movdqa %0,%%xmm5" : : "m" (rsa[20]));
|
||||
asm volatile("movdqa %0,%%xmm6" : : "m" (rsa[24]));
|
||||
asm volatile("movdqa %0,%%xmm7" : : "m" (rsa[28]));
|
||||
asm volatile("movdqa %0,%%xmm8" : : "m" (rsa[32]));
|
||||
asm volatile("movdqa %0,%%xmm9" : : "m" (rsa[36]));
|
||||
asm volatile("movdqa %0,%%xmm10" : : "m" (rsa[40]));
|
||||
asm volatile("movdqa %0,%%xmm11" : : "m" (rsa[44]));
|
||||
asm volatile("movdqa %0,%%xmm12" : : "m" (rsa[48]));
|
||||
asm volatile("movdqa %0,%%xmm13" : : "m" (rsa[52]));
|
||||
asm volatile("movdqa %0,%%xmm14" : : "m" (rsa[56]));
|
||||
asm volatile("movdqa %0,%%xmm15" : : "m" (rsa[60]));
|
||||
|
||||
raid6_put_fpu(s->cr0);
|
||||
}
|
||||
|
||||
#endif /* __x86_64__ */
|
||||
|
||||
/* User space test hack */
|
||||
#ifndef __KERNEL__
|
||||
static inline int cpuid_features(void)
|
||||
{
|
||||
u32 eax = 1;
|
||||
u32 ebx, ecx, edx;
|
||||
|
||||
asm volatile("cpuid" :
|
||||
"+a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx));
|
||||
|
||||
return edx;
|
||||
}
|
||||
#endif /* ndef __KERNEL__ */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue