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[MIPS] Sibyte: resurrect old cache hack.
The recent switch of the Sibyte SOCs from the processor specific cache managment code in c-sb1.c to c-r4k.c lost this old hack [MIPS] Hack for SB1 cache issues Removing flush_icache_page a while ago broke SB1 which was using an empty flush_data_cache_page function. This glues things well enough so a more efficient but also more intrusive solution can be found later. Signed-Off-By: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> in the hope it was no longer needed. As it turns it still is so resurrect it until there is a better solution. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 6 additions and 1 deletions
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@ -7,6 +7,7 @@
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* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <linux/kernel.h>
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@ -507,7 +508,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
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static void r4k_flush_data_cache_page(unsigned long addr)
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{
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r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
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if (in_atomic())
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local_r4k_flush_data_cache_page((void *)addr);
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else
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r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
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1, 1);
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}
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struct flush_icache_range_args {
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