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Linux 5.5-rc7 

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Merge tag 'v5.5-rc7' into efi/core, to pick up fixes

Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar 2020-01-20 08:05:16 +01:00
parent 4444f8541d def9d27807
commit a786810cc8
375 changed files with 2865 additions and 2484 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.mailmap
View File

@ -99,6 +99,7 @@ Jacob Shin <Jacob.Shin@amd.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@motorola.com>
Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
Jakub Kicinski <kuba@kernel.org> <jakub.kicinski@netronome.com>
James Bottomley <jejb@mulgrave.(none)>
James Bottomley <jejb@titanic.il.steeleye.com>
James E Wilson <wilson@specifix.com>

13
Documentation/ABI/stable/sysfs-driver-mlxreg-io
View File

@ -29,13 +29,13 @@ Description: This file shows the system fans direction:
The files are read only.
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
Date: November 2018
KernelVersion: 5.0
Contact: Vadim Pasternak <vadimpmellanox.com>
Description: These files show with which CPLD versions have been burned
on LED board.
on LED or Gearbox board.
The files are read only.
@ -121,6 +121,15 @@ Description: These files show the system reset cause, as following: ComEx
The files are read only.
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version
Date: November 2018
KernelVersion: 5.0
Contact: Vadim Pasternak <vadimpmellanox.com>
Description: These files show with which CPLD versions have been burned
on LED board.
The files are read only.
Date: June 2019
KernelVersion: 5.3
Contact: Vadim Pasternak <vadimpmellanox.com>

2
Documentation/admin-guide/devices.txt
View File

@ -319,7 +319,7 @@
182 = /dev/perfctr Performance-monitoring counters
183 = /dev/hwrng Generic random number generator
184 = /dev/cpu/microcode CPU microcode update interface
186 = /dev/atomicps Atomic shapshot of process state data
186 = /dev/atomicps Atomic snapshot of process state data
187 = /dev/irnet IrNET device
188 = /dev/smbusbios SMBus BIOS
189 = /dev/ussp_ctl User space serial port control

6
Documentation/devicetree/bindings/i2c/i2c-at91.txt
View File

@ -18,8 +18,10 @@ Optional properties:
- dma-names: should contain "tx" and "rx".
- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
capable I2C controllers.
- i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
and "atmel,sama5d2-i2c".
- i2c-sda-hold-time-ns: TWD hold time, only available for:
"atmel,sama5d4-i2c",
"atmel,sama5d2-i2c",
"microchip,sam9x60-i2c".
- Child nodes conforming to i2c bus binding
Examples :

2
Documentation/media/v4l-drivers/meye.rst
View File

@ -95,7 +95,7 @@ so all video4linux tools (like xawtv) should work with this driver.
Besides the video4linux interface, the driver has a private interface
for accessing the Motion Eye extended parameters (camera sharpness,
agc, video framerate), the shapshot and the MJPEG capture facilities.
agc, video framerate), the snapshot and the MJPEG capture facilities.
This interface consists of several ioctls (prototypes and structures
can be found in include/linux/meye.h):

2
Documentation/process/embargoed-hardware-issues.rst
View File

@ -255,7 +255,7 @@ an involved disclosed party. The current ambassadors list:
Red Hat Josh Poimboeuf <jpoimboe@redhat.com>
SUSE Jiri Kosina <jkosina@suse.cz>
Amazon
Amazon Peter Bowen <pzb@amzn.com>
Google Kees Cook <keescook@chromium.org>
============= ========================================================

20
MAINTAINERS
View File

@ -720,7 +720,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-altera.txt
F: drivers/i2c/busses/i2c-altera.c
ALTERA MAILBOX DRIVER
M: Ley Foon Tan <lftan@altera.com>
M: Ley Foon Tan <ley.foon.tan@intel.com>
L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
S: Maintained
F: drivers/mailbox/mailbox-altera.c
@ -1407,7 +1407,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
ARM/ACTIONS SEMI ARCHITECTURE
M: Andreas Färber <afaerber@suse.de>
R: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: owl
@ -3150,7 +3150,7 @@ S: Maintained
F: arch/mips/net/
BPF JIT for NFP NICs
M: Jakub Kicinski <jakub.kicinski@netronome.com>
M: Jakub Kicinski <kuba@kernel.org>
L: netdev@vger.kernel.org
L: bpf@vger.kernel.org
S: Supported
@ -11431,7 +11431,7 @@ F: include/uapi/linux/netrom.h
F: net/netrom/
NETRONOME ETHERNET DRIVERS
M: Jakub Kicinski <jakub.kicinski@netronome.com>
M: Jakub Kicinski <kuba@kernel.org>
L: oss-drivers@netronome.com
S: Maintained
F: drivers/net/ethernet/netronome/
@ -11591,7 +11591,7 @@ M: Boris Pismenny <borisp@mellanox.com>
M: Aviad Yehezkel <aviadye@mellanox.com>
M: John Fastabend <john.fastabend@gmail.com>
M: Daniel Borkmann <daniel@iogearbox.net>
M: Jakub Kicinski <jakub.kicinski@netronome.com>
M: Jakub Kicinski <kuba@kernel.org>
L: netdev@vger.kernel.org
S: Maintained
F: net/tls/*
@ -11603,7 +11603,7 @@ L: linux-wireless@vger.kernel.org
Q: http://patchwork.kernel.org/project/linux-wireless/list/
NETDEVSIM
M: Jakub Kicinski <jakub.kicinski@netronome.com>
M: Jakub Kicinski <kuba@kernel.org>
S: Maintained
F: drivers/net/netdevsim/*
@ -11680,7 +11680,7 @@ F: Documentation/scsi/NinjaSCSI.txt
F: drivers/scsi/nsp32*
NIOS2 ARCHITECTURE
M: Ley Foon Tan <lftan@altera.com>
M: Ley Foon Tan <ley.foon.tan@intel.com>
L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git
S: Maintained
@ -12564,7 +12564,7 @@ F: Documentation/devicetree/bindings/pci/aardvark-pci.txt
F: drivers/pci/controller/pci-aardvark.c
PCI DRIVER FOR ALTERA PCIE IP
M: Ley Foon Tan <lftan@altera.com>
M: Ley Foon Tan <ley.foon.tan@intel.com>
L: rfi@lists.rocketboards.org (moderated for non-subscribers)
L: linux-pci@vger.kernel.org
S: Supported
@ -12743,7 +12743,7 @@ S: Supported
F: Documentation/PCI/pci-error-recovery.rst
PCI MSI DRIVER FOR ALTERA MSI IP
M: Ley Foon Tan <lftan@altera.com>
M: Ley Foon Tan <ley.foon.tan@intel.com>
L: rfi@lists.rocketboards.org (moderated for non-subscribers)
L: linux-pci@vger.kernel.org
S: Supported
@ -18042,7 +18042,7 @@ XDP (eXpress Data Path)
M: Alexei Starovoitov <ast@kernel.org>
M: Daniel Borkmann <daniel@iogearbox.net>
M: David S. Miller <davem@davemloft.net>
M: Jakub Kicinski <jakub.kicinski@netronome.com>
M: Jakub Kicinski <kuba@kernel.org>
M: Jesper Dangaard Brouer <hawk@kernel.org>
M: John Fastabend <john.fastabend@gmail.com>
L: netdev@vger.kernel.org

2
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 5
PATCHLEVEL = 5
SUBLEVEL = 0
EXTRAVERSION = -rc5
EXTRAVERSION = -rc7
NAME = Kleptomaniac Octopus
# *DOCUMENTATION*

1
arch/arm/Kconfig
View File

@ -72,6 +72,7 @@ config ARM
select HAVE_ARM_SMCCC if CPU_V7
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
select HAVE_CONTEXT_TRACKING
select HAVE_COPY_THREAD_TLS
select HAVE_C_RECORDMCOUNT
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS if MMU

6
arch/arm/boot/dts/am571x-idk.dts
View File

@ -167,11 +167,7 @@
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
};
&mmc1 {

4
arch/arm/boot/dts/am572x-idk-common.dtsi
View File

@ -147,10 +147,6 @@
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {

25
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -29,6 +29,27 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
main_12v0: fixedregulator-main_12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "main_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
evm_5v0: fixedregulator-evm_5v0 {
/* Output of TPS54531D */
compatible = "regulator-fixed";
regulator-name = "evm_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&main_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
@ -547,10 +568,6 @@
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
&pcie1_ep {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;

369
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View File

@ -258,9 +258,9 @@
};
};
pca0: pca9552@60 {
pca0: pca9552@61 {
compatible = "nxp,pca9552";
reg = <0x60>;
reg = <0x61>;
#address-cells = <1>;
#size-cells = <0>;
@ -519,371 +519,6 @@
status = "okay";
};
&i2c13 {
status = "okay";
};
&i2c14 {
status = "okay";
};
&i2c15 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
power-supply@68 {
compatible = "ibm,cffps2";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps2";
reg = <0x69>;
};
power-supply@6a {
compatible = "ibm,cffps2";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps2";
reg = <0x6b>;
};
};
&i2c4 {
status = "okay";
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
tmp275@49 {
compatible = "ti,tmp275";
reg = <0x49>;
};
tmp275@4a {
compatible = "ti,tmp275";
reg = <0x4a>;
};
};
&i2c5 {
status = "okay";
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
tmp275@49 {
compatible = "ti,tmp275";
reg = <0x49>;
};
};
&i2c6 {
status = "okay";
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
tmp275@4a {
compatible = "ti,tmp275";
reg = <0x4a>;
};
tmp275@4b {
compatible = "ti,tmp275";
reg = <0x4b>;
};
};
&i2c7 {
status = "okay";
si7021-a20@20 {
compatible = "silabs,si7020";
reg = <0x20>;
};
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
max31785@52 {
compatible = "maxim,max31785a";
reg = <0x52>;
#address-cells = <1>;
#size-cells = <0>;
fan@0 {
compatible = "pmbus-fan";
reg = <0>;
tach-pulses = <2>;
};
fan@1 {
compatible = "pmbus-fan";
reg = <1>;
tach-pulses = <2>;
};
fan@2 {
compatible = "pmbus-fan";
reg = <2>;
tach-pulses = <2>;
};
fan@3 {
compatible = "pmbus-fan";
reg = <3>;
tach-pulses = <2>;
};
};
pca0: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
};
gpio@1 {
reg = <1>;
};
gpio@2 {
reg = <2>;
};
gpio@3 {
reg = <3>;
};
gpio@4 {
reg = <4>;
};
gpio@5 {
reg = <5>;
};
gpio@6 {
reg = <6>;
};
gpio@7 {
reg = <7>;
};
gpio@8 {
reg = <8>;
};
gpio@9 {
reg = <9>;
};
gpio@10 {
reg = <10>;
};
gpio@11 {
reg = <11>;
};
gpio@12 {
reg = <12>;
};
gpio@13 {
reg = <13>;
};
gpio@14 {
reg = <14>;
};
gpio@15 {
reg = <15>;
};
};
dps: dps310@76 {
compatible = "infineon,dps310";
reg = <0x76>;
#io-channel-cells = <0>;
};
};
&i2c8 {
status = "okay";
ucd90320@b {
compatible = "ti,ucd90160";
reg = <0x0b>;
};
ucd90320@c {
compatible = "ti,ucd90160";
reg = <0x0c>;
};
ucd90320@11 {
compatible = "ti,ucd90160";
reg = <0x11>;
};
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
tmp275@4a {
compatible = "ti,tmp275";
reg = <0x4a>;
};
};
&i2c9 {
status = "okay";
ir35221@42 {
compatible = "infineon,ir35221";
reg = <0x42>;
};
ir35221@43 {
compatible = "infineon,ir35221";
reg = <0x43>;
};
ir35221@44 {
compatible = "infineon,ir35221";
reg = <0x44>;
};
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
tmp423b@4d {
compatible = "ti,tmp423";
reg = <0x4d>;
};
ir35221@72 {
compatible = "infineon,ir35221";
reg = <0x72>;
};
ir35221@73 {
compatible = "infineon,ir35221";
reg = <0x73>;
};
ir35221@74 {
compatible = "infineon,ir35221";
reg = <0x74>;
};
};
&i2c10 {
status = "okay";
ir35221@42 {
compatible = "infineon,ir35221";
reg = <0x42>;
};
ir35221@43 {
compatible = "infineon,ir35221";
reg = <0x43>;
};
ir35221@44 {
compatible = "infineon,ir35221";
reg = <0x44>;
};
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
tmp423b@4d {
compatible = "ti,tmp423";
reg = <0x4d>;
};
ir35221@72 {
compatible = "infineon,ir35221";
reg = <0x72>;
};
ir35221@73 {
compatible = "infineon,ir35221";
reg = <0x73>;
};
ir35221@74 {
compatible = "infineon,ir35221";
reg = <0x74>;
};
};
&i2c11 {
status = "okay";
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
tmp275@49 {
compatible = "ti,tmp275";
reg = <0x49>;
};
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";

403
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
View File

@ -122,37 +122,6 @@
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-128.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt-bmc";
spi-max-frequency = <50000000>;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
spi-max-frequency = <100000000>;
};
};
&mac2 {
status = "okay";
pinctrl-names = "default";
@ -165,6 +134,11 @@
&emmc {
status = "okay";
};
&fsim0 {
status = "okay";
#address-cells = <2>;
#size-cells = <0>;
@ -820,373 +794,6 @@
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
bmp: bmp280@77 {
compatible = "bosch,bmp280";
reg = <0x77>;
#io-channel-cells = <1>;
};
max31785@52 {
compatible = "maxim,max31785a";
reg = <0x52>;
#address-cells = <1>;
#size-cells = <0>;
fan@0 {
compatible = "pmbus-fan";
reg = <0>;
tach-pulses = <2>;
maxim,fan-rotor-input = "tach";
maxim,fan-pwm-freq = <25000>;
maxim,fan-dual-tach;
maxim,fan-no-watchdog;
maxim,fan-no-fault-ramp;
maxim,fan-ramp = <2>;
maxim,fan-fault-pin-mon;
};
fan@1 {
compatible = "pmbus-fan";
reg = <1>;
tach-pulses = <2>;
maxim,fan-rotor-input = "tach";
maxim,fan-pwm-freq = <25000>;
maxim,fan-dual-tach;
maxim,fan-no-watchdog;
maxim,fan-no-fault-ramp;
maxim,fan-ramp = <2>;
maxim,fan-fault-pin-mon;
};
fan@2 {
compatible = "pmbus-fan";
reg = <2>;
tach-pulses = <2>;
maxim,fan-rotor-input = "tach";
maxim,fan-pwm-freq = <25000>;
maxim,fan-dual-tach;
maxim,fan-no-watchdog;
maxim,fan-no-fault-ramp;
maxim,fan-ramp = <2>;
maxim,fan-fault-pin-mon;
};
fan@3 {
compatible = "pmbus-fan";
reg = <3>;
tach-pulses = <2>;
maxim,fan-rotor-input = "tach";
maxim,fan-pwm-freq = <25000>;
maxim,fan-dual-tach;
maxim,fan-no-watchdog;
maxim,fan-no-fault-ramp;
maxim,fan-ramp = <2>;
maxim,fan-fault-pin-mon;
};
};
dps: dps310@76 {
compatible = "infineon,dps310";
reg = <0x76>;
#io-channel-cells = <0>;
};
pca0: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
power-supply@68 {
compatible = "ibm,cffps1";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps1";
reg = <0x69>;
};
};
&i2c4 {
status = "okay";
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@71 {
compatible = "infineon,ir35221";
reg = <0x71>;
};
};
&i2c5 {
status = "okay";
tmp423a@4c {
compatible = "ti,tmp423";
reg = <0x4c>;
};
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@71 {
compatible = "infineon,ir35221";
reg = <0x71>;
};
};
&i2c7 {
status = "okay";
};
&i2c9 {
status = "okay";
tmp275@4a {
compatible = "ti,tmp275";
reg = <0x4a>;
};
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
pca9552: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
"GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
"GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
"GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
"GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
"GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
"GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
"12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
eeprom@51 {
compatible = "atmel,24c64";
reg = <0x51>;
};
ucd90160@64 {
compatible = "ti,ucd90160";
reg = <0x64>;
};
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&pinctrl {
/* Hog these as no driver is probed for the entire LPC block */
pinctrl-names = "default";

39
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -163,26 +163,6 @@
spi-max-frequency = <50000000>;
status = "disabled";
};
fsim0: fsi@1e79b000 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b000 0x94>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi1_default>;
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
fsim1: fsi@1e79b100 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b100 0x94>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi2_default>;
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
};
mdio0: mdio@1e650000 {
@ -595,6 +575,25 @@
ranges = <0 0x1e78a000 0x1000>;
};
fsim0: fsi@1e79b000 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b000 0x94>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi1_default>;
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
fsim1: fsi@1e79b100 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b100 0x94>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi2_default>;
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
status = "disabled";
};
};
};
};

2
arch/arm/boot/dts/imx6dl-icore-mipi.dts
View File

@ -8,7 +8,7 @@
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-icore.dtsi"
#include "imx6qdl-icore-1.5.dtsi"
/ {
model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit";

2
arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
View File

@ -63,7 +63,7 @@
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
VDDIO-supply = <&sw2_reg>;
};
};

2
arch/arm/boot/dts/imx6q-dhcom-som.dtsi
View File

@ -204,7 +204,7 @@
};
rtc@56 {
compatible = "rv3029c2";
compatible = "microcrystal,rv3029";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_hw300>;
reg = <0x56>;

4
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -749,10 +749,6 @@
vin-supply = <&vgen5_reg>;
};
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&vgen5_reg>;
};

4
arch/arm/boot/dts/imx6sl-evk.dts
View File

@ -584,10 +584,6 @@
vin-supply = <&sw2_reg>;
};
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&sw2_reg>;
};

4
arch/arm/boot/dts/imx6sll-evk.dts
View File

@ -265,10 +265,6 @@
status = "okay";
};
&reg_3p0 {
vin-supply = <&sw2_reg>;
};
&snvs_poweroff {
status = "okay";
};

4
arch/arm/boot/dts/imx6sx-sdb-reva.dts
View File

@ -159,10 +159,6 @@
vin-supply = <&vgen6_reg>;
};
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&vgen6_reg>;
};

4
arch/arm/boot/dts/imx6sx-sdb.dts
View File

@ -141,10 +141,6 @@
vin-supply = <&vgen6_reg>;
};
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 {
vin-supply = <&vgen6_reg>;
};

4
arch/arm/boot/dts/imx7s-colibri.dtsi
View File

@ -49,3 +49,7 @@
reg = <0x80000000 0x10000000>;
};
};
&gpmi {
status = "okay";
};

4
arch/arm/boot/dts/imx7ulp.dtsi
View File

@ -37,10 +37,10 @@
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
reg = <0xf00>;
};
};

2
arch/arm/boot/dts/meson8.dtsi
View File

@ -253,7 +253,7 @@
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
reg = <0xe0 0x8>;
reg = <0xe0 0x18>;
};
pinctrl_aobus: pinctrl@84 {

12
arch/arm/boot/dts/mmp3.dtsi
View File

@ -356,7 +356,7 @@
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
reg = <0xd4011000 0x70>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_clocks MMP2_CLK_TWSI0>;
resets = <&soc_clocks MMP2_CLK_TWSI0>;
@ -368,7 +368,7 @@
twsi2: i2c@d4031000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4031000 0x1000>;
reg = <0xd4031000 0x70>;
interrupt-parent = <&twsi_mux>;
interrupts = <0>;
clocks = <&soc_clocks MMP2_CLK_TWSI1>;
@ -380,7 +380,7 @@
twsi3: i2c@d4032000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4032000 0x1000>;
reg = <0xd4032000 0x70>;
interrupt-parent = <&twsi_mux>;
interrupts = <1>;
clocks = <&soc_clocks MMP2_CLK_TWSI2>;
@ -392,7 +392,7 @@
twsi4: i2c@d4033000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4033000 0x1000>;
reg = <0xd4033000 0x70>;
interrupt-parent = <&twsi_mux>;
interrupts = <2>;
clocks = <&soc_clocks MMP2_CLK_TWSI3>;
@ -405,7 +405,7 @@
twsi5: i2c@d4033800 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4033800 0x1000>;
reg = <0xd4033800 0x70>;
interrupt-parent = <&twsi_mux>;
interrupts = <3>;
clocks = <&soc_clocks MMP2_CLK_TWSI4>;
@ -417,7 +417,7 @@
twsi6: i2c@d4034000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4034000 0x1000>;
reg = <0xd4034000 0x70>;
interrupt-parent = <&twsi_mux>;
interrupts = <4>;
clocks = <&soc_clocks MMP2_CLK_TWSI5>;

2
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
View File

@ -101,7 +101,7 @@
initial-mode = <1>; /* initialize in HUB mode */
disabled-ports = <1>;
intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
refclk-frequency = <19200000>;
};

6
arch/arm/kernel/process.c
View File

@ -226,8 +226,8 @@ void release_thread(struct task_struct *dead_task)
asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
int
copy_thread(unsigned long clone_flags, unsigned long stack_start,
unsigned long stk_sz, struct task_struct *p)
copy_thread_tls(unsigned long clone_flags, unsigned long stack_start,
unsigned long stk_sz, struct task_struct *p, unsigned long tls)
{
struct thread_info *thread = task_thread_info(p);
struct pt_regs *childregs = task_pt_regs(p);
@ -261,7 +261,7 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
clear_ptrace_hw_breakpoint(p);
if (clone_flags & CLONE_SETTLS)
thread->tp_value[0] = childregs->ARM_r3;
thread->tp_value[0] = tls;
thread->tp_value[1] = get_tpuser();
thread_notify(THREAD_NOTIFY_COPY, thread);

1
arch/arm/mach-davinci/Kconfig
View File

@ -9,6 +9,7 @@ menuconfig ARCH_DAVINCI
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select REGMAP_MMIO
select RESET_CONTROLLER
select HAVE_IDE
select PINCTRL_SINGLE

2
arch/arm/mach-mmp/time.c
View File

@ -207,7 +207,7 @@ static int __init mmp_dt_init_timer(struct device_node *np)
ret = clk_prepare_enable(clk);
if (ret)
return ret;
rate = clk_get_rate(clk) / 2;
rate = clk_get_rate(clk);
} else if (cpu_is_pj4()) {
rate = 6500000;
} else {

3
arch/arm/mach-omap2/Kconfig
View File

@ -95,6 +95,7 @@ config ARCH_OMAP2PLUS
bool
select ARCH_HAS_BANDGAP
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_HAS_RESET_CONTROLLER
select ARCH_OMAP
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
@ -105,11 +106,11 @@ config ARCH_OMAP2PLUS
select OMAP_DM_TIMER
select OMAP_GPMC
select PINCTRL
select RESET_CONTROLLER
select SOC_BUS
select TI_SYSC
select OMAP_IRQCHIP
select CLKSRC_TI_32K
select ARCH_HAS_RESET_CONTROLLER
help
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5

6
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -306,10 +306,14 @@ static void __init dra7x_evm_mmc_quirk(void)
static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk)
{
struct clk_hw *hw = __clk_get_hw(clk);
struct clockdomain *clkdm = NULL;
struct clk_hw_omap *hwclk;
hwclk = to_clk_hw_omap(__clk_get_hw(clk));
hwclk = to_clk_hw_omap(hw);
if (!omap2_clk_is_hw_omap(hw))
return NULL;
if (hwclk && hwclk->clkdm_name)
clkdm = clkdm_lookup(hwclk->clkdm_name);

1
arch/arm64/Kconfig
View File

@ -138,6 +138,7 @@ config ARM64
select HAVE_CMPXCHG_DOUBLE
select HAVE_CMPXCHG_LOCAL
select HAVE_CONTEXT_TRACKING
select HAVE_COPY_THREAD_TLS
select HAVE_DEBUG_BUGVERBOSE
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS

2
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
View File

@ -15,7 +15,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_eldo1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;

2
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
View File

@ -140,7 +140,7 @@
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_aldo2>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;

8
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -61,10 +61,10 @@
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 120 8>,
<0 121 8>,
<0 122 8>,
<0 123 8>;
interrupts = <0 170 4>,
<0 171 4>,
<0 172 4>,
<0 173 4>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,

28
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
View File

@ -46,25 +46,47 @@
};
gpio-keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
compatible = "gpio-keys";
key1 {
label = "A";
linux,code = <BTN_0>;
gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
interrupts = <34 IRQ_TYPE_EDGE_BOTH>;
};
key2 {
label = "B";
linux,code = <BTN_1>;
gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
interrupts = <35 IRQ_TYPE_EDGE_BOTH>;
};
key3 {
label = "C";
linux,code = <BTN_2>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
};
mic_mute {
label = "MicMute";
linux,code = <SW_MUTE_DEVICE>;
linux,input-type = <EV_SW>;
gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
interrupts = <99 IRQ_TYPE_EDGE_BOTH>;
};
power_key {
label = "PowerKey";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
};
};
@ -569,6 +591,8 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
interrupt-parent = <&gpio_intc>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;

2
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -175,7 +175,7 @@
dcfg: syscon@1e00000 {
compatible = "fsl,ls1028a-dcfg", "syscon";
reg = <0x0 0x1e00000 0x0 0x10000>;
big-endian;
little-endian;
};
rst: syscon@1e60000 {

2
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -740,7 +740,7 @@
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
<&clk IMX8MM_CLK_SDMA1_ROOT>;
<&clk IMX8MM_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -421,7 +421,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
vdd-supply = <&reg_3v3_p>;
vddio-supply = <&reg_3v3_p>;
};

8
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -60,10 +60,10 @@
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 120 8>,
<0 121 8>,
<0 122 8>,
<0 123 8>;
interrupts = <0 170 4>,
<0 171 4>,
<0 172 4>,
<0 173 4>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,

3
arch/arm64/boot/dts/rockchip/rk3328-a1.dts
View File

@ -49,7 +49,8 @@
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
linux,rc-map-name = "rc-beelink-gs1";
};
};

1
arch/arm64/include/asm/unistd.h
View File

@ -42,7 +42,6 @@
#endif
#define __ARCH_WANT_SYS_CLONE
#define __ARCH_WANT_SYS_CLONE3
#ifndef __COMPAT_SYSCALL_NR
#include <uapi/asm/unistd.h>

1
arch/arm64/include/uapi/asm/unistd.h
View File

@ -19,5 +19,6 @@
#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_SET_GET_RLIMIT
#define __ARCH_WANT_TIME32_SYSCALLS
#define __ARCH_WANT_SYS_CLONE3
#include <asm-generic/unistd.h>

10
arch/arm64/kernel/process.c
View File

@ -360,8 +360,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
asmlinkage void ret_from_fork(void) asm("ret_from_fork");
int copy_thread(unsigned long clone_flags, unsigned long stack_start,
unsigned long stk_sz, struct task_struct *p)
int copy_thread_tls(unsigned long clone_flags, unsigned long stack_start,
unsigned long stk_sz, struct task_struct *p, unsigned long tls)
{
struct pt_regs *childregs = task_pt_regs(p);
@ -394,11 +394,11 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
}
/*
* If a TLS pointer was passed to clone (4th argument), use it
* for the new thread.
* If a TLS pointer was passed to clone, use it for the new
* thread.
*/
if (clone_flags & CLONE_SETTLS)
p->thread.uw.tp_value = childregs->regs[3];
p->thread.uw.tp_value = tls;
} else {
memset(childregs, 0, sizeof(struct pt_regs));
childregs->pstate = PSR_MODE_EL1h;

11
arch/nds32/include/asm/cacheflush.h
View File

@ -9,7 +9,11 @@
#define PG_dcache_dirty PG_arch_1
void flush_icache_range(unsigned long start, unsigned long end);
#define flush_icache_range flush_icache_range
void flush_icache_page(struct vm_area_struct *vma, struct page *page);
#define flush_icache_page flush_icache_page
#ifdef CONFIG_CPU_CACHE_ALIASING
void flush_cache_mm(struct mm_struct *mm);
void flush_cache_dup_mm(struct mm_struct *mm);
@ -40,12 +44,11 @@ void invalidate_kernel_vmap_range(void *addr, int size);
#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&(mapping)->i_pages)
#else
#include <asm-generic/cacheflush.h>
#undef flush_icache_range
#undef flush_icache_page
#undef flush_icache_user_range
void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len);
#define flush_icache_user_range flush_icache_user_range
#include <asm-generic/cacheflush.h>
#endif
#endif /* __NDS32_CACHEFLUSH_H__ */

2
arch/nds32/include/asm/pgtable.h
View File

@ -195,7 +195,7 @@ extern void paging_init(void);
#define pte_unmap(pte) do { } while (0)
#define pte_unmap_nested(pte) do { } while (0)
#define pmd_off_k(address) pmd_offset(pgd_offset_k(address), address)
#define pmd_off_k(address) pmd_offset(pud_offset(p4d_offset(pgd_offset_k(address), (address)), (address)), (address))
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
/*

1
arch/parisc/Kconfig
View File

@ -62,6 +62,7 @@ config PARISC
select HAVE_FTRACE_MCOUNT_RECORD if HAVE_DYNAMIC_FTRACE
select HAVE_KPROBES_ON_FTRACE
select HAVE_DYNAMIC_FTRACE_WITH_REGS
select HAVE_COPY_THREAD_TLS
help
The PA-RISC microprocessor is designed by Hewlett-Packard and used

4
arch/parisc/kernel/drivers.c
View File

@ -889,8 +889,8 @@ static void print_parisc_device(struct parisc_device *dev)
static int count;
print_pa_hwpath(dev, hw_path);
pr_info("%d. %s at 0x%px [%s] { %d, 0x%x, 0x%.3x, 0x%.5x }",
++count, dev->name, (void*) dev->hpa.start, hw_path, dev->id.hw_type,
pr_info("%d. %s at %pap [%s] { %d, 0x%x, 0x%.3x, 0x%.5x }",
++count, dev->name, &(dev->hpa.start), hw_path, dev->id.hw_type,
dev->id.hversion_rev, dev->id.hversion, dev->id.sversion);
if (dev->num_addrs) {

8
arch/parisc/kernel/process.c
View File

@ -208,8 +208,8 @@ arch_initcall(parisc_idle_init);
* Copy architecture-specific thread state
*/
int
copy_thread(unsigned long clone_flags, unsigned long usp,
unsigned long kthread_arg, struct task_struct *p)
copy_thread_tls(unsigned long clone_flags, unsigned long usp,
unsigned long kthread_arg, struct task_struct *p, unsigned long tls)
{
struct pt_regs *cregs = &(p->thread.regs);
void *stack = task_stack_page(p);
@ -254,9 +254,9 @@ copy_thread(unsigned long clone_flags, unsigned long usp,
cregs->ksp = (unsigned long)stack + THREAD_SZ_ALGN + FRAME_SIZE;
cregs->kpc = (unsigned long) &child_return;
/* Setup thread TLS area from the 4th parameter in clone */
/* Setup thread TLS area */
if (clone_flags & CLONE_SETTLS)
cregs->cr27 = cregs->gr[23];
cregs->cr27 = tls;
}
return 0;

2
arch/parisc/mm/init.c
View File

@ -401,7 +401,7 @@ static void __init map_pages(unsigned long start_vaddr,
pmd = (pmd_t *) __pa(pmd);
}
pgd_populate(NULL, pg_dir, __va(pmd));
pud_populate(NULL, (pud_t *)pg_dir, __va(pmd));
#endif
pg_dir++;

1
arch/riscv/Kconfig
View File

@ -65,6 +65,7 @@ config RISCV
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select HAVE_ARCH_MMAP_RND_BITS if MMU
select ARCH_HAS_GCOV_PROFILE_ALL
select HAVE_COPY_THREAD_TLS
config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT

4
arch/riscv/include/asm/asm-prototypes.h
View File

@ -5,4 +5,8 @@
#include <linux/ftrace.h>
#include <asm-generic/asm-prototypes.h>
long long __lshrti3(long long a, int b);
long long __ashrti3(long long a, int b);
long long __ashlti3(long long a, int b);
#endif /* _ASM_RISCV_PROTOTYPES_H */

18
arch/riscv/kernel/head.S
View File

@ -80,7 +80,9 @@ _start_kernel:
#ifdef CONFIG_SMP
li t0, CONFIG_NR_CPUS
bgeu a0, t0, .Lsecondary_park
blt a0, t0, .Lgood_cores
tail .Lsecondary_park
.Lgood_cores:
#endif
/* Pick one hart to run the main boot sequence */
@ -209,11 +211,6 @@ relocate:
tail smp_callin
#endif
.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
j .Lsecondary_park
END(_start)
#ifdef CONFIG_RISCV_M_MODE
@ -251,7 +248,7 @@ ENTRY(reset_regs)
#ifdef CONFIG_FPU
csrr t0, CSR_MISA
andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
bnez t0, .Lreset_regs_done
beqz t0, .Lreset_regs_done
li t1, SR_FS
csrs CSR_STATUS, t1
@ -295,6 +292,13 @@ ENTRY(reset_regs)
END(reset_regs)
#endif /* CONFIG_RISCV_M_MODE */
.section ".text", "ax",@progbits
.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
j .Lsecondary_park
__PAGE_ALIGNED_BSS
/* Empty zero page */
.balign PAGE_SIZE

6
arch/riscv/kernel/process.c
View File

@ -99,8 +99,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
return 0;
}
int copy_thread(unsigned long clone_flags, unsigned long usp,
unsigned long arg, struct task_struct *p)
int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
unsigned long arg, struct task_struct *p, unsigned long tls)
{
struct pt_regs *childregs = task_pt_regs(p);
@ -121,7 +121,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
if (usp) /* User fork */
childregs->sp = usp;
if (clone_flags & CLONE_SETTLS)
childregs->tp = childregs->a5;
childregs->tp = tls;
childregs->a0 = 0; /* Return value of fork() */
p->thread.ra = (unsigned long)ret_from_fork;
}

3
arch/riscv/kernel/vdso/Makefile
View File

@ -58,7 +58,8 @@ quiet_cmd_vdsold = VDSOLD $@
cmd_vdsold = $(CC) $(KBUILD_CFLAGS) $(call cc-option, -no-pie) -nostdlib -nostartfiles $(SYSCFLAGS_$(@F)) \
-Wl,-T,$(filter-out FORCE,$^) -o $@.tmp && \
$(CROSS_COMPILE)objcopy \
$(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@
$(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@ && \
rm $@.tmp
# install commands for the unstripped file
quiet_cmd_vdso_install = INSTALL $@

75
arch/riscv/lib/tishift.S
View File

@ -4,34 +4,73 @@
*/
#include <linux/linkage.h>
#include <asm-generic/export.h>
ENTRY(__lshrti3)
SYM_FUNC_START(__lshrti3)
beqz a2, .L1
li a5,64
sub a5,a5,a2
addi sp,sp,-16
sext.w a4,a5
blez a5, .L2
sext.w a2,a2
sll a4,a1,a4
srl a0,a0,a2
srl a1,a1,a2
sll a4,a1,a4
srl a2,a1,a2
or a0,a0,a4
sd a1,8(sp)
sd a0,0(sp)
ld a0,0(sp)
ld a1,8(sp)
addi sp,sp,16
ret
mv a1,a2
.L1:
ret
.L2:
negw a4,a4
srl a1,a1,a4
sd a1,0(sp)
sd zero,8(sp)
ld a0,0(sp)
ld a1,8(sp)
addi sp,sp,16
negw a0,a4
li a2,0
srl a0,a1,a0
mv a1,a2
ret
ENDPROC(__lshrti3)
SYM_FUNC_END(__lshrti3)
EXPORT_SYMBOL(__lshrti3)
SYM_FUNC_START(__ashrti3)
beqz a2, .L3
li a5,64
sub a5,a5,a2
sext.w a4,a5
blez a5, .L4
sext.w a2,a2
srl a0,a0,a2
sll a4,a1,a4
sra a2,a1,a2
or a0,a0,a4
mv a1,a2
.L3:
ret
.L4:
negw a0,a4
srai a2,a1,0x3f
sra a0,a1,a0
mv a1,a2
ret
SYM_FUNC_END(__ashrti3)
EXPORT_SYMBOL(__ashrti3)
SYM_FUNC_START(__ashlti3)
beqz a2, .L5
li a5,64
sub a5,a5,a2
sext.w a4,a5
blez a5, .L6
sext.w a2,a2
sll a1,a1,a2
srl a4,a0,a4
sll a2,a0,a2
or a1,a1,a4
mv a0,a2
.L5:
ret
.L6:
negw a1,a4
li a2,0
sll a1,a0,a1
mv a0,a2
ret
SYM_FUNC_END(__ashlti3)
EXPORT_SYMBOL(__ashlti3)

2
arch/s390/kernel/setup.c
View File

@ -1052,7 +1052,7 @@ static void __init log_component_list(void)
if (!early_ipl_comp_list_addr)
return;
if (ipl_block.hdr.flags & IPL_PL_FLAG_IPLSR)
if (ipl_block.hdr.flags & IPL_PL_FLAG_SIPL)
pr_info("Linux is running with Secure-IPL enabled\n");
else
pr_info("Linux is running with Secure-IPL disabled\n");

1
arch/um/Kconfig
View File

@ -14,6 +14,7 @@ config UML
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_DEBUG_KMEMLEAK
select HAVE_DEBUG_BUGVERBOSE
select HAVE_COPY_THREAD_TLS
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
select GENERIC_CLOCKEVENTS

2
arch/um/include/asm/ptrace-generic.h
View File

@ -36,7 +36,7 @@ extern long subarch_ptrace(struct task_struct *child, long request,
extern unsigned long getreg(struct task_struct *child, int regno);
extern int putreg(struct task_struct *child, int regno, unsigned long value);
extern int arch_copy_tls(struct task_struct *new);
extern int arch_set_tls(struct task_struct *new, unsigned long tls);
extern void clear_flushed_tls(struct task_struct *task);
extern int syscall_trace_enter(struct pt_regs *regs);
extern void syscall_trace_leave(struct pt_regs *regs);

6
arch/um/kernel/process.c
View File

@ -153,8 +153,8 @@ void fork_handler(void)
userspace(&current->thread.regs.regs, current_thread_info()->aux_fp_regs);
}
int copy_thread(unsigned long clone_flags, unsigned long sp,
unsigned long arg, struct task_struct * p)
int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
unsigned long arg, struct task_struct * p, unsigned long tls)
{
void (*handler)(void);
int kthread = current->flags & PF_KTHREAD;
@ -188,7 +188,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
* Set a new TLS for the child thread?
*/
if (clone_flags & CLONE_SETTLS)
ret = arch_copy_tls(p);
ret = arch_set_tls(p, tls);
}
return ret;

6
arch/x86/events/intel/uncore_snb.c
View File

@ -15,6 +15,7 @@
#define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
#define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
#define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
#define PCI_DEVICE_ID_INTEL_SKL_E3_IMC 0x1918
#define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c
#define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904
#define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914
@ -657,6 +658,10 @@ static const struct pci_device_id skl_uncore_pci_ids[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
},
{ /* IMC */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_E3_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
},
{ /* IMC */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC),
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
@ -826,6 +831,7 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */
IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */
IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */
IMC_DEV(SKL_E3_IMC, &skl_uncore_pci_driver), /* Xeon E3 V5 Gen Core processor */
IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */
IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */
IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */

25
arch/x86/events/intel/uncore_snbep.c
View File

@ -369,11 +369,6 @@
#define SNR_M2M_PCI_PMON_BOX_CTL 0x438
#define SNR_M2M_PCI_PMON_UMASK_EXT 0xff
/* SNR PCIE3 */
#define SNR_PCIE3_PCI_PMON_CTL0 0x508
#define SNR_PCIE3_PCI_PMON_CTR0 0x4e8
#define SNR_PCIE3_PCI_PMON_BOX_CTL 0x4e4
/* SNR IMC */
#define SNR_IMC_MMIO_PMON_FIXED_CTL 0x54
#define SNR_IMC_MMIO_PMON_FIXED_CTR 0x38
@ -4328,27 +4323,12 @@ static struct intel_uncore_type snr_uncore_m2m = {
.format_group = &snr_m2m_uncore_format_group,
};
static struct intel_uncore_type snr_uncore_pcie3 = {
.name = "pcie3",
.num_counters = 4,
.num_boxes = 1,
.perf_ctr_bits = 48,
.perf_ctr = SNR_PCIE3_PCI_PMON_CTR0,
.event_ctl = SNR_PCIE3_PCI_PMON_CTL0,
.event_mask = SNBEP_PMON_RAW_EVENT_MASK,
.box_ctl = SNR_PCIE3_PCI_PMON_BOX_CTL,
.ops = &ivbep_uncore_pci_ops,
.format_group = &ivbep_uncore_format_group,
};
enum {
SNR_PCI_UNCORE_M2M,
SNR_PCI_UNCORE_PCIE3,
};
static struct intel_uncore_type *snr_pci_uncores[] = {
[SNR_PCI_UNCORE_M2M] = &snr_uncore_m2m,
[SNR_PCI_UNCORE_PCIE3] = &snr_uncore_pcie3,
NULL,
};
@ -4357,10 +4337,6 @@ static const struct pci_device_id snr_uncore_pci_ids[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
.driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, SNR_PCI_UNCORE_M2M, 0),
},
{ /* PCIe3 */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x334a),
.driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 0, SNR_PCI_UNCORE_PCIE3, 0),
},
{ /* end: all zeroes */ }
};
@ -4536,6 +4512,7 @@ static struct uncore_event_desc snr_uncore_imc_freerunning_events[] = {
INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
INTEL_UNCORE_EVENT_DESC(write.scale, "3.814697266e-6"),
INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"),
{ /* end: all zeroes */ },
};
static struct intel_uncore_ops snr_uncore_imc_freerunning_ops = {

4
arch/x86/kernel/cpu/amd.c
View File

@ -615,9 +615,9 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
return;
clear_all:
clear_cpu_cap(c, X86_FEATURE_SME);
setup_clear_cpu_cap(X86_FEATURE_SME);
clear_sev:
clear_cpu_cap(c, X86_FEATURE_SEV);
setup_clear_cpu_cap(X86_FEATURE_SEV);
}
}

9
arch/x86/kernel/cpu/mce/therm_throt.c
View File

@ -467,6 +467,7 @@ static int thermal_throttle_online(unsigned int cpu)
{
struct thermal_state *state = &per_cpu(thermal_state, cpu);
struct device *dev = get_cpu_device(cpu);
u32 l;
state->package_throttle.level = PACKAGE_LEVEL;
state->core_throttle.level = CORE_LEVEL;
@ -474,6 +475,10 @@ static int thermal_throttle_online(unsigned int cpu)
INIT_DELAYED_WORK(&state->package_throttle.therm_work, throttle_active_work);
INIT_DELAYED_WORK(&state->core_throttle.therm_work, throttle_active_work);
/* Unmask the thermal vector after the above workqueues are initialized. */
l = apic_read(APIC_LVTTHMR);
apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
return thermal_throttle_add_dev(dev, cpu);
}
@ -722,10 +727,6 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
/* Unmask the thermal vector: */
l = apic_read(APIC_LVTTHMR);
apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
tm2 ? "TM2" : "TM1");

2
arch/x86/kernel/cpu/resctrl/core.c
View File

@ -618,7 +618,7 @@ static void domain_remove_cpu(int cpu, struct rdt_resource *r)
if (static_branch_unlikely(&rdt_mon_enable_key))
rmdir_mondata_subdir_allrdtgrp(r, d->id);
list_del(&d->list);
if (is_mbm_enabled())
if (r->mon_capable && is_mbm_enabled())
cancel_delayed_work(&d->mbm_over);
if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) {
/*

6
arch/x86/kernel/cpu/resctrl/rdtgroup.c
View File

@ -1741,9 +1741,6 @@ static int set_cache_qos_cfg(int level, bool enable)
struct rdt_domain *d;
int cpu;
if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL))
return -ENOMEM;
if (level == RDT_RESOURCE_L3)
update = l3_qos_cfg_update;
else if (level == RDT_RESOURCE_L2)
@ -1751,6 +1748,9 @@ static int set_cache_qos_cfg(int level, bool enable)
else
return -EINVAL;
if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL))
return -ENOMEM;
r_l = &rdt_resources_all[level];
list_for_each_entry(d, &r_l->domains, list) {
/* Pick one CPU from each domain instance to update MSR */

6
arch/x86/um/tls_32.c
View File

@ -215,14 +215,12 @@ static int set_tls_entry(struct task_struct* task, struct user_desc *info,
return 0;
}
int arch_copy_tls(struct task_struct *new)
int arch_set_tls(struct task_struct *new, unsigned long tls)
{
struct user_desc info;
int idx, ret = -EFAULT;
if (copy_from_user(&info,
(void __user *) UPT_SI(&new->thread.regs.regs),
sizeof(info)))
if (copy_from_user(&info, (void __user *) tls, sizeof(info)))
goto out;
ret = -EINVAL;

7
arch/x86/um/tls_64.c
View File

@ -6,14 +6,13 @@ void clear_flushed_tls(struct task_struct *task)
{
}
int arch_copy_tls(struct task_struct *t)
int arch_set_tls(struct task_struct *t, unsigned long tls)
{
/*
* If CLONE_SETTLS is set, we need to save the thread id
* (which is argument 5, child_tid, of clone) so it can be set
* during context switches.
* so it can be set during context switches.
*/
t->thread.arch.fs = t->thread.regs.regs.gp[R8 / sizeof(long)];
t->thread.arch.fs = tls;
return 0;
}

1
arch/xtensa/Kconfig
View File

@ -24,6 +24,7 @@ config XTENSA
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
select HAVE_ARCH_TRACEHOOK
select HAVE_COPY_THREAD_TLS
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS
select HAVE_EXIT_THREAD

8
arch/xtensa/kernel/process.c
View File

@ -202,8 +202,9 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
* involved. Much simpler to just not copy those live frames across.
*/
int copy_thread(unsigned long clone_flags, unsigned long usp_thread_fn,
unsigned long thread_fn_arg, struct task_struct *p)
int copy_thread_tls(unsigned long clone_flags, unsigned long usp_thread_fn,
unsigned long thread_fn_arg, struct task_struct *p,
unsigned long tls)
{
struct pt_regs *childregs = task_pt_regs(p);
@ -266,9 +267,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp_thread_fn,
childregs->syscall = regs->syscall;
/* The thread pointer is passed in the '4th argument' (= a5) */
if (clone_flags & CLONE_SETTLS)
childregs->threadptr = childregs->areg[5];
childregs->threadptr = tls;
} else {
p->thread.ra = MAKE_RA_FOR_CALL(
(unsigned long)ret_from_kernel_thread, 1);

12
block/bio.c
View File

@ -538,6 +538,16 @@ void zero_fill_bio_iter(struct bio *bio, struct bvec_iter start)
}
EXPORT_SYMBOL(zero_fill_bio_iter);
/**
* bio_truncate - truncate the bio to small size of @new_size
* @bio: the bio to be truncated
* @new_size: new size for truncating the bio
*
* Description:
* Truncate the bio to new size of @new_size. If bio_op(bio) is
* REQ_OP_READ, zero the truncated part. This function should only
* be used for handling corner cases, such as bio eod.
*/
void bio_truncate(struct bio *bio, unsigned new_size)
{
struct bio_vec bv;
@ -548,7 +558,7 @@ void bio_truncate(struct bio *bio, unsigned new_size)
if (new_size >= bio->bi_iter.bi_size)
return;
if (bio_data_dir(bio) != READ)
if (bio_op(bio) != REQ_OP_READ)
goto exit;
bio_for_each_segment(bv, bio, iter) {

9
block/blk-merge.c
View File

@ -164,8 +164,13 @@ static inline unsigned get_max_segment_size(const struct request_queue *q,
unsigned long mask = queue_segment_boundary(q);
offset = mask & (page_to_phys(start_page) + offset);
return min_t(unsigned long, mask - offset + 1,
queue_max_segment_size(q));
/*
* overflow may be triggered in case of zero page physical address
* on 32bit arch, use queue's max segment size when that happens.
*/
return min_not_zero(mask - offset + 1,
(unsigned long)queue_max_segment_size(q));
}
/**

2
block/blk-settings.c
View File

@ -328,7 +328,7 @@ EXPORT_SYMBOL(blk_queue_max_segment_size);
* storage device can address. The default of 512 covers most
* hardware.
**/
void blk_queue_logical_block_size(struct request_queue *q, unsigned short size)
void blk_queue_logical_block_size(struct request_queue *q, unsigned int size)
{
q->limits.logical_block_size = size;

2
drivers/base/firmware_loader/builtin/Makefile
View File

@ -17,7 +17,7 @@ PROGBITS = $(if $(CONFIG_ARM),%,@)progbits
filechk_fwbin = \
echo "/* Generated by $(src)/Makefile */" ;\
echo " .section .rodata" ;\
echo " .p2align $(ASM_ALIGN)" ;\
echo " .p2align 4" ;\
echo "_fw_$(FWSTR)_bin:" ;\
echo " .incbin \"$(fwdir)/$(FWNAME)\"" ;\
echo "_fw_end:" ;\

4
drivers/block/null_blk_zoned.c
View File

@ -129,11 +129,13 @@ static blk_status_t null_zone_write(struct nullb_cmd *cmd, sector_t sector,
return BLK_STS_IOERR;
case BLK_ZONE_COND_EMPTY:
case BLK_ZONE_COND_IMP_OPEN:
case BLK_ZONE_COND_EXP_OPEN:
case BLK_ZONE_COND_CLOSED:
/* Writes must be at the write pointer position */
if (sector != zone->wp)
return BLK_STS_IOERR;
if (zone->cond == BLK_ZONE_COND_EMPTY)
if (zone->cond != BLK_ZONE_COND_EXP_OPEN)
zone->cond = BLK_ZONE_COND_IMP_OPEN;
zone->wp += nr_sectors;

10
drivers/bus/ti-sysc.c
View File

@ -343,6 +343,12 @@ static int sysc_get_clocks(struct sysc *ddata)
return -EINVAL;
}
/* Always add a slot for main clocks fck and ick even if unused */
if (!nr_fck)
ddata->nr_clocks++;
if (!nr_ick)
ddata->nr_clocks++;
ddata->clocks = devm_kcalloc(ddata->dev,
ddata->nr_clocks, sizeof(*ddata->clocks),
GFP_KERNEL);
@ -421,7 +427,7 @@ static int sysc_enable_opt_clocks(struct sysc *ddata)
struct clk *clock;
int i, error;
if (!ddata->clocks)
if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
return 0;
for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
@ -455,7 +461,7 @@ static void sysc_disable_opt_clocks(struct sysc *ddata)
struct clk *clock;
int i;
if (!ddata->clocks)
if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
return;
for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {

10
drivers/clk/clk.c
View File

@ -3426,11 +3426,17 @@ static int __clk_core_init(struct clk_core *core)
if (core->flags & CLK_IS_CRITICAL) {
unsigned long flags;
clk_core_prepare(core);
ret = clk_core_prepare(core);
if (ret)
goto out;
flags = clk_enable_lock();
clk_core_enable(core);
ret = clk_core_enable(core);
clk_enable_unlock(flags);
if (ret) {
clk_core_unprepare(core);
goto out;
}
}
clk_core_reparent_orphans_nolock();

2
drivers/clk/mmp/clk-of-mmp2.c
View File

@ -134,7 +134,7 @@ static DEFINE_SPINLOCK(ssp3_lock);
static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
static DEFINE_SPINLOCK(timer_lock);
static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
static DEFINE_SPINLOCK(reset_lock);

7
drivers/clk/qcom/gcc-sdm845.c
View File

@ -3255,6 +3255,7 @@ static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
.name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
@ -3263,6 +3264,7 @@ static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
.name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
@ -3271,6 +3273,7 @@ static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
.name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
@ -3279,6 +3282,7 @@ static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
.name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
@ -3287,6 +3291,7 @@ static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
@ -3295,6 +3300,7 @@ static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
@ -3303,6 +3309,7 @@ static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
.name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gcc_sdm845_clocks[] = {

8
drivers/clk/samsung/clk-exynos5420.c
View File

@ -12,6 +12,7 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk.h>
#include "clk.h"
#include "clk-cpu.h"
@ -1646,6 +1647,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_subcmus);
}
/*
* Keep top part of G3D clock path enabled permanently to ensure
* that the internal busses get their clock regardless of the
* main G3D clock enablement status.
*/
clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
samsung_clk_of_add_provider(np, ctx);
}

16
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View File

@ -23,9 +23,9 @@
*/
static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
"pll-periph0", "iosc" };
"iosc", "pll-periph0" };
static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
{ .index = 2, .shift = 0, .width = 5 },
{ .index = 3, .shift = 0, .width = 5 },
};
static struct ccu_div ar100_clk = {
@ -51,17 +51,7 @@ static struct ccu_div ar100_clk = {
static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
static struct ccu_div r_apb1_clk = {
.div = _SUNXI_CCU_DIV(0, 2),
.common = {
.reg = 0x00c,
.hw.init = CLK_HW_INIT("r-apb1",
"r-ahb",
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
static struct ccu_div r_apb2_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),

21
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View File

@ -51,19 +51,7 @@ static struct ccu_div ar100_clk = {
static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0);
static struct ccu_div apb0_clk = {
.div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
.common = {
.reg = 0x0c,
.hw.init = CLK_HW_INIT_HW("apb0",
&ahb0_clk.hw,
&ccu_div_ops,
0),
},
};
static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
/*
* Define the parent as an array that can be reused to save space
@ -127,7 +115,7 @@ static struct ccu_mp a83t_ir_clk = {
static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
&ar100_clk.common,
&a83t_apb0_clk.common,
&apb0_clk.common,
&apb0_pio_clk.common,
&apb0_ir_clk.common,
&apb0_timer_clk.common,
@ -167,7 +155,7 @@ static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
.hws = {
[CLK_AR100] = &ar100_clk.common.hw,
[CLK_AHB0] = &ahb0_clk.hw,
[CLK_APB0] = &a83t_apb0_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR] = &apb0_ir_clk.common.hw,
[CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
@ -282,9 +270,6 @@ static void __init sunxi_r_ccu_init(struct device_node *node,
static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
{
/* Fix apb0 bus gate parents here */
apb0_gate_parent[0] = &a83t_apb0_clk.common.hw;
sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
}
CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",

6
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
View File

@ -761,7 +761,8 @@ static struct ccu_mp outa_clk = {
.reg = 0x1f0,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("outa", out_parents,
&ccu_mp_ops, 0),
&ccu_mp_ops,
CLK_SET_RATE_PARENT),
}
};
@ -779,7 +780,8 @@ static struct ccu_mp outb_clk = {
.reg = 0x1f4,
.features = CCU_FEATURE_FIXED_PREDIV,
.hw.init = CLK_HW_INIT_PARENTS("outb", out_parents,
&ccu_mp_ops, 0),
&ccu_mp_ops,
CLK_SET_RATE_PARENT),
}
};

4
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@ -618,7 +618,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
},
.num = CLK_NUMBER,
.num = CLK_PLL_DDR1 + 1,
};
static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
@ -700,7 +700,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
[CLK_MBUS] = &mbus_clk.common.hw,
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
},
.num = CLK_NUMBER,
.num = CLK_I2S0 + 1,
};
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {

2
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
View File

@ -51,6 +51,4 @@
#define CLK_PLL_DDR1 74
#define CLK_NUMBER (CLK_I2S0 + 1)
#endif /* _CCU_SUN8I_H3_H_ */

4
drivers/clk/tegra/clk.c
View File

@ -231,8 +231,10 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
periph_banks = banks;
clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
if (!clks)
if (!clks) {
kfree(periph_clk_enb_refcnt);
return NULL;
}
clk_num = num;

1
drivers/clk/ti/clk-dra7-atl.c
View File

@ -233,7 +233,6 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
cinfo->iobase = of_iomap(node, 0);
cinfo->dev = &pdev->dev;
pm_runtime_enable(cinfo->dev);
pm_runtime_irq_safe(cinfo->dev);
pm_runtime_get_sync(cinfo->dev);
atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);

2
drivers/cpufreq/cpufreq-dt-platdev.c
View File

@ -121,6 +121,8 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "mediatek,mt8176", },
{ .compatible = "mediatek,mt8183", },
{ .compatible = "nvidia,tegra20", },
{ .compatible = "nvidia,tegra30", },
{ .compatible = "nvidia,tegra124", },
{ .compatible = "nvidia,tegra210", },

2
drivers/cpuidle/governors/teo.c
View File

@ -198,7 +198,7 @@ static void teo_update(struct cpuidle_driver *drv, struct cpuidle_device *dev)
* pattern detection.
*/
cpu_data->intervals[cpu_data->interval_idx++] = measured_ns;
if (cpu_data->interval_idx > INTERVALS)
if (cpu_data->interval_idx >= INTERVALS)
cpu_data->interval_idx = 0;
}

6
drivers/crypto/hisilicon/sec2/sec.h
View File

@ -40,7 +40,7 @@ struct sec_req {
int req_id;
/* Status of the SEC request */
int fake_busy;
atomic_t fake_busy;
};
/**
@ -132,8 +132,8 @@ struct sec_debug_file {
};
struct sec_dfx {
u64 send_cnt;
u64 recv_cnt;
atomic64_t send_cnt;
atomic64_t recv_cnt;
};
struct sec_debug {

12
drivers/crypto/hisilicon/sec2/sec_crypto.c
View File

@ -120,7 +120,7 @@ static void sec_req_cb(struct hisi_qp *qp, void *resp)
return;
}
__sync_add_and_fetch(&req->ctx->sec->debug.dfx.recv_cnt, 1);
atomic64_inc(&req->ctx->sec->debug.dfx.recv_cnt);
req->ctx->req_op->buf_unmap(req->ctx, req);
@ -135,13 +135,13 @@ static int sec_bd_send(struct sec_ctx *ctx, struct sec_req *req)
mutex_lock(&qp_ctx->req_lock);
ret = hisi_qp_send(qp_ctx->qp, &req->sec_sqe);
mutex_unlock(&qp_ctx->req_lock);
__sync_add_and_fetch(&ctx->sec->debug.dfx.send_cnt, 1);
atomic64_inc(&ctx->sec->debug.dfx.send_cnt);
if (ret == -EBUSY)
return -ENOBUFS;
if (!ret) {
if (req->fake_busy)
if (atomic_read(&req->fake_busy))
ret = -EBUSY;
else
ret = -EINPROGRESS;
@ -641,7 +641,7 @@ static void sec_skcipher_callback(struct sec_ctx *ctx, struct sec_req *req)
if (ctx->c_ctx.c_mode == SEC_CMODE_CBC && req->c_req.encrypt)
sec_update_iv(req);
if (__sync_bool_compare_and_swap(&req->fake_busy, 1, 0))
if (atomic_cmpxchg(&req->fake_busy, 1, 0) != 1)
sk_req->base.complete(&sk_req->base, -EINPROGRESS);
sk_req->base.complete(&sk_req->base, req->err_type);
@ -672,9 +672,9 @@ static int sec_request_init(struct sec_ctx *ctx, struct sec_req *req)
}
if (ctx->fake_req_limit <= atomic_inc_return(&qp_ctx->pending_reqs))
req->fake_busy = 1;
atomic_set(&req->fake_busy, 1);
else
req->fake_busy = 0;
atomic_set(&req->fake_busy, 0);
ret = ctx->req_op->get_res(ctx, req);
if (ret) {

14
drivers/crypto/hisilicon/sec2/sec_main.c
View File

@ -608,6 +608,14 @@ static const struct file_operations sec_dbg_fops = {
.write = sec_debug_write,
};
static int debugfs_atomic64_t_get(void *data, u64 *val)
{
*val = atomic64_read((atomic64_t *)data);
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(fops_atomic64_t_ro, debugfs_atomic64_t_get, NULL,
"%lld\n");
static int sec_core_debug_init(struct sec_dev *sec)
{
struct hisi_qm *qm = &sec->qm;
@ -628,9 +636,11 @@ static int sec_core_debug_init(struct sec_dev *sec)
debugfs_create_regset32("regs", 0444, tmp_d, regset);
debugfs_create_u64("send_cnt", 0444, tmp_d, &dfx->send_cnt);
debugfs_create_file("send_cnt", 0444, tmp_d, &dfx->send_cnt,
&fops_atomic64_t_ro);
debugfs_create_u64("recv_cnt", 0444, tmp_d, &dfx->recv_cnt);
debugfs_create_file("recv_cnt", 0444, tmp_d, &dfx->recv_cnt,
&fops_atomic64_t_ro);
return 0;
}

2
drivers/edac/sifive_edac.c
View File

@ -10,7 +10,7 @@
#include <linux/edac.h>
#include <linux/platform_device.h>
#include "edac_module.h"
#include <asm/sifive_l2_cache.h>
#include <soc/sifive/sifive_l2_cache.h>
#define DRVNAME "sifive_edac"

1
drivers/gpio/Kconfig
View File

@ -573,7 +573,6 @@ config GPIO_THUNDERX
tristate "Cavium ThunderX/OCTEON-TX GPIO"
depends on ARCH_THUNDER || (64BIT && COMPILE_TEST)
depends on PCI_MSI
select GPIOLIB_IRQCHIP
select IRQ_DOMAIN_HIERARCHY
select IRQ_FASTEOI_HIERARCHY_HANDLERS
help

161
drivers/gpio/gpio-thunderx.c
View File

@ -53,6 +53,7 @@ struct thunderx_line {
struct thunderx_gpio {
struct gpio_chip chip;
u8 __iomem *register_base;
struct irq_domain *irqd;
struct msix_entry *msix_entries; /* per line MSI-X */
struct thunderx_line *line_entries; /* per line irq info */
raw_spinlock_t lock;
@ -285,60 +286,54 @@ static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
}
}
static void thunderx_gpio_irq_ack(struct irq_data *d)
static void thunderx_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
writeq(GPIO_INTR_INTR,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txline->txgpio->register_base + intr_reg(txline->line));
}
static void thunderx_gpio_irq_mask(struct irq_data *d)
static void thunderx_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
writeq(GPIO_INTR_ENA_W1C,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txline->txgpio->register_base + intr_reg(txline->line));
}
static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
static void thunderx_gpio_irq_mask_ack(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txline->txgpio->register_base + intr_reg(txline->line));
}
static void thunderx_gpio_irq_unmask(struct irq_data *d)
static void thunderx_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
writeq(GPIO_INTR_ENA_W1S,
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txline->txgpio->register_base + intr_reg(txline->line));
}
static int thunderx_gpio_irq_set_type(struct irq_data *d,
static int thunderx_gpio_irq_set_type(struct irq_data *data,
unsigned int flow_type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_line *txline =
&txgpio->line_entries[irqd_to_hwirq(d)];
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
struct thunderx_gpio *txgpio = txline->txgpio;
u64 bit_cfg;
irqd_set_trigger_type(d, flow_type);
irqd_set_trigger_type(data, flow_type);
bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
irq_set_handler_locked(d, handle_fasteoi_ack_irq);
irq_set_handler_locked(data, handle_fasteoi_ack_irq);
bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
} else {
irq_set_handler_locked(d, handle_fasteoi_mask_irq);
irq_set_handler_locked(data, handle_fasteoi_mask_irq);
}
raw_spin_lock(&txgpio->lock);
@ -367,6 +362,33 @@ static void thunderx_gpio_irq_disable(struct irq_data *data)
irq_chip_disable_parent(data);
}
static int thunderx_gpio_irq_request_resources(struct irq_data *data)
{
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
struct thunderx_gpio *txgpio = txline->txgpio;
int r;
r = gpiochip_lock_as_irq(&txgpio->chip, txline->line);
if (r)
return r;
r = irq_chip_request_resources_parent(data);
if (r)
gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
return r;
}
static void thunderx_gpio_irq_release_resources(struct irq_data *data)
{
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
struct thunderx_gpio *txgpio = txline->txgpio;
irq_chip_release_resources_parent(data);
gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
}
/*
* Interrupts are chained from underlying MSI-X vectors. We have
* these irq_chip functions to be able to handle level triggering
@ -383,24 +405,50 @@ static struct irq_chip thunderx_gpio_irq_chip = {
.irq_unmask = thunderx_gpio_irq_unmask,
.irq_eoi = irq_chip_eoi_parent,
.irq_set_affinity = irq_chip_set_affinity_parent,
.irq_request_resources = thunderx_gpio_irq_request_resources,
.irq_release_resources = thunderx_gpio_irq_release_resources,
.irq_set_type = thunderx_gpio_irq_set_type,
.flags = IRQCHIP_SET_TYPE_MASKED
};
static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned int child,
unsigned int child_type,
unsigned int *parent,
unsigned int *parent_type)
static int thunderx_gpio_irq_translate(struct irq_domain *d,
struct irq_fwspec *fwspec,
irq_hw_number_t *hwirq,
unsigned int *type)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
struct thunderx_gpio *txgpio = d->host_data;
*parent = txgpio->base_msi + (2 * child);
*parent_type = IRQ_TYPE_LEVEL_HIGH;
if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
if (fwspec->param[0] >= txgpio->chip.ngpio)
return -EINVAL;
*hwirq = fwspec->param[0];
*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
return 0;
}
static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
struct thunderx_line *txline = arg;
return irq_domain_set_hwirq_and_chip(d, virq, txline->line,
&thunderx_gpio_irq_chip, txline);
}
static const struct irq_domain_ops thunderx_gpio_irqd_ops = {
.alloc = thunderx_gpio_irq_alloc,
.translate = thunderx_gpio_irq_translate
};
static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
return irq_find_mapping(txgpio->irqd, offset);
}
static int thunderx_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
@ -408,7 +456,6 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
struct device *dev = &pdev->dev;
struct thunderx_gpio *txgpio;
struct gpio_chip *chip;
struct gpio_irq_chip *girq;
int ngpio, i;
int err = 0;
@ -453,8 +500,8 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
}
txgpio->msix_entries = devm_kcalloc(dev,
ngpio, sizeof(struct msix_entry),
GFP_KERNEL);
ngpio, sizeof(struct msix_entry),
GFP_KERNEL);
if (!txgpio->msix_entries) {
err = -ENOMEM;
goto out;
@ -495,6 +542,27 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
if (err < 0)
goto out;
/*
* Push GPIO specific irqdomain on hierarchy created as a side
* effect of the pci_enable_msix()
*/
txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain,
0, 0, of_node_to_fwnode(dev->of_node),
&thunderx_gpio_irqd_ops, txgpio);
if (!txgpio->irqd) {
err = -ENOMEM;
goto out;
}
/* Push on irq_data and the domain for each line. */
for (i = 0; i < ngpio; i++) {
err = irq_domain_push_irq(txgpio->irqd,
txgpio->msix_entries[i].vector,
&txgpio->line_entries[i]);
if (err < 0)
dev_err(dev, "irq_domain_push_irq: %d\n", err);
}
chip->label = KBUILD_MODNAME;
chip->parent = dev;
chip->owner = THIS_MODULE;
@ -509,28 +577,11 @@ static int thunderx_gpio_probe(struct pci_dev *pdev,
chip->set = thunderx_gpio_set;
chip->set_multiple = thunderx_gpio_set_multiple;
chip->set_config = thunderx_gpio_set_config;
girq = &chip->irq;
girq->chip = &thunderx_gpio_irq_chip;
girq->fwnode = of_node_to_fwnode(dev->of_node);
girq->parent_domain =
irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
girq->handler = handle_bad_irq;
girq->default_type = IRQ_TYPE_NONE;
chip->to_irq = thunderx_gpio_to_irq;
err = devm_gpiochip_add_data(dev, chip, txgpio);
if (err)
goto out;
/* Push on irq_data and the domain for each line. */
for (i = 0; i < ngpio; i++) {
err = irq_domain_push_irq(chip->irq.domain,
txgpio->msix_entries[i].vector,
chip);
if (err < 0)
dev_err(dev, "irq_domain_push_irq: %d\n", err);
}
dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
ngpio, chip->base);
return 0;
@ -545,10 +596,10 @@ static void thunderx_gpio_remove(struct pci_dev *pdev)
struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
for (i = 0; i < txgpio->chip.ngpio; i++)
irq_domain_pop_irq(txgpio->chip.irq.domain,
irq_domain_pop_irq(txgpio->irqd,
txgpio->msix_entries[i].vector);
irq_domain_remove(txgpio->chip.irq.domain);
irq_domain_remove(txgpio->irqd);
pci_set_drvdata(pdev, NULL);
}

2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
View File

@ -254,7 +254,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
};
static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,

2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -817,8 +817,8 @@ static bool dc_link_detect_helper(struct dc_link *link,
}
case SIGNAL_TYPE_EDP: {
read_current_link_settings_on_detect(link);
detect_edp_sink_caps(link);
read_current_link_settings_on_detect(link);
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_EDP;
break;

39
drivers/gpu/drm/drm_dp_mst_topology.c
View File

@ -1190,6 +1190,8 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb,
txmsg->state == DRM_DP_SIDEBAND_TX_SENT) {
mstb->tx_slots[txmsg->seqno] = NULL;
}
mgr->is_waiting_for_dwn_reply = false;
}
out:
if (unlikely(ret == -EIO) && drm_debug_enabled(DRM_UT_DP)) {
@ -1199,6 +1201,7 @@ out:
}
mutex_unlock(&mgr->qlock);
drm_dp_mst_kick_tx(mgr);
return ret;
}
@ -2318,7 +2321,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb,
{
struct drm_dp_mst_topology_mgr *mgr = mstb->mgr;
struct drm_dp_mst_port *port;
int old_ddps, ret;
int old_ddps, old_input, ret, i;
u8 new_pdt;
bool dowork = false, create_connector = false;
@ -2349,6 +2352,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb,
}
old_ddps = port->ddps;
old_input = port->input;
port->input = conn_stat->input_port;
port->mcs = conn_stat->message_capability_status;
port->ldps = conn_stat->legacy_device_plug_status;
@ -2373,6 +2377,28 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb,
dowork = false;
}
if (!old_input && old_ddps != port->ddps && !port->ddps) {
for (i = 0; i < mgr->max_payloads; i++) {
struct drm_dp_vcpi *vcpi = mgr->proposed_vcpis[i];
struct drm_dp_mst_port *port_validated;
if (!vcpi)
continue;
port_validated =
container_of(vcpi, struct drm_dp_mst_port, vcpi);
port_validated =
drm_dp_mst_topology_get_port_validated(mgr, port_validated);
if (!port_validated) {
mutex_lock(&mgr->payload_lock);
vcpi->num_slots = 0;
mutex_unlock(&mgr->payload_lock);
} else {
drm_dp_mst_topology_put_port(port_validated);
}
}
}
if (port->connector)
drm_modeset_unlock(&mgr->base.lock);
else if (create_connector)
@ -2718,9 +2744,11 @@ static void process_single_down_tx_qlock(struct drm_dp_mst_topology_mgr *mgr)
ret = process_single_tx_qlock(mgr, txmsg, false);
if (ret == 1) {
/* txmsg is sent it should be in the slots now */
mgr->is_waiting_for_dwn_reply = true;
list_del(&txmsg->next);
} else if (ret) {
DRM_DEBUG_KMS("failed to send msg in q %d\n", ret);
mgr->is_waiting_for_dwn_reply = false;
list_del(&txmsg->next);
if (txmsg->seqno != -1)
txmsg->dst->tx_slots[txmsg->seqno] = NULL;
@ -2760,7 +2788,8 @@ static void drm_dp_queue_down_tx(struct drm_dp_mst_topology_mgr *mgr,
drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
}
if (list_is_singular(&mgr->tx_msg_downq))
if (list_is_singular(&mgr->tx_msg_downq) &&
!mgr->is_waiting_for_dwn_reply)
process_single_down_tx_qlock(mgr);
mutex_unlock(&mgr->qlock);
}
@ -3678,6 +3707,7 @@ static int drm_dp_mst_handle_down_rep(struct drm_dp_mst_topology_mgr *mgr)
mutex_lock(&mgr->qlock);
txmsg->state = DRM_DP_SIDEBAND_TX_RX;
mstb->tx_slots[slot] = NULL;
mgr->is_waiting_for_dwn_reply = false;
mutex_unlock(&mgr->qlock);
wake_up_all(&mgr->tx_waitq);
@ -3687,6 +3717,9 @@ static int drm_dp_mst_handle_down_rep(struct drm_dp_mst_topology_mgr *mgr)
no_msg:
drm_dp_mst_topology_put_mstb(mstb);
clear_down_rep_recv:
mutex_lock(&mgr->qlock);
mgr->is_waiting_for_dwn_reply = false;
mutex_unlock(&mgr->qlock);
memset(&mgr->down_rep_recv, 0, sizeof(struct drm_dp_sideband_msg_rx));
return 0;
@ -4497,7 +4530,7 @@ static void drm_dp_tx_work(struct work_struct *work)
struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, tx_work);
mutex_lock(&mgr->qlock);
if (!list_empty(&mgr->tx_msg_downq))
if (!list_empty(&mgr->tx_msg_downq) && !mgr->is_waiting_for_dwn_reply)
process_single_down_tx_qlock(mgr);
mutex_unlock(&mgr->qlock);
}

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