Linux 6.0-rc5
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAmMeQ2keHHRvcnZhbGRz QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGYRMH+gLNHiGirGZlm2GQ tKaZQUy7MiXuIP0hGDonDIIIAmIVhnjm9MDG8KT4W8AvEd7ukncyYqJfwWeWQPhP 4mZcf6l3Z8Ke+qiaFpXpMPCxTyWcln1ox0EoNx2g9gdPxZntaRuuaTQVljUfTiey aVPHxve8ip3G7jDoJnuLSxESOqWxkb8v/SshBP1E5bF5BZ+cgZRqq7FNigFqxjbk wF29K09BVOPjdgkSvY/b0/SnL5KlSdMAv+FrPcJNGivcdIPgf/qJks5cI2HRUo7o CpKgbcLorCVyD+d+zLonJBwIy3arbmKD8JqYnfdTSIqVOUqHXWUDfeydsH32u1Gu lPSI2Hw= =7LTL -----END PGP SIGNATURE----- Merge 6.0-rc5 into driver-core-next We need the driver core and debugfs changes in this branch. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
commit
a791dc1353
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@ -1,2 +1,4 @@
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Alan Cox <alan@lxorguk.ukuu.org.uk>
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Alan Cox <root@hraefn.swansea.linux.org.uk>
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Christoph Hellwig <hch@lst.de>
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Marc Gonzalez <marc.w.gonzalez@free.fr>
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6
.mailmap
6
.mailmap
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@ -98,8 +98,7 @@ Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
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Christian Marangi <ansuelsmth@gmail.com>
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Christophe Ricard <christophe.ricard@gmail.com>
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Christoph Hellwig <hch@lst.de>
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Colin Ian King <colin.king@intel.com> <colin.king@canonical.com>
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Colin Ian King <colin.king@intel.com> <colin.i.king@gmail.com>
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Colin Ian King <colin.i.king@gmail.com> <colin.king@canonical.com>
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Corey Minyard <minyard@acm.org>
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Damian Hobson-Garcia <dhobsong@igel.co.jp>
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Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
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@ -150,6 +149,8 @@ Greg Kroah-Hartman <gregkh@suse.de>
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Greg Kroah-Hartman <greg@kroah.com>
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Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
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Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
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Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@linux.vnet.ibm.com>
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Guilherme G. Piccoli <kernel@gpiccoli.net> <gpiccoli@canonical.com>
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Guo Ren <guoren@kernel.org> <guoren@linux.alibaba.com>
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Guo Ren <guoren@kernel.org> <ren_guo@c-sky.com>
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Gustavo Padovan <gustavo@las.ic.unicamp.br>
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@ -253,6 +254,7 @@ Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
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Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
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Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
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Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com>
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Luca Ceresoli <luca.ceresoli@bootlin.com> <luca@lucaceresoli.net>
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Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>
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Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
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Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org>
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@ -523,6 +523,7 @@ What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
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/sys/devices/system/cpu/vulnerabilities/retbleed
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Date: January 2018
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Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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Description: Information about CPU vulnerabilities
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@ -1,9 +1,9 @@
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.. _readme:
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Linux kernel release 5.x <http://kernel.org/>
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Linux kernel release 6.x <http://kernel.org/>
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=============================================
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These are the release notes for Linux version 5. Read them carefully,
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These are the release notes for Linux version 6. Read them carefully,
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as they tell you what this is all about, explain how to install the
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kernel, and what to do if something goes wrong.
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@ -63,7 +63,7 @@ Installing the kernel source
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directory where you have permissions (e.g. your home directory) and
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unpack it::
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xz -cd linux-5.x.tar.xz | tar xvf -
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xz -cd linux-6.x.tar.xz | tar xvf -
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Replace "X" with the version number of the latest kernel.
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@ -72,12 +72,12 @@ Installing the kernel source
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files. They should match the library, and not get messed up by
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whatever the kernel-du-jour happens to be.
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- You can also upgrade between 5.x releases by patching. Patches are
|
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- You can also upgrade between 6.x releases by patching. Patches are
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distributed in the xz format. To install by patching, get all the
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newer patch files, enter the top level directory of the kernel source
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(linux-5.x) and execute::
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(linux-6.x) and execute::
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xz -cd ../patch-5.x.xz | patch -p1
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xz -cd ../patch-6.x.xz | patch -p1
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Replace "x" for all versions bigger than the version "x" of your current
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source tree, **in_order**, and you should be ok. You may want to remove
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@ -85,13 +85,13 @@ Installing the kernel source
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that there are no failed patches (some-file-name# or some-file-name.rej).
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If there are, either you or I have made a mistake.
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Unlike patches for the 5.x kernels, patches for the 5.x.y kernels
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Unlike patches for the 6.x kernels, patches for the 6.x.y kernels
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(also known as the -stable kernels) are not incremental but instead apply
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directly to the base 5.x kernel. For example, if your base kernel is 5.0
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and you want to apply the 5.0.3 patch, you must not first apply the 5.0.1
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||||
and 5.0.2 patches. Similarly, if you are running kernel version 5.0.2 and
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||||
want to jump to 5.0.3, you must first reverse the 5.0.2 patch (that is,
|
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patch -R) **before** applying the 5.0.3 patch. You can read more on this in
|
||||
directly to the base 6.x kernel. For example, if your base kernel is 6.0
|
||||
and you want to apply the 6.0.3 patch, you must not first apply the 6.0.1
|
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and 6.0.2 patches. Similarly, if you are running kernel version 6.0.2 and
|
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want to jump to 6.0.3, you must first reverse the 6.0.2 patch (that is,
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patch -R) **before** applying the 6.0.3 patch. You can read more on this in
|
||||
:ref:`Documentation/process/applying-patches.rst <applying_patches>`.
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Alternatively, the script patch-kernel can be used to automate this
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@ -114,7 +114,7 @@ Installing the kernel source
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Software requirements
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---------------------
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Compiling and running the 5.x kernels requires up-to-date
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Compiling and running the 6.x kernels requires up-to-date
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versions of various software packages. Consult
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:ref:`Documentation/process/changes.rst <changes>` for the minimum version numbers
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required and how to get updates for these packages. Beware that using
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@ -132,12 +132,12 @@ Build directory for the kernel
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place for the output files (including .config).
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Example::
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kernel source code: /usr/src/linux-5.x
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kernel source code: /usr/src/linux-6.x
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build directory: /home/name/build/kernel
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To configure and build the kernel, use::
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cd /usr/src/linux-5.x
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cd /usr/src/linux-6.x
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make O=/home/name/build/kernel menuconfig
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make O=/home/name/build/kernel
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sudo make O=/home/name/build/kernel modules_install install
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@ -230,6 +230,20 @@ The possible values in this file are:
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* - 'Mitigation: Clear CPU buffers'
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- The processor is vulnerable and the CPU buffer clearing mitigation is
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enabled.
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* - 'Unknown: No mitigations'
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- The processor vulnerability status is unknown because it is
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out of Servicing period. Mitigation is not attempted.
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Definitions:
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------------
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Servicing period: The process of providing functional and security updates to
|
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Intel processors or platforms, utilizing the Intel Platform Update (IPU)
|
||||
process or other similar mechanisms.
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|
||||
End of Servicing Updates (ESU): ESU is the date at which Intel will no
|
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longer provide Servicing, such as through IPU or other similar update
|
||||
processes. ESU dates will typically be aligned to end of quarter.
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|
||||
If the processor is vulnerable then the following information is appended to
|
||||
the above information:
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|
|
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@ -5331,6 +5331,8 @@
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rodata= [KNL]
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on Mark read-only kernel memory as read-only (default).
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off Leave read-only kernel memory writable for debugging.
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full Mark read-only kernel memory and aliases as read-only
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[arm64]
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|
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rockchip.usb_uart
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Enable the uart passthrough on the designated usb port
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@ -50,10 +50,10 @@ For a short example, users can monitor the virtual address space of a given
|
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workload as below. ::
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# cd /sys/kernel/mm/damon/admin/
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# echo 1 > kdamonds/nr && echo 1 > kdamonds/0/contexts/nr
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# echo 1 > kdamonds/nr_kdamonds && echo 1 > kdamonds/0/contexts/nr_contexts
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# echo vaddr > kdamonds/0/contexts/0/operations
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# echo 1 > kdamonds/0/contexts/0/targets/nr
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# echo $(pidof <workload>) > kdamonds/0/contexts/0/targets/0/pid
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# echo 1 > kdamonds/0/contexts/0/targets/nr_targets
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# echo $(pidof <workload>) > kdamonds/0/contexts/0/targets/0/pid_target
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# echo on > kdamonds/0/state
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Files Hierarchy
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@ -366,12 +366,12 @@ memory rate becomes larger than 60%, or lower than 30%". ::
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# echo 1 > kdamonds/0/contexts/0/schemes/nr_schemes
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# cd kdamonds/0/contexts/0/schemes/0
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# # set the basic access pattern and the action
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# echo 4096 > access_patterns/sz/min
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# echo 8192 > access_patterns/sz/max
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# echo 0 > access_patterns/nr_accesses/min
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# echo 5 > access_patterns/nr_accesses/max
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# echo 10 > access_patterns/age/min
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# echo 20 > access_patterns/age/max
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# echo 4096 > access_pattern/sz/min
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# echo 8192 > access_pattern/sz/max
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# echo 0 > access_pattern/nr_accesses/min
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# echo 5 > access_pattern/nr_accesses/max
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# echo 10 > access_pattern/age/min
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# echo 20 > access_pattern/age/max
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# echo pageout > action
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# # set quotas
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# echo 10 > quotas/ms
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|
|
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|
|
@ -271,7 +271,7 @@ poll cycle or the number of packets processed reaches netdev_budget.
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netdev_max_backlog
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------------------
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Maximum number of packets, queued on the INPUT side, when the interface
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Maximum number of packets, queued on the INPUT side, when the interface
|
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receives packets faster than kernel can process them.
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netdev_rss_key
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|
|
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|
@ -242,44 +242,34 @@ HWCAP2_MTE3
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|||
by Documentation/arm64/memory-tagging-extension.rst.
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HWCAP2_SME
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|
||||
Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
|
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by Documentation/arm64/sme.rst.
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HWCAP2_SME_I16I64
|
||||
|
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Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
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HWCAP2_SME_F64F64
|
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|
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Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
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HWCAP2_SME_I8I32
|
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|
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Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
|
||||
|
||||
HWCAP2_SME_F16F32
|
||||
|
||||
Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
|
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|
||||
HWCAP2_SME_B16F32
|
||||
|
||||
Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
|
||||
|
||||
HWCAP2_SME_F32F32
|
||||
|
||||
Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
|
||||
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HWCAP2_SME_FA64
|
||||
|
||||
Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
|
||||
|
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HWCAP2_WFXT
|
||||
|
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Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
|
||||
|
||||
HWCAP2_EBF16
|
||||
|
||||
Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
|
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|
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4. Unused AT_HWCAP bits
|
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|
|
|
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|
|
@ -52,6 +52,8 @@ stable kernels.
|
|||
| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
|
||||
+----------------+-----------------+-----------------+-----------------------------+
|
||||
| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
|
||||
|
|
|
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|
|
@ -58,13 +58,11 @@ Like with atomic_t, the rule of thumb is:
|
|||
|
||||
- RMW operations that have a return value are fully ordered.
|
||||
|
||||
- RMW operations that are conditional are unordered on FAILURE,
|
||||
otherwise the above rules apply. In the case of test_and_set_bit_lock(),
|
||||
if the bit in memory is unchanged by the operation then it is deemed to have
|
||||
failed.
|
||||
- RMW operations that are conditional are fully ordered.
|
||||
|
||||
Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and
|
||||
clear_bit_unlock() which has RELEASE semantics.
|
||||
Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics,
|
||||
clear_bit_unlock() which has RELEASE semantics and test_bit_acquire which has
|
||||
ACQUIRE semantics.
|
||||
|
||||
Since a platform only has a single means of achieving atomic operations
|
||||
the same barriers as for atomic_t are used, see atomic_t.txt.
|
||||
|
|
|
|||
|
|
@ -23,3 +23,4 @@ Block
|
|||
stat
|
||||
switching-sched
|
||||
writeback_cache_control
|
||||
ublk
|
||||
|
|
|
|||
|
|
@ -0,0 +1,253 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
===========================================
|
||||
Userspace block device driver (ublk driver)
|
||||
===========================================
|
||||
|
||||
Overview
|
||||
========
|
||||
|
||||
ublk is a generic framework for implementing block device logic from userspace.
|
||||
The motivation behind it is that moving virtual block drivers into userspace,
|
||||
such as loop, nbd and similar can be very helpful. It can help to implement
|
||||
new virtual block device such as ublk-qcow2 (there are several attempts of
|
||||
implementing qcow2 driver in kernel).
|
||||
|
||||
Userspace block devices are attractive because:
|
||||
|
||||
- They can be written many programming languages.
|
||||
- They can use libraries that are not available in the kernel.
|
||||
- They can be debugged with tools familiar to application developers.
|
||||
- Crashes do not kernel panic the machine.
|
||||
- Bugs are likely to have a lower security impact than bugs in kernel
|
||||
code.
|
||||
- They can be installed and updated independently of the kernel.
|
||||
- They can be used to simulate block device easily with user specified
|
||||
parameters/setting for test/debug purpose
|
||||
|
||||
ublk block device (``/dev/ublkb*``) is added by ublk driver. Any IO request
|
||||
on the device will be forwarded to ublk userspace program. For convenience,
|
||||
in this document, ``ublk server`` refers to generic ublk userspace
|
||||
program. ``ublksrv`` [#userspace]_ is one of such implementation. It
|
||||
provides ``libublksrv`` [#userspace_lib]_ library for developing specific
|
||||
user block device conveniently, while also generic type block device is
|
||||
included, such as loop and null. Richard W.M. Jones wrote userspace nbd device
|
||||
``nbdublk`` [#userspace_nbdublk]_ based on ``libublksrv`` [#userspace_lib]_.
|
||||
|
||||
After the IO is handled by userspace, the result is committed back to the
|
||||
driver, thus completing the request cycle. This way, any specific IO handling
|
||||
logic is totally done by userspace, such as loop's IO handling, NBD's IO
|
||||
communication, or qcow2's IO mapping.
|
||||
|
||||
``/dev/ublkb*`` is driven by blk-mq request-based driver. Each request is
|
||||
assigned by one queue wide unique tag. ublk server assigns unique tag to each
|
||||
IO too, which is 1:1 mapped with IO of ``/dev/ublkb*``.
|
||||
|
||||
Both the IO request forward and IO handling result committing are done via
|
||||
``io_uring`` passthrough command; that is why ublk is also one io_uring based
|
||||
block driver. It has been observed that using io_uring passthrough command can
|
||||
give better IOPS than block IO; which is why ublk is one of high performance
|
||||
implementation of userspace block device: not only IO request communication is
|
||||
done by io_uring, but also the preferred IO handling in ublk server is io_uring
|
||||
based approach too.
|
||||
|
||||
ublk provides control interface to set/get ublk block device parameters.
|
||||
The interface is extendable and kabi compatible: basically any ublk request
|
||||
queue's parameter or ublk generic feature parameters can be set/get via the
|
||||
interface. Thus, ublk is generic userspace block device framework.
|
||||
For example, it is easy to setup a ublk device with specified block
|
||||
parameters from userspace.
|
||||
|
||||
Using ublk
|
||||
==========
|
||||
|
||||
ublk requires userspace ublk server to handle real block device logic.
|
||||
|
||||
Below is example of using ``ublksrv`` to provide ublk-based loop device.
|
||||
|
||||
- add a device::
|
||||
|
||||
ublk add -t loop -f ublk-loop.img
|
||||
|
||||
- format with xfs, then use it::
|
||||
|
||||
mkfs.xfs /dev/ublkb0
|
||||
mount /dev/ublkb0 /mnt
|
||||
# do anything. all IOs are handled by io_uring
|
||||
...
|
||||
umount /mnt
|
||||
|
||||
- list the devices with their info::
|
||||
|
||||
ublk list
|
||||
|
||||
- delete the device::
|
||||
|
||||
ublk del -a
|
||||
ublk del -n $ublk_dev_id
|
||||
|
||||
See usage details in README of ``ublksrv`` [#userspace_readme]_.
|
||||
|
||||
Design
|
||||
======
|
||||
|
||||
Control plane
|
||||
-------------
|
||||
|
||||
ublk driver provides global misc device node (``/dev/ublk-control``) for
|
||||
managing and controlling ublk devices with help of several control commands:
|
||||
|
||||
- ``UBLK_CMD_ADD_DEV``
|
||||
|
||||
Add a ublk char device (``/dev/ublkc*``) which is talked with ublk server
|
||||
WRT IO command communication. Basic device info is sent together with this
|
||||
command. It sets UAPI structure of ``ublksrv_ctrl_dev_info``,
|
||||
such as ``nr_hw_queues``, ``queue_depth``, and max IO request buffer size,
|
||||
for which the info is negotiated with the driver and sent back to the server.
|
||||
When this command is completed, the basic device info is immutable.
|
||||
|
||||
- ``UBLK_CMD_SET_PARAMS`` / ``UBLK_CMD_GET_PARAMS``
|
||||
|
||||
Set or get parameters of the device, which can be either generic feature
|
||||
related, or request queue limit related, but can't be IO logic specific,
|
||||
because the driver does not handle any IO logic. This command has to be
|
||||
sent before sending ``UBLK_CMD_START_DEV``.
|
||||
|
||||
- ``UBLK_CMD_START_DEV``
|
||||
|
||||
After the server prepares userspace resources (such as creating per-queue
|
||||
pthread & io_uring for handling ublk IO), this command is sent to the
|
||||
driver for allocating & exposing ``/dev/ublkb*``. Parameters set via
|
||||
``UBLK_CMD_SET_PARAMS`` are applied for creating the device.
|
||||
|
||||
- ``UBLK_CMD_STOP_DEV``
|
||||
|
||||
Halt IO on ``/dev/ublkb*`` and remove the device. When this command returns,
|
||||
ublk server will release resources (such as destroying per-queue pthread &
|
||||
io_uring).
|
||||
|
||||
- ``UBLK_CMD_DEL_DEV``
|
||||
|
||||
Remove ``/dev/ublkc*``. When this command returns, the allocated ublk device
|
||||
number can be reused.
|
||||
|
||||
- ``UBLK_CMD_GET_QUEUE_AFFINITY``
|
||||
|
||||
When ``/dev/ublkc`` is added, the driver creates block layer tagset, so
|
||||
that each queue's affinity info is available. The server sends
|
||||
``UBLK_CMD_GET_QUEUE_AFFINITY`` to retrieve queue affinity info. It can
|
||||
set up the per-queue context efficiently, such as bind affine CPUs with IO
|
||||
pthread and try to allocate buffers in IO thread context.
|
||||
|
||||
- ``UBLK_CMD_GET_DEV_INFO``
|
||||
|
||||
For retrieving device info via ``ublksrv_ctrl_dev_info``. It is the server's
|
||||
responsibility to save IO target specific info in userspace.
|
||||
|
||||
Data plane
|
||||
----------
|
||||
|
||||
ublk server needs to create per-queue IO pthread & io_uring for handling IO
|
||||
commands via io_uring passthrough. The per-queue IO pthread
|
||||
focuses on IO handling and shouldn't handle any control & management
|
||||
tasks.
|
||||
|
||||
The's IO is assigned by a unique tag, which is 1:1 mapping with IO
|
||||
request of ``/dev/ublkb*``.
|
||||
|
||||
UAPI structure of ``ublksrv_io_desc`` is defined for describing each IO from
|
||||
the driver. A fixed mmaped area (array) on ``/dev/ublkc*`` is provided for
|
||||
exporting IO info to the server; such as IO offset, length, OP/flags and
|
||||
buffer address. Each ``ublksrv_io_desc`` instance can be indexed via queue id
|
||||
and IO tag directly.
|
||||
|
||||
The following IO commands are communicated via io_uring passthrough command,
|
||||
and each command is only for forwarding the IO and committing the result
|
||||
with specified IO tag in the command data:
|
||||
|
||||
- ``UBLK_IO_FETCH_REQ``
|
||||
|
||||
Sent from the server IO pthread for fetching future incoming IO requests
|
||||
destined to ``/dev/ublkb*``. This command is sent only once from the server
|
||||
IO pthread for ublk driver to setup IO forward environment.
|
||||
|
||||
- ``UBLK_IO_COMMIT_AND_FETCH_REQ``
|
||||
|
||||
When an IO request is destined to ``/dev/ublkb*``, the driver stores
|
||||
the IO's ``ublksrv_io_desc`` to the specified mapped area; then the
|
||||
previous received IO command of this IO tag (either ``UBLK_IO_FETCH_REQ``
|
||||
or ``UBLK_IO_COMMIT_AND_FETCH_REQ)`` is completed, so the server gets
|
||||
the IO notification via io_uring.
|
||||
|
||||
After the server handles the IO, its result is committed back to the
|
||||
driver by sending ``UBLK_IO_COMMIT_AND_FETCH_REQ`` back. Once ublkdrv
|
||||
received this command, it parses the result and complete the request to
|
||||
``/dev/ublkb*``. In the meantime setup environment for fetching future
|
||||
requests with the same IO tag. That is, ``UBLK_IO_COMMIT_AND_FETCH_REQ``
|
||||
is reused for both fetching request and committing back IO result.
|
||||
|
||||
- ``UBLK_IO_NEED_GET_DATA``
|
||||
|
||||
With ``UBLK_F_NEED_GET_DATA`` enabled, the WRITE request will be firstly
|
||||
issued to ublk server without data copy. Then, IO backend of ublk server
|
||||
receives the request and it can allocate data buffer and embed its addr
|
||||
inside this new io command. After the kernel driver gets the command,
|
||||
data copy is done from request pages to this backend's buffer. Finally,
|
||||
backend receives the request again with data to be written and it can
|
||||
truly handle the request.
|
||||
|
||||
``UBLK_IO_NEED_GET_DATA`` adds one additional round-trip and one
|
||||
io_uring_enter() syscall. Any user thinks that it may lower performance
|
||||
should not enable UBLK_F_NEED_GET_DATA. ublk server pre-allocates IO
|
||||
buffer for each IO by default. Any new project should try to use this
|
||||
buffer to communicate with ublk driver. However, existing project may
|
||||
break or not able to consume the new buffer interface; that's why this
|
||||
command is added for backwards compatibility so that existing projects
|
||||
can still consume existing buffers.
|
||||
|
||||
- data copy between ublk server IO buffer and ublk block IO request
|
||||
|
||||
The driver needs to copy the block IO request pages into the server buffer
|
||||
(pages) first for WRITE before notifying the server of the coming IO, so
|
||||
that the server can handle WRITE request.
|
||||
|
||||
When the server handles READ request and sends
|
||||
``UBLK_IO_COMMIT_AND_FETCH_REQ`` to the server, ublkdrv needs to copy
|
||||
the server buffer (pages) read to the IO request pages.
|
||||
|
||||
Future development
|
||||
==================
|
||||
|
||||
Container-aware ublk deivice
|
||||
----------------------------
|
||||
|
||||
ublk driver doesn't handle any IO logic. Its function is well defined
|
||||
for now and very limited userspace interfaces are needed, which is also
|
||||
well defined too. It is possible to make ublk devices container-aware block
|
||||
devices in future as Stefan Hajnoczi suggested [#stefan]_, by removing
|
||||
ADMIN privilege.
|
||||
|
||||
Zero copy
|
||||
---------
|
||||
|
||||
Zero copy is a generic requirement for nbd, fuse or similar drivers. A
|
||||
problem [#xiaoguang]_ Xiaoguang mentioned is that pages mapped to userspace
|
||||
can't be remapped any more in kernel with existing mm interfaces. This can
|
||||
occurs when destining direct IO to ``/dev/ublkb*``. Also, he reported that
|
||||
big requests (IO size >= 256 KB) may benefit a lot from zero copy.
|
||||
|
||||
|
||||
References
|
||||
==========
|
||||
|
||||
.. [#userspace] https://github.com/ming1/ubdsrv
|
||||
|
||||
.. [#userspace_lib] https://github.com/ming1/ubdsrv/tree/master/lib
|
||||
|
||||
.. [#userspace_nbdublk] https://gitlab.com/rwmjones/libnbd/-/tree/nbdublk
|
||||
|
||||
.. [#userspace_readme] https://github.com/ming1/ubdsrv/blob/master/README
|
||||
|
||||
.. [#stefan] https://lore.kernel.org/linux-block/YoOr6jBfgVm8GvWg@stefanha-x1.localdomain/
|
||||
|
||||
.. [#xiaoguang] https://lore.kernel.org/linux-block/YoOr6jBfgVm8GvWg@stefanha-x1.localdomain/
|
||||
|
|
@ -86,6 +86,7 @@ if major >= 3:
|
|||
"__used",
|
||||
"__weak",
|
||||
"noinline",
|
||||
"__fix_address",
|
||||
|
||||
# include/linux/memblock.h:
|
||||
"__init_memblock",
|
||||
|
|
|
|||
|
|
@ -48,7 +48,6 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- intel,vm-map
|
||||
- clocks
|
||||
- resets
|
||||
- "#thermal-sensor-cells"
|
||||
|
|
|
|||
|
|
@ -60,6 +60,9 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -24,8 +24,10 @@ properties:
|
|||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Should be configured with type IRQ_TYPE_EDGE_RISING.
|
||||
If two interrupts are provided, expected order is INT1 and INT2.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- goodix,gt1151
|
||||
- goodix,gt1158
|
||||
- goodix,gt5663
|
||||
- goodix,gt5688
|
||||
- goodix,gt911
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ patternProperties:
|
|||
description: List of regulators and its properties
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
qcom,ocp-max-retries:
|
||||
|
|
@ -100,8 +101,6 @@ patternProperties:
|
|||
SAW controlled gang leader. Will be configured as SAW regulator.
|
||||
type: boolean
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
|
|
@ -17,9 +17,6 @@ description:
|
|||
acts as directory-based coherency manager.
|
||||
All the properties in ePAPR/DeviceTree specification applies for this platform.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -33,11 +30,16 @@ select:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-ccache
|
||||
- sifive,fu740-c000-ccache
|
||||
- const: cache
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-ccache
|
||||
- sifive,fu740-c000-ccache
|
||||
- const: cache
|
||||
- items:
|
||||
- const: microchip,mpfs-ccache
|
||||
- const: sifive,fu540-c000-ccache
|
||||
- const: cache
|
||||
|
||||
cache-block-size:
|
||||
const: 64
|
||||
|
|
@ -72,29 +74,46 @@ properties:
|
|||
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
|
||||
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: sifive,fu540-c000-ccache
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError and DataFail signals.
|
||||
maxItems: 3
|
||||
cache-sets:
|
||||
const: 1024
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- sifive,fu740-c000-ccache
|
||||
- microchip,mpfs-ccache
|
||||
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError, DataFail, DirFail signals.
|
||||
minItems: 4
|
||||
cache-sets:
|
||||
const: 2048
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError, DataFail, DirFail signals.
|
||||
minItems: 4
|
||||
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError and DataFail signals.
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: sifive,fu740-c000-ccache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 2048
|
||||
|
||||
else:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 1024
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -214,6 +214,7 @@ patternProperties:
|
|||
- polling-delay
|
||||
- polling-delay-passive
|
||||
- thermal-sensors
|
||||
- trips
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ properties:
|
|||
- mediatek,mt2712-mtu3
|
||||
- mediatek,mt8173-mtu3
|
||||
- mediatek,mt8183-mtu3
|
||||
- mediatek,mt8188-mtu3
|
||||
- mediatek,mt8192-mtu3
|
||||
- mediatek,mt8195-mtu3
|
||||
- const: mediatek,mtu3
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ properties:
|
|||
- qcom,sm6115-dwc3
|
||||
- qcom,sm6125-dwc3
|
||||
- qcom,sm6350-dwc3
|
||||
- qcom,sm6375-dwc3
|
||||
- qcom,sm8150-dwc3
|
||||
- qcom,sm8250-dwc3
|
||||
- qcom,sm8350-dwc3
|
||||
|
|
@ -108,12 +109,17 @@ properties:
|
|||
HS/FS/LS modes are supported.
|
||||
type: boolean
|
||||
|
||||
wakeup-source: true
|
||||
|
||||
# Required child node:
|
||||
|
||||
patternProperties:
|
||||
"^usb@[0-9a-f]+$":
|
||||
$ref: snps,dwc3.yaml#
|
||||
|
||||
properties:
|
||||
wakeup-source: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ correct address for this module, you could get in big trouble (read:
|
|||
crashes, data corruption, etc.). Try this only as a last resort (try BIOS
|
||||
updates first, for example), and backup first! An even more dangerous
|
||||
option is 'force_addr=<IOPORT>'. This will not only enable the PIIX4 like
|
||||
'force' foes, but it will also set a new base I/O port address. The SMBus
|
||||
'force' does, but it will also set a new base I/O port address. The SMBus
|
||||
parts of the PIIX4 needs a range of 8 of these addresses to function
|
||||
correctly. If these addresses are already reserved by some other device,
|
||||
you will get into big trouble! DON'T USE THIS IF YOU ARE NOT VERY SURE
|
||||
|
|
@ -86,15 +86,15 @@ If you own Force CPCI735 motherboard or other OSB4 based systems you may need
|
|||
to change the SMBus Interrupt Select register so the SMBus controller uses
|
||||
the SMI mode.
|
||||
|
||||
1) Use lspci command and locate the PCI device with the SMBus controller:
|
||||
1) Use ``lspci`` command and locate the PCI device with the SMBus controller:
|
||||
00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
|
||||
The line may vary for different chipsets. Please consult the driver source
|
||||
for all possible PCI ids (and lspci -n to match them). Lets assume the
|
||||
for all possible PCI ids (and ``lspci -n`` to match them). Let's assume the
|
||||
device is located at 00:0f.0.
|
||||
2) Now you just need to change the value in 0xD2 register. Get it first with
|
||||
command: lspci -xxx -s 00:0f.0
|
||||
command: ``lspci -xxx -s 00:0f.0``
|
||||
If the value is 0x3 then you need to change it to 0x1:
|
||||
setpci -s 00:0f.0 d2.b=1
|
||||
``setpci -s 00:0f.0 d2.b=1``
|
||||
|
||||
Please note that you don't need to do that in all cases, just when the SMBus is
|
||||
not working properly.
|
||||
|
|
@ -109,6 +109,3 @@ which can easily get corrupted due to a state machine bug. These are mostly
|
|||
Thinkpad laptops, but desktop systems may also be affected. We have no list
|
||||
of all affected systems, so the only safe solution was to prevent access to
|
||||
the SMBus on all IBM systems (detected using DMI data.)
|
||||
|
||||
For additional information, read:
|
||||
http://www.lm-sensors.org/browser/lm-sensors/trunk/README
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@ I2C muxes and complex topologies
|
|||
There are a couple of reasons for building more complex I2C topologies
|
||||
than a straight-forward I2C bus with one adapter and one or more devices.
|
||||
|
||||
Some example use cases are:
|
||||
|
||||
1. A mux may be needed on the bus to prevent address collisions.
|
||||
|
||||
2. The bus may be accessible from some external bus master, and arbitration
|
||||
|
|
@ -14,10 +16,10 @@ than a straight-forward I2C bus with one adapter and one or more devices.
|
|||
from the I2C bus, at least most of the time, and sits behind a gate
|
||||
that has to be operated before the device can be accessed.
|
||||
|
||||
Etc
|
||||
===
|
||||
Several types of hardware components such as I2C muxes, I2C gates and I2C
|
||||
arbitrators allow to handle such needs.
|
||||
|
||||
These constructs are represented as I2C adapter trees by Linux, where
|
||||
These components are represented as I2C adapter trees by Linux, where
|
||||
each adapter has a parent adapter (except the root adapter) and zero or
|
||||
more child adapters. The root adapter is the actual adapter that issues
|
||||
I2C transfers, and all adapters with a parent are part of an "i2c-mux"
|
||||
|
|
@ -35,46 +37,7 @@ Locking
|
|||
=======
|
||||
|
||||
There are two variants of locking available to I2C muxes, they can be
|
||||
mux-locked or parent-locked muxes. As is evident from below, it can be
|
||||
useful to know if a mux is mux-locked or if it is parent-locked. The
|
||||
following list was correct at the time of writing:
|
||||
|
||||
In drivers/i2c/muxes/:
|
||||
|
||||
====================== =============================================
|
||||
i2c-arb-gpio-challenge Parent-locked
|
||||
i2c-mux-gpio Normally parent-locked, mux-locked iff
|
||||
all involved gpio pins are controlled by the
|
||||
same I2C root adapter that they mux.
|
||||
i2c-mux-gpmux Normally parent-locked, mux-locked iff
|
||||
specified in device-tree.
|
||||
i2c-mux-ltc4306 Mux-locked
|
||||
i2c-mux-mlxcpld Parent-locked
|
||||
i2c-mux-pca9541 Parent-locked
|
||||
i2c-mux-pca954x Parent-locked
|
||||
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
|
||||
all involved pinctrl devices are controlled
|
||||
by the same I2C root adapter that they mux.
|
||||
i2c-mux-reg Parent-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/iio/:
|
||||
|
||||
====================== =============================================
|
||||
gyro/mpu3050 Mux-locked
|
||||
imu/inv_mpu6050/ Mux-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/media/:
|
||||
|
||||
======================= =============================================
|
||||
dvb-frontends/lgdt3306a Mux-locked
|
||||
dvb-frontends/m88ds3103 Parent-locked
|
||||
dvb-frontends/rtl2830 Parent-locked
|
||||
dvb-frontends/rtl2832 Mux-locked
|
||||
dvb-frontends/si2168 Mux-locked
|
||||
usb/cx231xx/ Parent-locked
|
||||
======================= =============================================
|
||||
mux-locked or parent-locked muxes.
|
||||
|
||||
|
||||
Mux-locked muxes
|
||||
|
|
@ -89,40 +52,8 @@ full transaction, unrelated I2C transfers may interleave the different
|
|||
stages of the transaction. This has the benefit that the mux driver
|
||||
may be easier and cleaner to implement, but it has some caveats.
|
||||
|
||||
==== =====================================================================
|
||||
ML1. If you build a topology with a mux-locked mux being the parent
|
||||
of a parent-locked mux, this might break the expectation from the
|
||||
parent-locked mux that the root adapter is locked during the
|
||||
transaction.
|
||||
|
||||
ML2. It is not safe to build arbitrary topologies with two (or more)
|
||||
mux-locked muxes that are not siblings, when there are address
|
||||
collisions between the devices on the child adapters of these
|
||||
non-sibling muxes.
|
||||
|
||||
I.e. the select-transfer-deselect transaction targeting e.g. device
|
||||
address 0x42 behind mux-one may be interleaved with a similar
|
||||
operation targeting device address 0x42 behind mux-two. The
|
||||
intension with such a topology would in this hypothetical example
|
||||
be that mux-one and mux-two should not be selected simultaneously,
|
||||
but mux-locked muxes do not guarantee that in all topologies.
|
||||
|
||||
ML3. A mux-locked mux cannot be used by a driver for auto-closing
|
||||
gates/muxes, i.e. something that closes automatically after a given
|
||||
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
|
||||
may creep in and close prematurely.
|
||||
|
||||
ML4. If any non-I2C operation in the mux driver changes the I2C mux state,
|
||||
the driver has to lock the root adapter during that operation.
|
||||
Otherwise garbage may appear on the bus as seen from devices
|
||||
behind the mux, when an unrelated I2C transfer is in flight during
|
||||
the non-I2C mux-changing operation.
|
||||
==== =====================================================================
|
||||
|
||||
|
||||
Mux-locked Example
|
||||
------------------
|
||||
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
|
|
@ -153,6 +84,43 @@ This means that accesses to D2 are lockout out for the full duration
|
|||
of the entire operation. But accesses to D3 are possibly interleaved
|
||||
at any point.
|
||||
|
||||
Mux-locked caveats
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
When using a mux-locked mux, be aware of the following restrictions:
|
||||
|
||||
[ML1]
|
||||
If you build a topology with a mux-locked mux being the parent
|
||||
of a parent-locked mux, this might break the expectation from the
|
||||
parent-locked mux that the root adapter is locked during the
|
||||
transaction.
|
||||
|
||||
[ML2]
|
||||
It is not safe to build arbitrary topologies with two (or more)
|
||||
mux-locked muxes that are not siblings, when there are address
|
||||
collisions between the devices on the child adapters of these
|
||||
non-sibling muxes.
|
||||
|
||||
I.e. the select-transfer-deselect transaction targeting e.g. device
|
||||
address 0x42 behind mux-one may be interleaved with a similar
|
||||
operation targeting device address 0x42 behind mux-two. The
|
||||
intent with such a topology would in this hypothetical example
|
||||
be that mux-one and mux-two should not be selected simultaneously,
|
||||
but mux-locked muxes do not guarantee that in all topologies.
|
||||
|
||||
[ML3]
|
||||
A mux-locked mux cannot be used by a driver for auto-closing
|
||||
gates/muxes, i.e. something that closes automatically after a given
|
||||
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
|
||||
may creep in and close prematurely.
|
||||
|
||||
[ML4]
|
||||
If any non-I2C operation in the mux driver changes the I2C mux state,
|
||||
the driver has to lock the root adapter during that operation.
|
||||
Otherwise garbage may appear on the bus as seen from devices
|
||||
behind the mux, when an unrelated I2C transfer is in flight during
|
||||
the non-I2C mux-changing operation.
|
||||
|
||||
|
||||
Parent-locked muxes
|
||||
-------------------
|
||||
|
|
@ -161,28 +129,10 @@ Parent-locked muxes lock the parent adapter during the full select-
|
|||
transfer-deselect transaction. The implication is that the mux driver
|
||||
has to ensure that any and all I2C transfers through that parent
|
||||
adapter during the transaction are unlocked I2C transfers (using e.g.
|
||||
__i2c_transfer), or a deadlock will follow. There are a couple of
|
||||
caveats.
|
||||
|
||||
==== ====================================================================
|
||||
PL1. If you build a topology with a parent-locked mux being the child
|
||||
of another mux, this might break a possible assumption from the
|
||||
child mux that the root adapter is unused between its select op
|
||||
and the actual transfer (e.g. if the child mux is auto-closing
|
||||
and the parent mux issues I2C transfers as part of its select).
|
||||
This is especially the case if the parent mux is mux-locked, but
|
||||
it may also happen if the parent mux is parent-locked.
|
||||
|
||||
PL2. If select/deselect calls out to other subsystems such as gpio,
|
||||
pinctrl, regmap or iio, it is essential that any I2C transfers
|
||||
caused by these subsystems are unlocked. This can be convoluted to
|
||||
accomplish, maybe even impossible if an acceptably clean solution
|
||||
is sought.
|
||||
==== ====================================================================
|
||||
|
||||
__i2c_transfer), or a deadlock will follow.
|
||||
|
||||
Parent-locked Example
|
||||
---------------------
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
|
|
@ -212,10 +162,30 @@ When there is an access to D1, this happens:
|
|||
9. M1 unlocks its parent adapter.
|
||||
10. M1 unlocks muxes on its parent.
|
||||
|
||||
|
||||
This means that accesses to both D2 and D3 are locked out for the full
|
||||
duration of the entire operation.
|
||||
|
||||
Parent-locked Caveats
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
When using a parent-locked mux, be aware of the following restrictions:
|
||||
|
||||
[PL1]
|
||||
If you build a topology with a parent-locked mux being the child
|
||||
of another mux, this might break a possible assumption from the
|
||||
child mux that the root adapter is unused between its select op
|
||||
and the actual transfer (e.g. if the child mux is auto-closing
|
||||
and the parent mux issues I2C transfers as part of its select).
|
||||
This is especially the case if the parent mux is mux-locked, but
|
||||
it may also happen if the parent mux is parent-locked.
|
||||
|
||||
[PL2]
|
||||
If select/deselect calls out to other subsystems such as gpio,
|
||||
pinctrl, regmap or iio, it is essential that any I2C transfers
|
||||
caused by these subsystems are unlocked. This can be convoluted to
|
||||
accomplish, maybe even impossible if an acceptably clean solution
|
||||
is sought.
|
||||
|
||||
|
||||
Complex Examples
|
||||
================
|
||||
|
|
@ -261,8 +231,10 @@ This is a good topology::
|
|||
When device D1 is accessed, accesses to D2 are locked out for the
|
||||
full duration of the operation (muxes on the top child adapter of M1
|
||||
are locked). But accesses to D3 and D4 are possibly interleaved at
|
||||
any point. Accesses to D3 locks out D1 and D2, but accesses to D4
|
||||
are still possibly interleaved.
|
||||
any point.
|
||||
|
||||
Accesses to D3 locks out D1 and D2, but accesses to D4 are still possibly
|
||||
interleaved.
|
||||
|
||||
|
||||
Mux-locked mux as parent of parent-locked mux
|
||||
|
|
@ -394,3 +366,47 @@ This is a good topology::
|
|||
When D1 or D2 are accessed, accesses to D3 and D4 are locked out while
|
||||
accesses to D5 may interleave. When D3 or D4 are accessed, accesses to
|
||||
all other devices are locked out.
|
||||
|
||||
|
||||
Mux type of existing device drivers
|
||||
===================================
|
||||
|
||||
Whether a device is mux-locked or parent-locked depends on its
|
||||
implementation. The following list was correct at the time of writing:
|
||||
|
||||
In drivers/i2c/muxes/:
|
||||
|
||||
====================== =============================================
|
||||
i2c-arb-gpio-challenge Parent-locked
|
||||
i2c-mux-gpio Normally parent-locked, mux-locked iff
|
||||
all involved gpio pins are controlled by the
|
||||
same I2C root adapter that they mux.
|
||||
i2c-mux-gpmux Normally parent-locked, mux-locked iff
|
||||
specified in device-tree.
|
||||
i2c-mux-ltc4306 Mux-locked
|
||||
i2c-mux-mlxcpld Parent-locked
|
||||
i2c-mux-pca9541 Parent-locked
|
||||
i2c-mux-pca954x Parent-locked
|
||||
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
|
||||
all involved pinctrl devices are controlled
|
||||
by the same I2C root adapter that they mux.
|
||||
i2c-mux-reg Parent-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/iio/:
|
||||
|
||||
====================== =============================================
|
||||
gyro/mpu3050 Mux-locked
|
||||
imu/inv_mpu6050/ Mux-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/media/:
|
||||
|
||||
======================= =============================================
|
||||
dvb-frontends/lgdt3306a Mux-locked
|
||||
dvb-frontends/m88ds3103 Parent-locked
|
||||
dvb-frontends/rtl2830 Parent-locked
|
||||
dvb-frontends/rtl2832 Mux-locked
|
||||
dvb-frontends/si2168 Mux-locked
|
||||
usb/cx231xx/ Parent-locked
|
||||
======================= =============================================
|
||||
|
|
|
|||
|
|
@ -517,6 +517,7 @@ All I-Force devices are supported by the iforce module. This includes:
|
|||
* AVB Mag Turbo Force
|
||||
* AVB Top Shot Pegasus
|
||||
* AVB Top Shot Force Feedback Racing Wheel
|
||||
* Boeder Force Feedback Wheel
|
||||
* Logitech WingMan Force
|
||||
* Logitech WingMan Force Wheel
|
||||
* Guillemot Race Leader Force Feedback
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ The ``netdevsim`` driver supports rate objects management, which includes:
|
|||
- setting tx_share and tx_max rate values for any rate object type;
|
||||
- setting parent node for any rate object type.
|
||||
|
||||
Rate nodes and it's parameters are exposed in ``netdevsim`` debugfs in RO mode.
|
||||
Rate nodes and their parameters are exposed in ``netdevsim`` debugfs in RO mode.
|
||||
For example created rate node with name ``some_group``:
|
||||
|
||||
.. code:: shell
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Transmit path guidelines:
|
|||
|
||||
1) The ndo_start_xmit method must not return NETDEV_TX_BUSY under
|
||||
any normal circumstances. It is considered a hard error unless
|
||||
there is no way your device can tell ahead of time when it's
|
||||
there is no way your device can tell ahead of time when its
|
||||
transmit function will become busy.
|
||||
|
||||
Instead it must maintain the queue properly. For example,
|
||||
|
|
|
|||
|
|
@ -1035,7 +1035,10 @@ tcp_limit_output_bytes - INTEGER
|
|||
tcp_challenge_ack_limit - INTEGER
|
||||
Limits number of Challenge ACK sent per second, as recommended
|
||||
in RFC 5961 (Improving TCP's Robustness to Blind In-Window Attacks)
|
||||
Default: 1000
|
||||
Note that this per netns rate limit can allow some side channel
|
||||
attacks and probably should not be enabled.
|
||||
TCP stack implements per TCP socket limits anyway.
|
||||
Default: INT_MAX (unlimited)
|
||||
|
||||
UDP variables
|
||||
=============
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ Initial Release:
|
|||
================
|
||||
This is conceptually very similar to the macvlan driver with one major
|
||||
exception of using L3 for mux-ing /demux-ing among slaves. This property makes
|
||||
the master device share the L2 with it's slave devices. I have developed this
|
||||
the master device share the L2 with its slave devices. I have developed this
|
||||
driver in conjunction with network namespaces and not sure if there is use case
|
||||
outside of it.
|
||||
|
||||
|
|
|
|||
|
|
@ -530,7 +530,7 @@ its tunnel close actions. For L2TPIP sockets, the socket's close
|
|||
handler initiates the same tunnel close actions. All sessions are
|
||||
first closed. Each session drops its tunnel ref. When the tunnel ref
|
||||
reaches zero, the tunnel puts its socket ref. When the socket is
|
||||
eventually destroyed, it's sk_destruct finally frees the L2TP tunnel
|
||||
eventually destroyed, its sk_destruct finally frees the L2TP tunnel
|
||||
context.
|
||||
|
||||
Sessions
|
||||
|
|
|
|||
|
|
@ -1055,17 +1055,6 @@ The kernel interface functions are as follows:
|
|||
first function to change. Note that this must be called in TASK_RUNNING
|
||||
state.
|
||||
|
||||
(#) Get reply timestamp::
|
||||
|
||||
bool rxrpc_kernel_get_reply_time(struct socket *sock,
|
||||
struct rxrpc_call *call,
|
||||
ktime_t *_ts)
|
||||
|
||||
This allows the timestamp on the first DATA packet of the reply of a
|
||||
client call to be queried, provided that it is still in the Rx ring. If
|
||||
successful, the timestamp will be stored into ``*_ts`` and true will be
|
||||
returned; false will be returned otherwise.
|
||||
|
||||
(#) Get remote client epoch::
|
||||
|
||||
u32 rxrpc_kernel_get_epoch(struct socket *sock,
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@ tools such as iproute2.
|
|||
|
||||
The switchdev driver can know a particular port's position in the topology by
|
||||
monitoring NETDEV_CHANGEUPPER notifications. For example, a port moved into a
|
||||
bond will see it's upper master change. If that bond is moved into a bridge,
|
||||
bond will see its upper master change. If that bond is moved into a bridge,
|
||||
the bond's upper master will change. And so on. The driver will track such
|
||||
movements to know what position a port is in in the overall topology by
|
||||
registering for netdevice events and acting on NETDEV_CHANGEUPPER.
|
||||
|
|
|
|||
|
|
@ -70,8 +70,16 @@
|
|||
|
||||
% Translations have Asian (CJK) characters which are only displayed if
|
||||
% xeCJK is used
|
||||
\usepackage{ifthen}
|
||||
\newboolean{enablecjk}
|
||||
\setboolean{enablecjk}{false}
|
||||
\IfFontExistsTF{Noto Sans CJK SC}{
|
||||
% Load xeCJK when CJK font is available
|
||||
\IfFileExists{xeCJK.sty}{
|
||||
\setboolean{enablecjk}{true}
|
||||
}{}
|
||||
}{}
|
||||
\ifthenelse{\boolean{enablecjk}}{
|
||||
% Load xeCJK when both the Noto Sans CJK font and xeCJK.sty are available.
|
||||
\usepackage{xeCJK}
|
||||
% Noto CJK fonts don't provide slant shape. [AutoFakeSlant] permits
|
||||
% its emulation.
|
||||
|
|
@ -196,7 +204,7 @@
|
|||
% Inactivate CJK after tableofcontents
|
||||
\apptocmd{\sphinxtableofcontents}{\kerneldocCJKoff}{}{}
|
||||
\xeCJKsetup{CJKspace = true}% For inter-phrase space of Korean TOC
|
||||
}{ % No CJK font found
|
||||
}{ % Don't enable CJK
|
||||
% Custom macros to on/off CJK and switch CJK fonts (Dummy)
|
||||
\newcommand{\kerneldocCJKon}{}
|
||||
\newcommand{\kerneldocCJKoff}{}
|
||||
|
|
@ -204,14 +212,16 @@
|
|||
%% and ignore the argument (#1) in their definitions, whole contents of
|
||||
%% CJK chapters can be ignored.
|
||||
\newcommand{\kerneldocBeginSC}[1]{%
|
||||
%% Put a note on missing CJK fonts in place of zh_CN translation.
|
||||
\begin{sphinxadmonition}{note}{Note on missing fonts:}
|
||||
%% Put a note on missing CJK fonts or the xecjk package in place of
|
||||
%% zh_CN translation.
|
||||
\begin{sphinxadmonition}{note}{Note on missing fonts and a package:}
|
||||
Translations of Simplified Chinese (zh\_CN), Traditional Chinese
|
||||
(zh\_TW), Korean (ko\_KR), and Japanese (ja\_JP) were skipped
|
||||
due to the lack of suitable font families.
|
||||
due to the lack of suitable font families and/or the texlive-xecjk
|
||||
package.
|
||||
|
||||
If you want them, please install ``Noto Sans CJK'' font families
|
||||
by following instructions from
|
||||
along with the texlive-xecjk package by following instructions from
|
||||
\sphinxcode{./scripts/sphinx-pre-install}.
|
||||
Having optional ``Noto Serif CJK'' font families will improve
|
||||
the looks of those translations.
|
||||
|
|
|
|||
|
|
@ -35,8 +35,7 @@ Linux カーネルに変更を加えたいと思っている個人又は会社
|
|||
てもらえやすくする提案を集めたものです。
|
||||
|
||||
コードを投稿する前に、Documentation/process/submit-checklist.rst の項目リストに目
|
||||
を通してチェックしてください。もしあなたがドライバーを投稿しようとし
|
||||
ているなら、Documentation/process/submitting-drivers.rst にも目を通してください。
|
||||
を通してチェックしてください。
|
||||
|
||||
--------------------------------------------
|
||||
セクション1 パッチの作り方と送り方
|
||||
|
|
|
|||
33
MAINTAINERS
33
MAINTAINERS
|
|
@ -3612,6 +3612,7 @@ F: include/linux/find.h
|
|||
F: include/linux/nodemask.h
|
||||
F: lib/bitmap.c
|
||||
F: lib/cpumask.c
|
||||
F: lib/cpumask_kunit.c
|
||||
F: lib/find_bit.c
|
||||
F: lib/find_bit_benchmark.c
|
||||
F: lib/test_bitmap.c
|
||||
|
|
@ -3679,6 +3680,7 @@ F: Documentation/networking/bonding.rst
|
|||
F: drivers/net/bonding/
|
||||
F: include/net/bond*
|
||||
F: include/uapi/linux/if_bonding.h
|
||||
F: tools/testing/selftests/drivers/net/bonding/
|
||||
|
||||
BOSCH SENSORTEC BMA400 ACCELEROMETER IIO DRIVER
|
||||
M: Dan Robertson <dan@dlrobertson.com>
|
||||
|
|
@ -9208,8 +9210,8 @@ F: Documentation/ABI/testing/debugfs-hisi-zip
|
|||
F: drivers/crypto/hisilicon/zip/
|
||||
|
||||
HISILICON ROCE DRIVER
|
||||
M: Haoyue Xu <xuhaoyue1@hisilicon.com>
|
||||
M: Wenpeng Liang <liangwenpeng@huawei.com>
|
||||
M: Weihang Li <liweihang@huawei.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
|
||||
|
|
@ -9783,7 +9785,7 @@ M: Christian Brauner <brauner@kernel.org>
|
|||
M: Seth Forshee <sforshee@kernel.org>
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git
|
||||
T: git://git.kernel.org/pub/scm/linux/kernel/git/vfs/idmapping.git
|
||||
F: Documentation/filesystems/idmappings.rst
|
||||
F: tools/testing/selftests/mount_setattr/
|
||||
F: include/linux/mnt_idmapping.h
|
||||
|
|
@ -10032,6 +10034,7 @@ F: Documentation/devicetree/bindings/input/
|
|||
F: Documentation/devicetree/bindings/serio/
|
||||
F: Documentation/input/
|
||||
F: drivers/input/
|
||||
F: include/dt-bindings/input/
|
||||
F: include/linux/input.h
|
||||
F: include/linux/input/
|
||||
F: include/uapi/linux/input-event-codes.h
|
||||
|
|
@ -10660,6 +10663,7 @@ T: git git://git.kernel.dk/linux-block
|
|||
T: git git://git.kernel.dk/liburing
|
||||
F: io_uring/
|
||||
F: include/linux/io_uring.h
|
||||
F: include/linux/io_uring_types.h
|
||||
F: include/uapi/linux/io_uring.h
|
||||
F: tools/io_uring/
|
||||
|
||||
|
|
@ -17530,9 +17534,19 @@ M: Conor Dooley <conor.dooley@microchip.com>
|
|||
M: Daire McNamara <daire.mcnamara@microchip.com>
|
||||
L: linux-riscv@lists.infradead.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
|
||||
F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
|
||||
F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
|
||||
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
|
||||
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
|
||||
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
|
||||
F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
|
||||
F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
|
||||
F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
|
||||
F: arch/riscv/boot/dts/microchip/
|
||||
F: drivers/char/hw_random/mpfs-rng.c
|
||||
F: drivers/clk/microchip/clk-mpfs.c
|
||||
F: drivers/i2c/busses/i2c-microchip-core.c
|
||||
F: drivers/mailbox/mailbox-mpfs.c
|
||||
F: drivers/pci/controller/pcie-microchip-host.c
|
||||
F: drivers/rtc/rtc-mpfs.c
|
||||
|
|
@ -17733,6 +17747,17 @@ L: linux-rdma@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/infiniband/ulp/rtrs/
|
||||
|
||||
RUNTIME VERIFICATION (RV)
|
||||
M: Daniel Bristot de Oliveira <bristot@kernel.org>
|
||||
M: Steven Rostedt <rostedt@goodmis.org>
|
||||
L: linux-trace-devel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/trace/rv/
|
||||
F: include/linux/rv.h
|
||||
F: include/rv/
|
||||
F: kernel/trace/rv/
|
||||
F: tools/verification/
|
||||
|
||||
RXRPC SOCKETS (AF_RXRPC)
|
||||
M: David Howells <dhowells@redhat.com>
|
||||
M: Marc Dionne <marc.dionne@auristor.com>
|
||||
|
|
@ -20599,6 +20624,7 @@ F: include/*/ftrace.h
|
|||
F: include/linux/trace*.h
|
||||
F: include/trace/
|
||||
F: kernel/trace/
|
||||
F: scripts/tracing/
|
||||
F: tools/testing/selftests/ftrace/
|
||||
|
||||
TRACING MMIO ACCESSES (MMIOTRACE)
|
||||
|
|
@ -20763,6 +20789,7 @@ UBLK USERSPACE BLOCK DRIVER
|
|||
M: Ming Lei <ming.lei@redhat.com>
|
||||
L: linux-block@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/block/ublk.rst
|
||||
F: drivers/block/ublk_drv.c
|
||||
F: include/uapi/linux/ublk_cmd.h
|
||||
|
||||
|
|
@ -22304,7 +22331,7 @@ M: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
|
|||
R: Srinivas Neeli <srinivas.neeli@xilinx.com>
|
||||
R: Michal Simek <michal.simek@xilinx.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
|
||||
F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
|
||||
F: Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
|
||||
F: drivers/gpio/gpio-xilinx.c
|
||||
F: drivers/gpio/gpio-zynq.c
|
||||
|
|
|
|||
5
Makefile
5
Makefile
|
|
@ -2,7 +2,7 @@
|
|||
VERSION = 6
|
||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Hurr durr I'ma ninja sloth
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -1287,8 +1287,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
|||
|
||||
PHONY += headers
|
||||
headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(if $(filter um, $(SRCARCH)), $(error Headers not exportable for UML))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
$(Q)$(MAKE) $(hdr-inst)=arch/$(SRCARCH)/include/uapi
|
||||
|
||||
|
|
|
|||
|
|
@ -923,6 +923,9 @@ config HAVE_SOFTIRQ_ON_OWN_STACK
|
|||
Architecture provides a function to run __do_softirq() on a
|
||||
separate stack.
|
||||
|
||||
config SOFTIRQ_ON_OWN_STACK
|
||||
def_bool HAVE_SOFTIRQ_ON_OWN_STACK && !PREEMPT_RT
|
||||
|
||||
config ALTERNATE_USER_ADDRESS_SPACE
|
||||
bool
|
||||
help
|
||||
|
|
|
|||
|
|
@ -283,11 +283,8 @@ arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
|
|||
return (old & mask) != 0;
|
||||
}
|
||||
|
||||
static __always_inline bool
|
||||
arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
|
||||
{
|
||||
return (1UL & (((const int *) addr)[nr >> 5] >> (nr & 31))) != 0UL;
|
||||
}
|
||||
#define arch_test_bit generic_test_bit
|
||||
#define arch_test_bit_acquire generic_test_bit_acquire
|
||||
|
||||
/*
|
||||
* ffz = Find First Zero in word. Undefined if no zero exists,
|
||||
|
|
|
|||
|
|
@ -399,7 +399,7 @@
|
|||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdog: watchdog@10010000 {
|
||||
|
|
|
|||
|
|
@ -410,7 +410,7 @@
|
|||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial0: serial@1010c000 {
|
||||
|
|
|
|||
|
|
@ -555,7 +555,7 @@
|
|||
interrupt-parent = <&intc_pb11mp>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
};
|
||||
|
||||
watchdog@1000f000 {
|
||||
|
|
|
|||
|
|
@ -390,7 +390,7 @@
|
|||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdog0: watchdog@1000f000 {
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@
|
|||
regulators {
|
||||
vdd_3v3: VDD_IO {
|
||||
regulator-name = "VDD_IO";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -95,8 +95,8 @@
|
|||
|
||||
vddio_ddr: VDD_DDR {
|
||||
regulator-name = "VDD_DDR";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -118,8 +118,8 @@
|
|||
|
||||
vdd_core: VDD_CORE {
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -160,8 +160,8 @@
|
|||
|
||||
LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
|
|
@ -175,9 +175,8 @@
|
|||
|
||||
LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
|
|
|
|||
|
|
@ -196,8 +196,8 @@
|
|||
regulators {
|
||||
vdd_io_reg: VDD_IO {
|
||||
regulator-name = "VDD_IO";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -215,8 +215,8 @@
|
|||
|
||||
VDD_DDR {
|
||||
regulator-name = "VDD_DDR";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -234,8 +234,8 @@
|
|||
|
||||
VDD_CORE {
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -257,7 +257,6 @@
|
|||
regulator-max-microvolt = <1850000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -272,8 +271,8 @@
|
|||
|
||||
LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
|
|
@ -287,8 +286,8 @@
|
|||
|
||||
LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
|
|
|
|||
|
|
@ -244,8 +244,8 @@
|
|||
regulators {
|
||||
vdd_3v3: VDD_IO {
|
||||
regulator-name = "VDD_IO";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -264,8 +264,8 @@
|
|||
|
||||
vddioddr: VDD_DDR {
|
||||
regulator-name = "VDD_DDR";
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -285,8 +285,8 @@
|
|||
|
||||
vddcore: VDD_CORE {
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-min-microvolt = <1150000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-always-on;
|
||||
|
|
@ -306,7 +306,7 @@
|
|||
vddcpu: VDD_OTHER {
|
||||
regulator-name = "VDD_OTHER";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-initial-mode = <2>;
|
||||
regulator-allowed-modes = <2>, <4>;
|
||||
regulator-ramp-delay = <3125>;
|
||||
|
|
@ -326,8 +326,8 @@
|
|||
|
||||
vldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-standby {
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
|
|
@ -39,6 +40,7 @@
|
|||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
|
@ -46,10 +48,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
|
|
@ -80,23 +82,23 @@
|
|||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
cpu_off = <1>;
|
||||
cpu_on = <2>;
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x4000>;
|
||||
ranges = <0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>;
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -40,10 +40,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
|
|
@ -65,23 +65,23 @@
|
|||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
cpu_off = <1>;
|
||||
cpu_on = <2>;
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x4000>;
|
||||
ranges = <0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>;
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
|
@ -39,10 +40,10 @@
|
|||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -51,16 +51,6 @@
|
|||
vin-supply = <®_3p3v_s5>;
|
||||
};
|
||||
|
||||
reg_3p3v_s0: regulator-3p3v-s0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V_3V3_S0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <®_3p3v_s5>;
|
||||
};
|
||||
|
||||
reg_3p3v_s5: regulator-3p3v-s5 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V_3V3_S5";
|
||||
|
|
@ -259,7 +249,7 @@
|
|||
|
||||
/* default boot source: workaround #1 for errata ERR006282 */
|
||||
smarc_flash: flash@0 {
|
||||
compatible = "winbond,w25q16dw", "jedec,spi-nor";
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
backlight_led: backlight_led {
|
||||
backlight_led: backlight-led {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 5000000 0>;
|
||||
brightness-levels = <0 16 64 255>;
|
||||
|
|
|
|||
|
|
@ -178,12 +178,12 @@
|
|||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp@300000 {
|
||||
spi@300000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x00300000 0x1000>;
|
||||
interrupts-extended = <&impd1_vic 3>;
|
||||
clocks = <&impd1_sspclk>, <&sysclk>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
};
|
||||
|
||||
impd1_gpio0: gpio@400000 {
|
||||
|
|
|
|||
|
|
@ -391,7 +391,7 @@
|
|||
reg = <0x101f4000 0x1000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&xtal24mhz>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
clock-names = "sspclk", "apb_pclk";
|
||||
};
|
||||
|
||||
fpga {
|
||||
|
|
|
|||
|
|
@ -196,7 +196,6 @@ CONFIG_RTC_DRV_AT91SAM9=y
|
|||
CONFIG_DMADEVICES=y
|
||||
CONFIG_AT_HDMAC=y
|
||||
CONFIG_AT_XDMAC=y
|
||||
CONFIG_MICROCHIP_PIT64B=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_IIO=y
|
||||
CONFIG_AT91_ADC=y
|
||||
|
|
|
|||
|
|
@ -188,7 +188,6 @@ CONFIG_RTC_DRV_AT91SAM9=y
|
|||
CONFIG_DMADEVICES=y
|
||||
CONFIG_AT_XDMAC=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_MICROCHIP_PIT64B=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_IIO=y
|
||||
CONFIG_IIO_SW_TRIGGER=y
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static void __init init_irq_stacks(void)
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
static void ____do_softirq(void *arg)
|
||||
{
|
||||
__do_softirq();
|
||||
|
|
|
|||
|
|
@ -541,9 +541,41 @@ extern u32 at91_pm_suspend_in_sram_sz;
|
|||
|
||||
static int at91_suspend_finish(unsigned long val)
|
||||
{
|
||||
unsigned char modified_gray_code[] = {
|
||||
0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
|
||||
0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
|
||||
0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
|
||||
0x10, 0x11,
|
||||
};
|
||||
unsigned int tmp, index;
|
||||
int i;
|
||||
|
||||
if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
|
||||
/*
|
||||
* Bootloader will perform DDR recalibration and will try to
|
||||
* restore the ZQ0SR0 with the value saved here. But the
|
||||
* calibration is buggy and restoring some values from ZQ0SR0
|
||||
* is forbidden and risky thus we need to provide processed
|
||||
* values for these (modified gray code values).
|
||||
*/
|
||||
tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
|
||||
|
||||
/* Store pull-down output impedance select. */
|
||||
index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
|
||||
soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
|
||||
|
||||
/* Store pull-up output impedance select. */
|
||||
index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
|
||||
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
|
||||
|
||||
/* Store pull-down on-die termination impedance select. */
|
||||
index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
|
||||
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
|
||||
|
||||
/* Store pull-up on-die termination impedance select. */
|
||||
index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
|
||||
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
|
||||
|
||||
/*
|
||||
* The 1st 8 words of memory might get corrupted in the process
|
||||
* of DDR PHY recalibration; it is saved here in securam and it
|
||||
|
|
@ -1066,10 +1098,6 @@ static int __init at91_pm_backup_init(void)
|
|||
of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
|
||||
if (!located)
|
||||
goto securam_fail;
|
||||
|
||||
/* DDR3PHY_ZQ0SR0 */
|
||||
soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
|
||||
0x188);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -172,9 +172,15 @@ sr_ena_2:
|
|||
/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
|
||||
cmp r7, #AT91_PM_BACKUP
|
||||
beq sr_ena_3
|
||||
ldr tmp1, [r3, #DDR3PHY_PIR]
|
||||
orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
|
||||
str tmp1, [r3, #DDR3PHY_PIR]
|
||||
|
||||
/* Disable DX DLLs. */
|
||||
ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
|
||||
orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
|
||||
str tmp1, [r3, #DDR3PHY_DX0DLLCR]
|
||||
|
||||
ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
|
||||
orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
|
||||
str tmp1, [r3, #DDR3PHY_DX1DLLCR]
|
||||
|
||||
sr_ena_3:
|
||||
/* Power down DDR PHY data receivers. */
|
||||
|
|
@ -221,10 +227,14 @@ sr_ena_3:
|
|||
bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
|
||||
str tmp1, [r3, #DDR3PHY_DSGCR]
|
||||
|
||||
/* Take DDR PHY's DLL out of bypass mode. */
|
||||
ldr tmp1, [r3, #DDR3PHY_PIR]
|
||||
bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP
|
||||
str tmp1, [r3, #DDR3PHY_PIR]
|
||||
/* Enable DX DLLs. */
|
||||
ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
|
||||
bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
|
||||
str tmp1, [r3, #DDR3PHY_DX0DLLCR]
|
||||
|
||||
ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
|
||||
bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
|
||||
str tmp1, [r3, #DDR3PHY_DX1DLLCR]
|
||||
|
||||
/* Enable quasi-dynamic programming. */
|
||||
mov tmp1, #0
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static void __init ixp4xx_of_map_io(void)
|
|||
}
|
||||
|
||||
/*
|
||||
* We handle 4 differen SoC families. These compatible strings are enough
|
||||
* We handle 4 different SoC families. These compatible strings are enough
|
||||
* to provide the core so that different boards can add their more detailed
|
||||
* specifics.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -917,6 +917,23 @@ config ARM64_ERRATUM_1902691
|
|||
|
||||
If unsure, say Y.
|
||||
|
||||
config ARM64_ERRATUM_2457168
|
||||
bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
|
||||
depends on ARM64_AMU_EXTN
|
||||
default y
|
||||
help
|
||||
This option adds the workaround for ARM Cortex-A510 erratum 2457168.
|
||||
|
||||
The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
|
||||
as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
|
||||
incorrectly giving a significantly higher output value.
|
||||
|
||||
Work around this problem by returning 0 when reading the affected counter in
|
||||
key locations that results in disabling all users of this counter. This effect
|
||||
is the same to firmware disabling affected counters.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
config CAVIUM_ERRATUM_22375
|
||||
bool "Cavium erratum 22375, 24313"
|
||||
default y
|
||||
|
|
@ -1870,6 +1887,8 @@ config ARM64_BTI_KERNEL
|
|||
depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
|
||||
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
|
||||
depends on !CC_IS_GCC || GCC_VERSION >= 100100
|
||||
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
|
||||
depends on !CC_IS_GCC
|
||||
# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
|
||||
depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
|
||||
depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
|
||||
|
|
|
|||
|
|
@ -26,7 +26,8 @@
|
|||
compatible = "arm,mhu", "arm,primecell";
|
||||
reg = <0x0 0x2b1f0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
clocks = <&soc_refclk100mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
|
|
|
|||
|
|
@ -67,7 +67,6 @@
|
|||
port@0 {
|
||||
reg = <0>;
|
||||
csys2_funnel_in_port0: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf0_out_port>;
|
||||
};
|
||||
};
|
||||
|
|
@ -75,7 +74,6 @@
|
|||
port@1 {
|
||||
reg = <1>;
|
||||
csys2_funnel_in_port1: endpoint {
|
||||
slave-mode;
|
||||
remote-endpoint = <&etf1_out_port>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@
|
|||
&enetc_port0 {
|
||||
phy-handle = <&slot1_sgmii>;
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -626,24 +626,28 @@
|
|||
lan1: port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan2: port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan3: port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan4: port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -32,10 +32,10 @@
|
|||
};
|
||||
|
||||
/* Fixed clock dedicated to SPI CAN controller */
|
||||
clk20m: oscillator {
|
||||
clk40m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <20000000>;
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
|
|
@ -202,8 +202,8 @@
|
|||
|
||||
can1: can@0 {
|
||||
compatible = "microchip,mcp251xfd";
|
||||
clocks = <&clk20m>;
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
|
||||
clocks = <&clk40m>;
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_int>;
|
||||
reg = <0>;
|
||||
|
|
@ -603,7 +603,7 @@
|
|||
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
|
||||
reg = <0x4a>;
|
||||
/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
|
||||
reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -745,6 +745,7 @@
|
|||
};
|
||||
|
||||
&usbphynop2 {
|
||||
power-domains = <&pgc_otg2>;
|
||||
vcc-supply = <®_vdd_3v3>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@
|
|||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
|
||||
cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -403,8 +403,8 @@
|
|||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c5>;
|
||||
pinctrl-1 = <&pinctrl_i2c5_gpio>;
|
||||
scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -648,10 +648,10 @@
|
|||
|
||||
pinctrl_ecspi1: dhcom-ecspi1-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
|
||||
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
|
||||
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
|
||||
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
|
||||
MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44
|
||||
MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44
|
||||
MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44
|
||||
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -770,10 +770,10 @@
|
|||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC
|
||||
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00
|
||||
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK
|
||||
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK
|
||||
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
|
||||
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
|
||||
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
|
||||
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -628,7 +628,7 @@
|
|||
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
|
||||
reg = <0x4a>;
|
||||
/* Verdin GPIO_2 (SODIMM 208) */
|
||||
reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -705,7 +705,7 @@
|
|||
pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
|
||||
reg = <0x4a>;
|
||||
/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
|
||||
reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -204,7 +204,6 @@
|
|||
reg = <0x51>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc>;
|
||||
interrupt-names = "irq";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
quartz-load-femtofarads = <7000>;
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@
|
|||
"renesas,rcar-gen4-hscif",
|
||||
"renesas,hscif";
|
||||
reg = <0 0xe6540000 0 96>;
|
||||
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 514>,
|
||||
<&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
|
||||
<&scif_clk>;
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ static __always_inline int icache_is_vpipt(void)
|
|||
|
||||
static inline u32 cache_type_cwg(void)
|
||||
{
|
||||
return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;
|
||||
return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
|
||||
}
|
||||
|
||||
#define __read_mostly __section(".data..read_mostly")
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ struct vl_info {
|
|||
|
||||
#ifdef CONFIG_ARM64_SVE
|
||||
|
||||
extern void sve_alloc(struct task_struct *task);
|
||||
extern void sve_alloc(struct task_struct *task, bool flush);
|
||||
extern void fpsimd_release_task(struct task_struct *task);
|
||||
extern void fpsimd_sync_to_sve(struct task_struct *task);
|
||||
extern void fpsimd_force_sync_to_sve(struct task_struct *task);
|
||||
|
|
@ -256,7 +256,7 @@ size_t sve_state_size(struct task_struct const *task);
|
|||
|
||||
#else /* ! CONFIG_ARM64_SVE */
|
||||
|
||||
static inline void sve_alloc(struct task_struct *task) { }
|
||||
static inline void sve_alloc(struct task_struct *task, bool flush) { }
|
||||
static inline void fpsimd_release_task(struct task_struct *task) { }
|
||||
static inline void sve_sync_to_fpsimd(struct task_struct *task) { }
|
||||
static inline void sve_sync_from_fpsimd_zeropad(struct task_struct *task) { }
|
||||
|
|
|
|||
|
|
@ -64,28 +64,28 @@
|
|||
#define EARLY_KASLR (0)
|
||||
#endif
|
||||
|
||||
#define EARLY_ENTRIES(vstart, vend, shift) \
|
||||
((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1 + EARLY_KASLR)
|
||||
#define EARLY_ENTRIES(vstart, vend, shift, add) \
|
||||
((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1 + add)
|
||||
|
||||
#define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT))
|
||||
#define EARLY_PGDS(vstart, vend, add) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT, add))
|
||||
|
||||
#if SWAPPER_PGTABLE_LEVELS > 3
|
||||
#define EARLY_PUDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PUD_SHIFT))
|
||||
#define EARLY_PUDS(vstart, vend, add) (EARLY_ENTRIES(vstart, vend, PUD_SHIFT, add))
|
||||
#else
|
||||
#define EARLY_PUDS(vstart, vend) (0)
|
||||
#define EARLY_PUDS(vstart, vend, add) (0)
|
||||
#endif
|
||||
|
||||
#if SWAPPER_PGTABLE_LEVELS > 2
|
||||
#define EARLY_PMDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, SWAPPER_TABLE_SHIFT))
|
||||
#define EARLY_PMDS(vstart, vend, add) (EARLY_ENTRIES(vstart, vend, SWAPPER_TABLE_SHIFT, add))
|
||||
#else
|
||||
#define EARLY_PMDS(vstart, vend) (0)
|
||||
#define EARLY_PMDS(vstart, vend, add) (0)
|
||||
#endif
|
||||
|
||||
#define EARLY_PAGES(vstart, vend) ( 1 /* PGDIR page */ \
|
||||
+ EARLY_PGDS((vstart), (vend)) /* each PGDIR needs a next level page table */ \
|
||||
+ EARLY_PUDS((vstart), (vend)) /* each PUD needs a next level page table */ \
|
||||
+ EARLY_PMDS((vstart), (vend))) /* each PMD needs a next level page table */
|
||||
#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end))
|
||||
#define EARLY_PAGES(vstart, vend, add) ( 1 /* PGDIR page */ \
|
||||
+ EARLY_PGDS((vstart), (vend), add) /* each PGDIR needs a next level page table */ \
|
||||
+ EARLY_PUDS((vstart), (vend), add) /* each PUD needs a next level page table */ \
|
||||
+ EARLY_PMDS((vstart), (vend), add)) /* each PMD needs a next level page table */
|
||||
#define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR, _end, EARLY_KASLR))
|
||||
|
||||
/* the initial ID map may need two extra pages if it needs to be extended */
|
||||
#if VA_BITS < 48
|
||||
|
|
@ -93,7 +93,7 @@
|
|||
#else
|
||||
#define INIT_IDMAP_DIR_SIZE (INIT_IDMAP_DIR_PAGES * PAGE_SIZE)
|
||||
#endif
|
||||
#define INIT_IDMAP_DIR_PAGES EARLY_PAGES(KIMAGE_VADDR, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE)
|
||||
#define INIT_IDMAP_DIR_PAGES EARLY_PAGES(KIMAGE_VADDR, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE, 1)
|
||||
|
||||
/* Initial memory map size */
|
||||
#if ARM64_KERNEL_USES_PMD_MAPS
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@
|
|||
#ifndef __ARM64_ASM_SETUP_H
|
||||
#define __ARM64_ASM_SETUP_H
|
||||
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <uapi/asm/setup.h>
|
||||
|
||||
void *get_early_fdt_ptr(void);
|
||||
|
|
@ -14,4 +16,19 @@ void early_fdt_map(u64 dt_phys);
|
|||
extern phys_addr_t __fdt_pointer __initdata;
|
||||
extern u64 __cacheline_aligned boot_args[4];
|
||||
|
||||
static inline bool arch_parse_debug_rodata(char *arg)
|
||||
{
|
||||
extern bool rodata_enabled;
|
||||
extern bool rodata_full;
|
||||
|
||||
if (arg && !strcmp(arg, "full")) {
|
||||
rodata_enabled = true;
|
||||
rodata_full = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
#define arch_parse_debug_rodata arch_parse_debug_rodata
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1116,6 +1116,7 @@
|
|||
|
||||
#else
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/build_bug.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/alternative.h>
|
||||
|
|
@ -1209,8 +1210,6 @@
|
|||
par; \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
#define SYS_FIELD_GET(reg, field, val) \
|
||||
FIELD_GET(reg##_##field##_MASK, val)
|
||||
|
||||
|
|
@ -1220,4 +1219,6 @@
|
|||
#define SYS_FIELD_PREP_ENUM(reg, field, val) \
|
||||
FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SYSREG_H */
|
||||
|
|
|
|||
|
|
@ -45,7 +45,8 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
|
|||
|
||||
int init_cache_level(unsigned int cpu)
|
||||
{
|
||||
unsigned int ctype, level, leaves, fw_level;
|
||||
unsigned int ctype, level, leaves;
|
||||
int fw_level;
|
||||
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
|
||||
|
||||
for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
|
||||
|
|
@ -63,6 +64,9 @@ int init_cache_level(unsigned int cpu)
|
|||
else
|
||||
fw_level = acpi_find_last_cache_level(cpu);
|
||||
|
||||
if (fw_level < 0)
|
||||
return fw_level;
|
||||
|
||||
if (level < fw_level) {
|
||||
/*
|
||||
* some external caches not specified in CLIDR_EL1
|
||||
|
|
|
|||
|
|
@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
|
|||
#ifdef CONFIG_ARM64_ERRATUM_1286807
|
||||
{
|
||||
ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
|
||||
},
|
||||
{
|
||||
/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
|
||||
ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
|
||||
},
|
||||
|
|
@ -654,6 +656,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
|
|||
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_2457168
|
||||
{
|
||||
.desc = "ARM erratum 2457168",
|
||||
.capability = ARM64_WORKAROUND_2457168,
|
||||
.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
|
||||
|
||||
/* Cortex-A510 r0p0-r1p1 */
|
||||
CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_2038923
|
||||
{
|
||||
.desc = "ARM erratum 2038923",
|
||||
|
|
|
|||
|
|
@ -1870,7 +1870,10 @@ static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
|
|||
pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
|
||||
smp_processor_id());
|
||||
cpumask_set_cpu(smp_processor_id(), &amu_cpus);
|
||||
update_freq_counters_refs();
|
||||
|
||||
/* 0 reference values signal broken/disabled counters */
|
||||
if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
|
||||
update_freq_counters_refs();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -502,7 +502,7 @@ tsk .req x28 // current thread_info
|
|||
SYM_CODE_START(vectors)
|
||||
kernel_ventry 1, t, 64, sync // Synchronous EL1t
|
||||
kernel_ventry 1, t, 64, irq // IRQ EL1t
|
||||
kernel_ventry 1, t, 64, fiq // FIQ EL1h
|
||||
kernel_ventry 1, t, 64, fiq // FIQ EL1t
|
||||
kernel_ventry 1, t, 64, error // Error EL1t
|
||||
|
||||
kernel_ventry 1, h, 64, sync // Synchronous EL1h
|
||||
|
|
|
|||
|
|
@ -715,10 +715,12 @@ size_t sve_state_size(struct task_struct const *task)
|
|||
* do_sve_acc() case, there is no ABI requirement to hide stale data
|
||||
* written previously be task.
|
||||
*/
|
||||
void sve_alloc(struct task_struct *task)
|
||||
void sve_alloc(struct task_struct *task, bool flush)
|
||||
{
|
||||
if (task->thread.sve_state) {
|
||||
memset(task->thread.sve_state, 0, sve_state_size(task));
|
||||
if (flush)
|
||||
memset(task->thread.sve_state, 0,
|
||||
sve_state_size(task));
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1388,7 +1390,7 @@ void do_sve_acc(unsigned long esr, struct pt_regs *regs)
|
|||
return;
|
||||
}
|
||||
|
||||
sve_alloc(current);
|
||||
sve_alloc(current, true);
|
||||
if (!current->thread.sve_state) {
|
||||
force_sig(SIGKILL);
|
||||
return;
|
||||
|
|
@ -1439,7 +1441,7 @@ void do_sme_acc(unsigned long esr, struct pt_regs *regs)
|
|||
return;
|
||||
}
|
||||
|
||||
sve_alloc(current);
|
||||
sve_alloc(current, false);
|
||||
sme_alloc(current);
|
||||
if (!current->thread.sve_state || !current->thread.za_state) {
|
||||
force_sig(SIGKILL);
|
||||
|
|
@ -1460,17 +1462,6 @@ void do_sme_acc(unsigned long esr, struct pt_regs *regs)
|
|||
fpsimd_bind_task_to_cpu();
|
||||
}
|
||||
|
||||
/*
|
||||
* If SVE was not already active initialise the SVE registers,
|
||||
* any non-shared state between the streaming and regular SVE
|
||||
* registers is architecturally guaranteed to be zeroed when
|
||||
* we enter streaming mode. We do not need to initialize ZA
|
||||
* since ZA must be disabled at this point and enabling ZA is
|
||||
* architecturally defined to zero ZA.
|
||||
*/
|
||||
if (system_supports_sve() && !test_thread_flag(TIF_SVE))
|
||||
sve_init_regs();
|
||||
|
||||
put_cpu_fpsimd_context();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -371,7 +371,9 @@ SYM_FUNC_END(create_idmap)
|
|||
SYM_FUNC_START_LOCAL(create_kernel_mapping)
|
||||
adrp x0, init_pg_dir
|
||||
mov_q x5, KIMAGE_VADDR // compile time __va(_text)
|
||||
#ifdef CONFIG_RELOCATABLE
|
||||
add x5, x5, x23 // add KASLR displacement
|
||||
#endif
|
||||
adrp x6, _end // runtime __pa(_end)
|
||||
adrp x3, _text // runtime __pa(_text)
|
||||
sub x6, x6, x3 // _end - _text
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ static int prepare_elf_headers(void **addr, unsigned long *sz)
|
|||
u64 i;
|
||||
phys_addr_t start, end;
|
||||
|
||||
nr_ranges = 1; /* for exclusion of crashkernel region */
|
||||
nr_ranges = 2; /* for exclusion of crashkernel region */
|
||||
for_each_mem_range(i, &start, &end)
|
||||
nr_ranges++;
|
||||
|
||||
|
|
|
|||
|
|
@ -94,11 +94,9 @@ asmlinkage u64 kaslr_early_init(void *fdt)
|
|||
|
||||
seed = get_kaslr_seed(fdt);
|
||||
if (!seed) {
|
||||
#ifdef CONFIG_ARCH_RANDOM
|
||||
if (!__early_cpu_has_rndr() ||
|
||||
!__arm64_rndr((unsigned long *)&seed))
|
||||
#endif
|
||||
return 0;
|
||||
if (!__early_cpu_has_rndr() ||
|
||||
!__arm64_rndr((unsigned long *)&seed))
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -882,7 +882,7 @@ static int sve_set_common(struct task_struct *target,
|
|||
* state and ensure there's storage.
|
||||
*/
|
||||
if (target->thread.svcr != old_svcr)
|
||||
sve_alloc(target);
|
||||
sve_alloc(target, true);
|
||||
}
|
||||
|
||||
/* Registers: FPSIMD-only case */
|
||||
|
|
@ -912,7 +912,7 @@ static int sve_set_common(struct task_struct *target,
|
|||
goto out;
|
||||
}
|
||||
|
||||
sve_alloc(target);
|
||||
sve_alloc(target, true);
|
||||
if (!target->thread.sve_state) {
|
||||
ret = -ENOMEM;
|
||||
clear_tsk_thread_flag(target, TIF_SVE);
|
||||
|
|
@ -1082,9 +1082,8 @@ static int za_set(struct task_struct *target,
|
|||
|
||||
/* Ensure there is some SVE storage for streaming mode */
|
||||
if (!target->thread.sve_state) {
|
||||
sve_alloc(target);
|
||||
sve_alloc(target, false);
|
||||
if (!target->thread.sve_state) {
|
||||
clear_thread_flag(TIF_SME);
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
|
@ -1094,7 +1093,6 @@ static int za_set(struct task_struct *target,
|
|||
sme_alloc(target);
|
||||
if (!target->thread.za_state) {
|
||||
ret = -ENOMEM;
|
||||
clear_tsk_thread_flag(target, TIF_SME);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ static size_t sigframe_size(struct rt_sigframe_user_layout const *user)
|
|||
* not taken into account. This limit is not a guarantee and is
|
||||
* NOT ABI.
|
||||
*/
|
||||
#define SIGFRAME_MAXSZ SZ_64K
|
||||
#define SIGFRAME_MAXSZ SZ_256K
|
||||
|
||||
static int __sigframe_alloc(struct rt_sigframe_user_layout *user,
|
||||
unsigned long *offset, size_t size, bool extend)
|
||||
|
|
@ -310,7 +310,7 @@ static int restore_sve_fpsimd_context(struct user_ctxs *user)
|
|||
fpsimd_flush_task_state(current);
|
||||
/* From now, fpsimd_thread_switch() won't touch thread.sve_state */
|
||||
|
||||
sve_alloc(current);
|
||||
sve_alloc(current, true);
|
||||
if (!current->thread.sve_state) {
|
||||
clear_thread_flag(TIF_SVE);
|
||||
return -ENOMEM;
|
||||
|
|
@ -926,6 +926,16 @@ static void setup_return(struct pt_regs *regs, struct k_sigaction *ka,
|
|||
|
||||
/* Signal handlers are invoked with ZA and streaming mode disabled */
|
||||
if (system_supports_sme()) {
|
||||
/*
|
||||
* If we were in streaming mode the saved register
|
||||
* state was SVE but we will exit SM and use the
|
||||
* FPSIMD register state - flush the saved FPSIMD
|
||||
* register state in case it gets loaded.
|
||||
*/
|
||||
if (current->thread.svcr & SVCR_SM_MASK)
|
||||
memset(¤t->thread.uw.fpsimd_state, 0,
|
||||
sizeof(current->thread.uw.fpsimd_state));
|
||||
|
||||
current->thread.svcr &= ~(SVCR_ZA_MASK |
|
||||
SVCR_SM_MASK);
|
||||
sme_smstop();
|
||||
|
|
|
|||
|
|
@ -101,6 +101,9 @@ SYM_FUNC_END(__cpu_suspend_enter)
|
|||
SYM_CODE_START(cpu_resume)
|
||||
bl init_kernel_el
|
||||
bl finalise_el2
|
||||
#if VA_BITS > 48
|
||||
ldr_l x0, vabits_actual
|
||||
#endif
|
||||
bl __cpu_setup
|
||||
/* enable the MMU early - so we can access sleep_save_stash by va */
|
||||
adrp x1, swapper_pg_dir
|
||||
|
|
|
|||
|
|
@ -296,12 +296,25 @@ core_initcall(init_amu_fie);
|
|||
|
||||
static void cpu_read_corecnt(void *val)
|
||||
{
|
||||
/*
|
||||
* A value of 0 can be returned if the current CPU does not support AMUs
|
||||
* or if the counter is disabled for this CPU. A return value of 0 at
|
||||
* counter read is properly handled as an error case by the users of the
|
||||
* counter.
|
||||
*/
|
||||
*(u64 *)val = read_corecnt();
|
||||
}
|
||||
|
||||
static void cpu_read_constcnt(void *val)
|
||||
{
|
||||
*(u64 *)val = read_constcnt();
|
||||
/*
|
||||
* Return 0 if the current CPU is affected by erratum 2457168. A value
|
||||
* of 0 is also returned if the current CPU does not support AMUs or if
|
||||
* the counter is disabled. A return value of 0 at counter read is
|
||||
* properly handled as an error case by the users of the counter.
|
||||
*/
|
||||
*(u64 *)val = this_cpu_has_cap(ARM64_WORKAROUND_2457168) ?
|
||||
0UL : read_constcnt();
|
||||
}
|
||||
|
||||
static inline
|
||||
|
|
@ -328,7 +341,22 @@ int counters_read_on_cpu(int cpu, smp_call_func_t func, u64 *val)
|
|||
*/
|
||||
bool cpc_ffh_supported(void)
|
||||
{
|
||||
return freq_counters_valid(get_cpu_with_amu_feat());
|
||||
int cpu = get_cpu_with_amu_feat();
|
||||
|
||||
/*
|
||||
* FFH is considered supported if there is at least one present CPU that
|
||||
* supports AMUs. Using FFH to read core and reference counters for CPUs
|
||||
* that do not support AMUs, have counters disabled or that are affected
|
||||
* by errata, will result in a return value of 0.
|
||||
*
|
||||
* This is done to allow any enabled and valid counters to be read
|
||||
* through FFH, knowing that potentially returning 0 as counter value is
|
||||
* properly handled by the users of these counters.
|
||||
*/
|
||||
if ((cpu >= nr_cpu_ids) || !cpumask_test_cpu(cpu, cpu_present_mask))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
|
||||
|
|
|
|||
|
|
@ -642,24 +642,6 @@ static void __init map_kernel_segment(pgd_t *pgdp, void *va_start, void *va_end,
|
|||
vm_area_add_early(vma);
|
||||
}
|
||||
|
||||
static int __init parse_rodata(char *arg)
|
||||
{
|
||||
int ret = strtobool(arg, &rodata_enabled);
|
||||
if (!ret) {
|
||||
rodata_full = false;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* permit 'full' in addition to boolean options */
|
||||
if (strcmp(arg, "full"))
|
||||
return -EINVAL;
|
||||
|
||||
rodata_enabled = true;
|
||||
rodata_full = true;
|
||||
return 0;
|
||||
}
|
||||
early_param("rodata", parse_rodata);
|
||||
|
||||
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
|
||||
static int __init map_entry_trampoline(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@ WORKAROUND_1902691
|
|||
WORKAROUND_2038923
|
||||
WORKAROUND_2064142
|
||||
WORKAROUND_2077057
|
||||
WORKAROUND_2457168
|
||||
WORKAROUND_TRBE_OVERWRITE_FILL_MODE
|
||||
WORKAROUND_TSB_FLUSH_FAILURE
|
||||
WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
|
||||
|
|
|
|||
|
|
@ -179,6 +179,21 @@ arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
|
|||
return retval;
|
||||
}
|
||||
|
||||
static __always_inline bool
|
||||
arch_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr)
|
||||
{
|
||||
int retval;
|
||||
|
||||
asm volatile(
|
||||
"{P0 = tstbit(%1,%2); if (P0.new) %0 = #1; if (!P0.new) %0 = #0;}\n"
|
||||
: "=&r" (retval)
|
||||
: "r" (addr[BIT_WORD(nr)]), "r" (nr % BITS_PER_LONG)
|
||||
: "p0", "memory"
|
||||
);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* ffz - find first zero in word.
|
||||
* @word: The word to search
|
||||
|
|
|
|||
|
|
@ -331,11 +331,8 @@ arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
|
|||
return (old & bit) != 0;
|
||||
}
|
||||
|
||||
static __always_inline bool
|
||||
arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
|
||||
{
|
||||
return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
|
||||
}
|
||||
#define arch_test_bit generic_test_bit
|
||||
#define arch_test_bit_acquire generic_test_bit_acquire
|
||||
|
||||
/**
|
||||
* ffz - find the first zero bit in a long word
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ config LOONGARCH
|
|||
select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
|
||||
select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
|
||||
select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
|
||||
select ARCH_KEEP_MEMBLOCK
|
||||
select ARCH_MIGHT_HAVE_PC_PARPORT
|
||||
select ARCH_MIGHT_HAVE_PC_SERIO
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
|
|
@ -51,6 +52,7 @@ config LOONGARCH
|
|||
select ARCH_USE_CMPXCHG_LOCKREF
|
||||
select ARCH_USE_QUEUED_RWLOCKS
|
||||
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
|
||||
select ARCH_WANT_LD_ORPHAN_WARN
|
||||
select ARCH_WANTS_NO_INSTR
|
||||
select BUILDTIME_TABLE_SORT
|
||||
select COMMON_CLK
|
||||
|
|
@ -111,6 +113,7 @@ config LOONGARCH
|
|||
select PCI_ECAM if ACPI
|
||||
select PCI_LOONGSON
|
||||
select PCI_MSI_ARCH_FALLBACKS
|
||||
select PCI_QUIRKS
|
||||
select PERF_USE_VMALLOC
|
||||
select RTC_LIB
|
||||
select SMP
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ extern int acpi_pci_disabled;
|
|||
extern int acpi_noirq;
|
||||
|
||||
#define acpi_os_ioremap acpi_os_ioremap
|
||||
void __init __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
|
||||
void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
|
||||
|
||||
static inline void disable_acpi(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -109,4 +109,20 @@ extern unsigned long vm_map_base;
|
|||
*/
|
||||
#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
|
||||
|
||||
/*
|
||||
* On LoongArch, I/O ports mappring is following:
|
||||
*
|
||||
* | .... |
|
||||
* |-----------------------|
|
||||
* | pci io ports(16K~32M) |
|
||||
* |-----------------------|
|
||||
* | isa io ports(0 ~16K) |
|
||||
* PCI_IOBASE ->|-----------------------|
|
||||
* | .... |
|
||||
*/
|
||||
#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
|
||||
#define PCI_IOSIZE SZ_32M
|
||||
#define ISA_IOSIZE SZ_16K
|
||||
#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
|
||||
|
||||
#endif /* _ASM_ADDRSPACE_H */
|
||||
|
|
|
|||
|
|
@ -5,8 +5,9 @@
|
|||
#ifndef __ASM_CMPXCHG_H
|
||||
#define __ASM_CMPXCHG_H
|
||||
|
||||
#include <asm/barrier.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/build_bug.h>
|
||||
#include <asm/barrier.h>
|
||||
|
||||
#define __xchg_asm(amswap_db, m, val) \
|
||||
({ \
|
||||
|
|
@ -21,10 +22,53 @@
|
|||
__ret; \
|
||||
})
|
||||
|
||||
static inline unsigned int __xchg_small(volatile void *ptr, unsigned int val,
|
||||
unsigned int size)
|
||||
{
|
||||
unsigned int shift;
|
||||
u32 old32, mask, temp;
|
||||
volatile u32 *ptr32;
|
||||
|
||||
/* Mask value to the correct size. */
|
||||
mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
|
||||
val &= mask;
|
||||
|
||||
/*
|
||||
* Calculate a shift & mask that correspond to the value we wish to
|
||||
* exchange within the naturally aligned 4 byte integerthat includes
|
||||
* it.
|
||||
*/
|
||||
shift = (unsigned long)ptr & 0x3;
|
||||
shift *= BITS_PER_BYTE;
|
||||
mask <<= shift;
|
||||
|
||||
/*
|
||||
* Calculate a pointer to the naturally aligned 4 byte integer that
|
||||
* includes our byte of interest, and load its value.
|
||||
*/
|
||||
ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
|
||||
|
||||
asm volatile (
|
||||
"1: ll.w %0, %3 \n"
|
||||
" andn %1, %0, %z4 \n"
|
||||
" or %1, %1, %z5 \n"
|
||||
" sc.w %1, %2 \n"
|
||||
" beqz %1, 1b \n"
|
||||
: "=&r" (old32), "=&r" (temp), "=ZC" (*ptr32)
|
||||
: "ZC" (*ptr32), "Jr" (mask), "Jr" (val << shift)
|
||||
: "memory");
|
||||
|
||||
return (old32 & mask) >> shift;
|
||||
}
|
||||
|
||||
static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
|
||||
int size)
|
||||
{
|
||||
switch (size) {
|
||||
case 1:
|
||||
case 2:
|
||||
return __xchg_small(ptr, x, size);
|
||||
|
||||
case 4:
|
||||
return __xchg_asm("amswap_db.w", (volatile u32 *)ptr, (u32)x);
|
||||
|
||||
|
|
@ -67,10 +111,62 @@ static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
|
|||
__ret; \
|
||||
})
|
||||
|
||||
static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned int old,
|
||||
unsigned int new, unsigned int size)
|
||||
{
|
||||
unsigned int shift;
|
||||
u32 old32, mask, temp;
|
||||
volatile u32 *ptr32;
|
||||
|
||||
/* Mask inputs to the correct size. */
|
||||
mask = GENMASK((size * BITS_PER_BYTE) - 1, 0);
|
||||
old &= mask;
|
||||
new &= mask;
|
||||
|
||||
/*
|
||||
* Calculate a shift & mask that correspond to the value we wish to
|
||||
* compare & exchange within the naturally aligned 4 byte integer
|
||||
* that includes it.
|
||||
*/
|
||||
shift = (unsigned long)ptr & 0x3;
|
||||
shift *= BITS_PER_BYTE;
|
||||
old <<= shift;
|
||||
new <<= shift;
|
||||
mask <<= shift;
|
||||
|
||||
/*
|
||||
* Calculate a pointer to the naturally aligned 4 byte integer that
|
||||
* includes our byte of interest, and load its value.
|
||||
*/
|
||||
ptr32 = (volatile u32 *)((unsigned long)ptr & ~0x3);
|
||||
|
||||
asm volatile (
|
||||
"1: ll.w %0, %3 \n"
|
||||
" and %1, %0, %z4 \n"
|
||||
" bne %1, %z5, 2f \n"
|
||||
" andn %1, %0, %z4 \n"
|
||||
" or %1, %1, %z6 \n"
|
||||
" sc.w %1, %2 \n"
|
||||
" beqz %1, 1b \n"
|
||||
" b 3f \n"
|
||||
"2: \n"
|
||||
__WEAK_LLSC_MB
|
||||
"3: \n"
|
||||
: "=&r" (old32), "=&r" (temp), "=ZC" (*ptr32)
|
||||
: "ZC" (*ptr32), "Jr" (mask), "Jr" (old), "Jr" (new)
|
||||
: "memory");
|
||||
|
||||
return (old32 & mask) >> shift;
|
||||
}
|
||||
|
||||
static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
|
||||
unsigned long new, unsigned int size)
|
||||
{
|
||||
switch (size) {
|
||||
case 1:
|
||||
case 2:
|
||||
return __cmpxchg_small(ptr, old, new, size);
|
||||
|
||||
case 4:
|
||||
return __cmpxchg_asm("ll.w", "sc.w", (volatile u32 *)ptr,
|
||||
(u32)old, new);
|
||||
|
|
|
|||
|
|
@ -7,34 +7,15 @@
|
|||
|
||||
#define ARCH_HAS_IOREMAP_WC
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bug.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable-bits.h>
|
||||
#include <asm/string.h>
|
||||
|
||||
/*
|
||||
* On LoongArch, I/O ports mappring is following:
|
||||
*
|
||||
* | .... |
|
||||
* |-----------------------|
|
||||
* | pci io ports(64K~32M) |
|
||||
* |-----------------------|
|
||||
* | isa io ports(0 ~16K) |
|
||||
* PCI_IOBASE ->|-----------------------|
|
||||
* | .... |
|
||||
*/
|
||||
#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
|
||||
#define PCI_IOSIZE SZ_32M
|
||||
#define ISA_IOSIZE SZ_16K
|
||||
#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
|
||||
|
||||
/*
|
||||
* Change "struct page" to physical address.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ static inline int pfn_valid(unsigned long pfn)
|
|||
|
||||
#endif
|
||||
|
||||
#define virt_to_pfn(kaddr) PFN_DOWN(virt_to_phys((void *)(kaddr)))
|
||||
#define virt_to_pfn(kaddr) PFN_DOWN(PHYSADDR(kaddr))
|
||||
#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
|
||||
|
||||
extern int __virt_addr_valid(volatile void *kaddr);
|
||||
|
|
|
|||
|
|
@ -123,6 +123,10 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
|
|||
int size)
|
||||
{
|
||||
switch (size) {
|
||||
case 1:
|
||||
case 2:
|
||||
return __xchg_small((volatile void *)ptr, val, size);
|
||||
|
||||
case 4:
|
||||
return __xchg_asm("amswap.w", (volatile u32 *)ptr, (u32)val);
|
||||
|
||||
|
|
@ -204,9 +208,13 @@ do { \
|
|||
#define this_cpu_write_4(pcp, val) _percpu_write(pcp, val)
|
||||
#define this_cpu_write_8(pcp, val) _percpu_write(pcp, val)
|
||||
|
||||
#define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val)
|
||||
#define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val)
|
||||
#define this_cpu_xchg_4(pcp, val) _percpu_xchg(pcp, val)
|
||||
#define this_cpu_xchg_8(pcp, val) _percpu_xchg(pcp, val)
|
||||
|
||||
#define this_cpu_cmpxchg_1(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
|
||||
#define this_cpu_cmpxchg_2(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
|
||||
#define this_cpu_cmpxchg_4(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
|
||||
#define this_cpu_cmpxchg_8(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
|
||||
|
||||
|
|
|
|||
|
|
@ -59,7 +59,6 @@
|
|||
#include <linux/mm_types.h>
|
||||
#include <linux/mmzone.h>
|
||||
#include <asm/fixmap.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
struct mm_struct;
|
||||
struct vm_area_struct;
|
||||
|
|
@ -145,7 +144,7 @@ static inline void set_p4d(p4d_t *p4d, p4d_t p4dval)
|
|||
*p4d = p4dval;
|
||||
}
|
||||
|
||||
#define p4d_phys(p4d) virt_to_phys((void *)p4d_val(p4d))
|
||||
#define p4d_phys(p4d) PHYSADDR(p4d_val(p4d))
|
||||
#define p4d_page(p4d) (pfn_to_page(p4d_phys(p4d) >> PAGE_SHIFT))
|
||||
|
||||
#endif
|
||||
|
|
@ -188,7 +187,7 @@ static inline pmd_t *pud_pgtable(pud_t pud)
|
|||
|
||||
#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while (0)
|
||||
|
||||
#define pud_phys(pud) virt_to_phys((void *)pud_val(pud))
|
||||
#define pud_phys(pud) PHYSADDR(pud_val(pud))
|
||||
#define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
|
||||
|
||||
#endif
|
||||
|
|
@ -221,7 +220,7 @@ static inline void pmd_clear(pmd_t *pmdp)
|
|||
|
||||
#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while (0)
|
||||
|
||||
#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
|
||||
#define pmd_phys(pmd) PHYSADDR(pmd_val(pmd))
|
||||
|
||||
#ifndef CONFIG_TRANSPARENT_HUGEPAGE
|
||||
#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
|
||||
|
|
|
|||
|
|
@ -1,10 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#ifndef _ASM_REBOOT_H
|
||||
#define _ASM_REBOOT_H
|
||||
|
||||
extern void (*pm_restart)(void);
|
||||
|
||||
#endif /* _ASM_REBOOT_H */
|
||||
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Reference in New Issue