mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-08-21 00:10:09 +00:00
Code Issues Releases Wiki Activity

staging: mt7621-spi: change mt7621_spi_wait_till_ready to take struct mt7621_spi

Browse source 
All callers have a 'struct mt7621_spi' and that is all
mt7621_spi_wait_till_ready() needs.  So just pass it
instead of the spi_device.

Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
NeilBrown 2018-06-07 08:04:21 +10:00 committed by Greg Kroah-Hartman
parent c0f784ba92
commit a83834c1c9
1 changed files with 5 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/staging/mt7621-spi/spi-mt7621.c
View file

@ -155,9 +155,8 @@ static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
return 0;
}
static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
{
struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
int i;
for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
@ -187,7 +186,7 @@ static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
u32 data[9] = { 0 };
u32 val;
mt7621_spi_wait_till_ready(spi);
mt7621_spi_wait_till_ready(rs);
list_for_each_entry(t, &m->transfers, transfer_list) {
const u8 *buf = t->tx_buf;
@ -238,7 +237,7 @@ static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
val |= SPI_CTL_START;
mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
mt7621_spi_wait_till_ready(spi);
mt7621_spi_wait_till_ready(rs);
mt7621_spi_set_cs(spi, 0);
@ -278,7 +277,7 @@ static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
u32 data[9] = { 0 };
u32 val = 0;
mt7621_spi_wait_till_ready(spi);
mt7621_spi_wait_till_ready(rs);
list_for_each_entry(t, &m->transfers, transfer_list) {
const u8 *buf = t->tx_buf;
@ -323,7 +322,7 @@ static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
val |= SPI_CTL_START;
mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
mt7621_spi_wait_till_ready(spi);
mt7621_spi_wait_till_ready(rs);
mt7621_spi_set_cs(spi, 0);