mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
Merge commit 'v3.1' into spi/next
This commit is contained in:
commit
a853ba8d6d
556 changed files with 4740 additions and 3603 deletions
13
Documentation/ABI/testing/sysfs-class-scsi_host
Normal file
13
Documentation/ABI/testing/sysfs-class-scsi_host
Normal file
|
@ -0,0 +1,13 @@
|
|||
What: /sys/class/scsi_host/hostX/isci_id
|
||||
Date: June 2011
|
||||
Contact: Dave Jiang <dave.jiang@intel.com>
|
||||
Description:
|
||||
This file contains the enumerated host ID for the Intel
|
||||
SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
|
||||
Storage Control Unit embeds up to two 4-port controllers in
|
||||
a single PCI device. The controllers are enumerated in order
|
||||
which usually means the lowest number scsi_host corresponds
|
||||
with the first controller, but this association is not
|
||||
guaranteed. The 'isci_id' attribute unambiguously identifies
|
||||
the controller index: '0' for the first controller,
|
||||
'1' for the second.
|
|
@ -380,7 +380,7 @@ will be charged as a new owner of it.
|
|||
|
||||
5.2 stat file
|
||||
|
||||
5.2.1 memory.stat file includes following statistics
|
||||
memory.stat file includes following statistics
|
||||
|
||||
# per-memory cgroup local status
|
||||
cache - # of bytes of page cache memory.
|
||||
|
@ -438,89 +438,6 @@ Note:
|
|||
file_mapped is accounted only when the memory cgroup is owner of page
|
||||
cache.)
|
||||
|
||||
5.2.2 memory.vmscan_stat
|
||||
|
||||
memory.vmscan_stat includes statistics information for memory scanning and
|
||||
freeing, reclaiming. The statistics shows memory scanning information since
|
||||
memory cgroup creation and can be reset to 0 by writing 0 as
|
||||
|
||||
#echo 0 > ../memory.vmscan_stat
|
||||
|
||||
This file contains following statistics.
|
||||
|
||||
[param]_[file_or_anon]_pages_by_[reason]_[under_heararchy]
|
||||
[param]_elapsed_ns_by_[reason]_[under_hierarchy]
|
||||
|
||||
For example,
|
||||
|
||||
scanned_file_pages_by_limit indicates the number of scanned
|
||||
file pages at vmscan.
|
||||
|
||||
Now, 3 parameters are supported
|
||||
|
||||
scanned - the number of pages scanned by vmscan
|
||||
rotated - the number of pages activated at vmscan
|
||||
freed - the number of pages freed by vmscan
|
||||
|
||||
If "rotated" is high against scanned/freed, the memcg seems busy.
|
||||
|
||||
Now, 2 reason are supported
|
||||
|
||||
limit - the memory cgroup's limit
|
||||
system - global memory pressure + softlimit
|
||||
(global memory pressure not under softlimit is not handled now)
|
||||
|
||||
When under_hierarchy is added in the tail, the number indicates the
|
||||
total memcg scan of its children and itself.
|
||||
|
||||
elapsed_ns is a elapsed time in nanosecond. This may include sleep time
|
||||
and not indicates CPU usage. So, please take this as just showing
|
||||
latency.
|
||||
|
||||
Here is an example.
|
||||
|
||||
# cat /cgroup/memory/A/memory.vmscan_stat
|
||||
scanned_pages_by_limit 9471864
|
||||
scanned_anon_pages_by_limit 6640629
|
||||
scanned_file_pages_by_limit 2831235
|
||||
rotated_pages_by_limit 4243974
|
||||
rotated_anon_pages_by_limit 3971968
|
||||
rotated_file_pages_by_limit 272006
|
||||
freed_pages_by_limit 2318492
|
||||
freed_anon_pages_by_limit 962052
|
||||
freed_file_pages_by_limit 1356440
|
||||
elapsed_ns_by_limit 351386416101
|
||||
scanned_pages_by_system 0
|
||||
scanned_anon_pages_by_system 0
|
||||
scanned_file_pages_by_system 0
|
||||
rotated_pages_by_system 0
|
||||
rotated_anon_pages_by_system 0
|
||||
rotated_file_pages_by_system 0
|
||||
freed_pages_by_system 0
|
||||
freed_anon_pages_by_system 0
|
||||
freed_file_pages_by_system 0
|
||||
elapsed_ns_by_system 0
|
||||
scanned_pages_by_limit_under_hierarchy 9471864
|
||||
scanned_anon_pages_by_limit_under_hierarchy 6640629
|
||||
scanned_file_pages_by_limit_under_hierarchy 2831235
|
||||
rotated_pages_by_limit_under_hierarchy 4243974
|
||||
rotated_anon_pages_by_limit_under_hierarchy 3971968
|
||||
rotated_file_pages_by_limit_under_hierarchy 272006
|
||||
freed_pages_by_limit_under_hierarchy 2318492
|
||||
freed_anon_pages_by_limit_under_hierarchy 962052
|
||||
freed_file_pages_by_limit_under_hierarchy 1356440
|
||||
elapsed_ns_by_limit_under_hierarchy 351386416101
|
||||
scanned_pages_by_system_under_hierarchy 0
|
||||
scanned_anon_pages_by_system_under_hierarchy 0
|
||||
scanned_file_pages_by_system_under_hierarchy 0
|
||||
rotated_pages_by_system_under_hierarchy 0
|
||||
rotated_anon_pages_by_system_under_hierarchy 0
|
||||
rotated_file_pages_by_system_under_hierarchy 0
|
||||
freed_pages_by_system_under_hierarchy 0
|
||||
freed_anon_pages_by_system_under_hierarchy 0
|
||||
freed_file_pages_by_system_under_hierarchy 0
|
||||
elapsed_ns_by_system_under_hierarchy 0
|
||||
|
||||
5.3 swappiness
|
||||
|
||||
Similar to /proc/sys/vm/swappiness, but affecting a hierarchy of groups only.
|
||||
|
|
|
@ -35,13 +35,6 @@ the Out-Of-Spec bit. Following table summarizes the exported sysfs files:
|
|||
All Sysfs entries are named with their core_id (represented here by 'X').
|
||||
tempX_input - Core temperature (in millidegrees Celsius).
|
||||
tempX_max - All cooling devices should be turned on (on Core2).
|
||||
Initialized with IA32_THERM_INTERRUPT. When the CPU
|
||||
temperature reaches this temperature, an interrupt is
|
||||
generated and tempX_max_alarm is set.
|
||||
tempX_max_hyst - If the CPU temperature falls below than temperature,
|
||||
an interrupt is generated and tempX_max_alarm is reset.
|
||||
tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max.
|
||||
Reset if the temperature drops to or below tempX_max_hyst.
|
||||
tempX_crit - Maximum junction temperature (in millidegrees Celsius).
|
||||
tempX_crit_alarm - Set when Out-of-spec bit is set, never clears.
|
||||
Correct CPU operation is no longer guaranteed.
|
||||
|
@ -49,9 +42,10 @@ tempX_label - Contains string "Core X", where X is processor
|
|||
number. For Package temp, this will be "Physical id Y",
|
||||
where Y is the package number.
|
||||
|
||||
The TjMax temperature is set to 85 degrees C if undocumented model specific
|
||||
register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as
|
||||
(sometimes) documented in processor datasheet.
|
||||
On CPU models which support it, TjMax is read from a model-specific register.
|
||||
On other models, it is set to an arbitrary value based on weak heuristics.
|
||||
If these heuristics don't work for you, you can pass the correct TjMax value
|
||||
as a module parameter (tjmax).
|
||||
|
||||
Appendix A. Known TjMax lists (TBD):
|
||||
Some information comes from ark.intel.com
|
||||
|
|
|
@ -2086,9 +2086,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
Override pmtimer IOPort with a hex value.
|
||||
e.g. pmtmr=0x508
|
||||
|
||||
pnp.debug [PNP]
|
||||
Enable PNP debug messages. This depends on the
|
||||
CONFIG_PNP_DEBUG_MESSAGES option.
|
||||
pnp.debug=1 [PNP]
|
||||
Enable PNP debug messages (depends on the
|
||||
CONFIG_PNP_DEBUG_MESSAGES option). Change at run-time
|
||||
via /sys/module/pnp/parameters/debug. We always show
|
||||
current resource usage; turning this on also shows
|
||||
possible settings and some assignment information.
|
||||
|
||||
pnpacpi= [ACPI]
|
||||
{ off }
|
||||
|
@ -2703,10 +2706,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
functions are at fixed addresses, they make nice
|
||||
targets for exploits that can control RIP.
|
||||
|
||||
emulate [default] Vsyscalls turn into traps and are
|
||||
emulated reasonably safely.
|
||||
emulate Vsyscalls turn into traps and are emulated
|
||||
reasonably safely.
|
||||
|
||||
native Vsyscalls are native syscall instructions.
|
||||
native [default] Vsyscalls are native syscall
|
||||
instructions.
|
||||
This is a little bit faster than trapping
|
||||
and makes a few dynamic recompilers work
|
||||
better than they would in emulation mode.
|
||||
|
|
|
@ -1,3 +1,5 @@
|
|||
Note: This driver doesn't have a maintainer.
|
||||
|
||||
Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux.
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
|
@ -55,7 +57,6 @@ Test and make sure PCI latency is now correct for all cases.
|
|||
Authors:
|
||||
|
||||
Sten Wang <sten_wang@davicom.com.tw > : Original Author
|
||||
Tobias Ringstrom <tori@unhappy.mine.nu> : Current Maintainer
|
||||
|
||||
Contributors:
|
||||
|
||||
|
|
|
@ -1042,7 +1042,7 @@ conf/interface/*:
|
|||
The functional behaviour for certain settings is different
|
||||
depending on whether local forwarding is enabled or not.
|
||||
|
||||
accept_ra - BOOLEAN
|
||||
accept_ra - INTEGER
|
||||
Accept Router Advertisements; autoconfigure using them.
|
||||
|
||||
Possible values are:
|
||||
|
@ -1106,7 +1106,7 @@ dad_transmits - INTEGER
|
|||
The amount of Duplicate Address Detection probes to send.
|
||||
Default: 1
|
||||
|
||||
forwarding - BOOLEAN
|
||||
forwarding - INTEGER
|
||||
Configure interface-specific Host/Router behaviour.
|
||||
|
||||
Note: It is recommended to have the same setting on all
|
||||
|
|
|
@ -27,7 +27,7 @@ applying a filter to each packet that assigns it to one of a small number
|
|||
of logical flows. Packets for each flow are steered to a separate receive
|
||||
queue, which in turn can be processed by separate CPUs. This mechanism is
|
||||
generally known as “Receive-side Scaling” (RSS). The goal of RSS and
|
||||
the other scaling techniques to increase performance uniformly.
|
||||
the other scaling techniques is to increase performance uniformly.
|
||||
Multi-queue distribution can also be used for traffic prioritization, but
|
||||
that is not the focus of these techniques.
|
||||
|
||||
|
@ -186,10 +186,10 @@ are steered using plain RPS. Multiple table entries may point to the
|
|||
same CPU. Indeed, with many flows and few CPUs, it is very likely that
|
||||
a single application thread handles flows with many different flow hashes.
|
||||
|
||||
rps_sock_table is a global flow table that contains the *desired* CPU for
|
||||
flows: the CPU that is currently processing the flow in userspace. Each
|
||||
table value is a CPU index that is updated during calls to recvmsg and
|
||||
sendmsg (specifically, inet_recvmsg(), inet_sendmsg(), inet_sendpage()
|
||||
rps_sock_flow_table is a global flow table that contains the *desired* CPU
|
||||
for flows: the CPU that is currently processing the flow in userspace.
|
||||
Each table value is a CPU index that is updated during calls to recvmsg
|
||||
and sendmsg (specifically, inet_recvmsg(), inet_sendmsg(), inet_sendpage()
|
||||
and tcp_splice_read()).
|
||||
|
||||
When the scheduler moves a thread to a new CPU while it has outstanding
|
||||
|
@ -243,7 +243,7 @@ configured. The number of entries in the global flow table is set through:
|
|||
|
||||
The number of entries in the per-queue flow table are set through:
|
||||
|
||||
/sys/class/net/<dev>/queues/tx-<n>/rps_flow_cnt
|
||||
/sys/class/net/<dev>/queues/rx-<n>/rps_flow_cnt
|
||||
|
||||
== Suggested Configuration
|
||||
|
||||
|
|
|
@ -123,10 +123,11 @@ be automatically shutdown if it's set to "never".
|
|||
khugepaged runs usually at low frequency so while one may not want to
|
||||
invoke defrag algorithms synchronously during the page faults, it
|
||||
should be worth invoking defrag at least in khugepaged. However it's
|
||||
also possible to disable defrag in khugepaged:
|
||||
also possible to disable defrag in khugepaged by writing 0 or enable
|
||||
defrag in khugepaged by writing 1:
|
||||
|
||||
echo yes >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo no >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo 0 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo 1 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
|
||||
You can also control how many pages khugepaged should scan at each
|
||||
pass:
|
||||
|
|
32
MAINTAINERS
32
MAINTAINERS
|
@ -1278,7 +1278,6 @@ F: drivers/input/misc/ati_remote2.c
|
|||
ATLX ETHERNET DRIVERS
|
||||
M: Jay Cliburn <jcliburn@gmail.com>
|
||||
M: Chris Snook <chris.snook@gmail.com>
|
||||
M: Jie Yang <jie.yang@atheros.com>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://sourceforge.net/projects/atl1
|
||||
W: http://atl1.sourceforge.net
|
||||
|
@ -1574,7 +1573,6 @@ F: drivers/scsi/bfa/
|
|||
|
||||
BROCADE BNA 10 GIGABIT ETHERNET DRIVER
|
||||
M: Rasesh Mody <rmody@brocade.com>
|
||||
M: Debashis Dutt <ddutt@brocade.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/net/bna/
|
||||
|
@ -1758,7 +1756,6 @@ F: Documentation/zh_CN/
|
|||
|
||||
CISCO VIC ETHERNET NIC DRIVER
|
||||
M: Christian Benvenuti <benve@cisco.com>
|
||||
M: Vasanthy Kolluri <vkolluri@cisco.com>
|
||||
M: Roopa Prabhu <roprabhu@cisco.com>
|
||||
M: David Wang <dwang2@cisco.com>
|
||||
S: Supported
|
||||
|
@ -2463,7 +2460,7 @@ S: Supported
|
|||
F: drivers/infiniband/hw/ehca/
|
||||
|
||||
EHEA (IBM pSeries eHEA 10Gb ethernet adapter) DRIVER
|
||||
M: Breno Leitao <leitao@linux.vnet.ibm.com>
|
||||
M: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ehea/
|
||||
|
@ -3262,6 +3259,17 @@ F: Documentation/input/multi-touch-protocol.txt
|
|||
F: drivers/input/input-mt.c
|
||||
K: \b(ABS|SYN)_MT_
|
||||
|
||||
INTEL C600 SERIES SAS CONTROLLER DRIVER
|
||||
M: Intel SCU Linux support <intel-linux-scu@intel.com>
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
M: Ed Nadolski <edmund.nadolski@intel.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git
|
||||
S: Maintained
|
||||
F: drivers/scsi/isci/
|
||||
F: firmware/isci/
|
||||
|
||||
INTEL IDLE DRIVER
|
||||
M: Len Brown <lenb@kernel.org>
|
||||
L: linux-pm@lists.linux-foundation.org
|
||||
|
@ -3305,7 +3313,7 @@ M: David Woodhouse <dwmw2@infradead.org>
|
|||
L: iommu@lists.linux-foundation.org
|
||||
T: git git://git.infradead.org/iommu-2.6.git
|
||||
S: Supported
|
||||
F: drivers/pci/intel-iommu.c
|
||||
F: drivers/iommu/intel-iommu.c
|
||||
F: include/linux/intel-iommu.h
|
||||
|
||||
INTEL IOP-ADMA DMA DRIVER
|
||||
|
@ -4404,7 +4412,8 @@ L: netfilter@vger.kernel.org
|
|||
L: coreteam@netfilter.org
|
||||
W: http://www.netfilter.org/
|
||||
W: http://www.iptables.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next-2.6.git
|
||||
S: Supported
|
||||
F: include/linux/netfilter*
|
||||
F: include/linux/netfilter/
|
||||
|
@ -4774,7 +4783,7 @@ F: drivers/net/wireless/orinoco/
|
|||
|
||||
OSD LIBRARY and FILESYSTEM
|
||||
M: Boaz Harrosh <bharrosh@panasas.com>
|
||||
M: Benny Halevy <bhalevy@panasas.com>
|
||||
M: Benny Halevy <bhalevy@tonian.com>
|
||||
L: osd-dev@open-osd.org
|
||||
W: http://open-osd.org
|
||||
T: git git://git.open-osd.org/open-osd.git
|
||||
|
@ -6357,15 +6366,14 @@ F: net/ipv4/tcp_lp.c
|
|||
|
||||
TEGRA SUPPORT
|
||||
M: Colin Cross <ccross@android.com>
|
||||
M: Erik Gilling <konkers@android.com>
|
||||
M: Olof Johansson <olof@lixom.net>
|
||||
M: Stephen Warren <swarren@nvidia.com>
|
||||
L: linux-tegra@vger.kernel.org
|
||||
T: git git://android.git.kernel.org/kernel/tegra.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
|
||||
S: Supported
|
||||
F: arch/arm/mach-tegra
|
||||
|
||||
TEHUTI ETHERNET DRIVER
|
||||
M: Alexander Indenbaum <baum@tehutinetworks.net>
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
|
@ -7200,6 +7208,9 @@ W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
|
|||
S: Supported
|
||||
F: Documentation/hwmon/wm83??
|
||||
F: drivers/leds/leds-wm83*.c
|
||||
F: drivers/input/misc/wm831x-on.c
|
||||
F: drivers/input/touchscreen/wm831x-ts.c
|
||||
F: drivers/input/touchscreen/wm97*.c
|
||||
F: drivers/mfd/wm8*.c
|
||||
F: drivers/power/wm83*.c
|
||||
F: drivers/rtc/rtc-wm83*.c
|
||||
|
@ -7209,6 +7220,7 @@ F: drivers/watchdog/wm83*_wdt.c
|
|||
F: include/linux/mfd/wm831x/
|
||||
F: include/linux/mfd/wm8350/
|
||||
F: include/linux/mfd/wm8400*
|
||||
F: include/linux/wm97xx.h
|
||||
F: include/sound/wm????.h
|
||||
F: sound/soc/codecs/wm*
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION =
|
||||
NAME = "Divemaster Edition"
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -51,7 +51,7 @@ config GENERIC_CMOS_UPDATE
|
|||
def_bool y
|
||||
|
||||
config GENERIC_GPIO
|
||||
def_bool y
|
||||
bool
|
||||
|
||||
config ZONE_DMA
|
||||
bool
|
||||
|
|
|
@ -1283,6 +1283,20 @@ config ARM_ERRATA_364296
|
|||
processor into full low interrupt latency mode. ARM11MPCore
|
||||
is not affected.
|
||||
|
||||
config ARM_ERRATA_764369
|
||||
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
|
||||
depends on CPU_V7 && SMP
|
||||
help
|
||||
This option enables the workaround for erratum 764369
|
||||
affecting Cortex-A9 MPCore with two or more processors (all
|
||||
current revisions). Under certain timing circumstances, a data
|
||||
cache line maintenance operation by MVA targeting an Inner
|
||||
Shareable memory region may fail to proceed up to either the
|
||||
Point of Coherency or to the Point of Unification of the
|
||||
system. This workaround adds a DSB instruction before the
|
||||
relevant cache maintenance functions and sets a specific bit
|
||||
in the diagnostic control register of the SCU.
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/arm/common/Kconfig"
|
||||
|
|
|
@ -57,14 +57,14 @@ serial@70006300 {
|
|||
};
|
||||
|
||||
sdhci@c8000200 {
|
||||
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
|
||||
<&gpio 57 0>, /* wp, gpio PH1 */
|
||||
<&gpio 155 0>; /* power, gpio PT3 */
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
gpios = <&gpio 58 0>, /* cd, gpio PH2 */
|
||||
<&gpio 59 0>, /* wp, gpio PH3 */
|
||||
<&gpio 70 0>; /* power, gpio PI6 */
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -21,8 +21,8 @@ serial@70006300 {
|
|||
};
|
||||
|
||||
sdhci@c8000400 {
|
||||
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
|
||||
<&gpio 57 0>, /* wp, gpio PH1 */
|
||||
<&gpio 70 0>; /* power, gpio PI6 */
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base)
|
|||
writel(0, base + VIC_INT_SELECT);
|
||||
writel(0, base + VIC_INT_ENABLE);
|
||||
writel(~0, base + VIC_INT_ENABLE_CLEAR);
|
||||
writel(0, base + VIC_IRQ_STATUS);
|
||||
writel(0, base + VIC_ITCR);
|
||||
writel(~0, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
|
|
@ -25,17 +25,17 @@
|
|||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldrex %1, [%2]\n" \
|
||||
"1: ldrex %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: strex %1, %0, [%2]\n" \
|
||||
" teq %1, #0\n" \
|
||||
"2: strex %2, %0, [%3]\n" \
|
||||
" teq %2, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%4") \
|
||||
: "=&r" (ret), "=&r" (oldval) \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
|
||||
|
@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
#include <linux/preempt.h>
|
||||
#include <asm/domain.h>
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(ldr) " %1, [%2]\n" \
|
||||
"1: " T(ldr) " %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: " T(str) " %0, [%2]\n" \
|
||||
"2: " T(str) " %0, [%3]\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%4") \
|
||||
: "=&r" (ret), "=&r" (oldval) \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
|
||||
|
@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
|||
int cmp = (encoded_op >> 24) & 15;
|
||||
int oparg = (encoded_op << 8) >> 20;
|
||||
int cmparg = (encoded_op << 20) >> 20;
|
||||
int oldval = 0, ret;
|
||||
int oldval = 0, ret, tmp;
|
||||
|
||||
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
|
||||
oparg = 1 << oparg;
|
||||
|
@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
|||
|
||||
switch (op) {
|
||||
case FUTEX_OP_SET:
|
||||
__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_ADD:
|
||||
__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_OR:
|
||||
__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_ANDN:
|
||||
__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
|
||||
__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
|
||||
break;
|
||||
case FUTEX_OP_XOR:
|
||||
__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
default:
|
||||
ret = -ENOSYS;
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
#ifndef __ASM_ARM_LOCALTIMER_H
|
||||
#define __ASM_ARM_LOCALTIMER_H
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
struct clock_event_device;
|
||||
|
||||
/*
|
||||
|
|
|
@ -478,8 +478,8 @@
|
|||
/*
|
||||
* Unimplemented (or alternatively implemented) syscalls
|
||||
*/
|
||||
#define __IGNORE_fadvise64_64 1
|
||||
#define __IGNORE_migrate_pages 1
|
||||
#define __IGNORE_fadvise64_64
|
||||
#define __IGNORE_migrate_pages
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_ARM_UNISTD_H */
|
||||
|
|
|
@ -321,8 +321,8 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
|
|||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] =
|
||||
ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#define SCU_CTRL 0x00
|
||||
#define SCU_CONFIG 0x04
|
||||
|
@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
|
|||
{
|
||||
u32 scu_ctrl;
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
/* Cortex-A9 only */
|
||||
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
|
||||
scu_ctrl = __raw_readl(scu_base + 0x30);
|
||||
if (!(scu_ctrl & 1))
|
||||
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
|
||||
}
|
||||
#endif
|
||||
|
||||
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
|
||||
/* already enabled? */
|
||||
if (scu_ctrl & 1)
|
||||
|
|
|
@ -23,8 +23,10 @@
|
|||
|
||||
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
|
||||
#define ARM_EXIT_KEEP(x) x
|
||||
#define ARM_EXIT_DISCARD(x)
|
||||
#else
|
||||
#define ARM_EXIT_KEEP(x)
|
||||
#define ARM_EXIT_DISCARD(x) x
|
||||
#endif
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
|
@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
|
|||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* XXX: The linker does not define how output sections are
|
||||
* assigned to input sections when there are multiple statements
|
||||
* matching the same input section name. There is no documented
|
||||
* order of matching.
|
||||
*
|
||||
* unwind exit sections must be discarded before the rest of the
|
||||
* unwind sections get included.
|
||||
*/
|
||||
|
@ -47,6 +54,9 @@ SECTIONS
|
|||
*(.ARM.extab.exit.text)
|
||||
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
|
||||
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
|
||||
ARM_EXIT_DISCARD(EXIT_TEXT)
|
||||
ARM_EXIT_DISCARD(EXIT_DATA)
|
||||
EXIT_CALL
|
||||
#ifndef CONFIG_HOTPLUG
|
||||
*(.ARM.exidx.devexit.text)
|
||||
*(.ARM.extab.devexit.text)
|
||||
|
@ -58,6 +68,8 @@ SECTIONS
|
|||
#ifndef CONFIG_SMP_ON_UP
|
||||
*(.alt.smp.init)
|
||||
#endif
|
||||
*(.discard)
|
||||
*(.discard.*)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
|
@ -279,9 +291,6 @@ SECTIONS
|
|||
|
||||
STABS_DEBUG
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* Default discards */
|
||||
DISCARDS
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
|
|||
|
||||
void __init dove_spi1_init(void)
|
||||
{
|
||||
orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
|
|
@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "exynos4-fimc.0",
|
||||
.name = "sclk_cam0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
|
@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "exynos4-fimc.1",
|
||||
.name = "sclk_cam1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
|
@ -1160,7 +1158,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
|
|||
|
||||
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
||||
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650);
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650c);
|
||||
|
||||
clk_fout_apll.ops = &exynos4_fout_apll_ops;
|
||||
clk_fout_mpll.rate = mpll;
|
||||
|
|
|
@ -132,12 +132,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
|
|||
return ((cycle_t)hi << 32) | lo;
|
||||
}
|
||||
|
||||
static void exynos4_frc_resume(struct clocksource *cs)
|
||||
{
|
||||
exynos4_mct_frc_start(0, 0);
|
||||
}
|
||||
|
||||
struct clocksource mct_frc = {
|
||||
.name = "mct-frc",
|
||||
.rating = 400,
|
||||
.read = exynos4_frc_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
.resume = exynos4_frc_resume,
|
||||
};
|
||||
|
||||
static void __init exynos4_clocksource_init(void)
|
||||
|
@ -389,9 +395,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
|
|||
}
|
||||
|
||||
/* Setup the local clock events for a CPU */
|
||||
void __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
int __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
{
|
||||
exynos4_mct_tick_init(evt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int local_timer_ack(void)
|
||||
|
|
|
@ -106,6 +106,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
|||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
set_cpu_online(cpu, true);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
|
|
|
@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
|||
|
||||
if (rows > 8) {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[0~7] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
|
||||
S3C_GPIO_PULL_UP);
|
||||
|
||||
/* Set all the necessary GPX3 pins: KP_ROW[8~] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
} else {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[x] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
|
||||
S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
|
||||
S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
/* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
|
|||
static void __init ap_map_io(void)
|
||||
{
|
||||
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
|
||||
vga_base = PCI_MEMORY_VADDR;
|
||||
}
|
||||
|
||||
#define INTEGRATOR_SC_VALID_INT 0x003fffff
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
|
|||
|
||||
pcibios_min_io = 0x6000;
|
||||
pcibios_min_mem = 0x00100000;
|
||||
vga_base = PCI_MEMORY_VADDR;
|
||||
|
||||
/*
|
||||
* Hook in our fault handler for PCI errors
|
||||
|
|
|
@ -193,7 +193,8 @@ static int __init omap2430_i2c_init(void)
|
|||
{
|
||||
omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
|
||||
ARRAY_SIZE(sdp2430_i2c1_boardinfo));
|
||||
omap2_pmic_init("twl4030", &sdp2430_twldata);
|
||||
omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
|
||||
&sdp2430_twldata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -137,8 +137,7 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
|
|||
*/
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
|
||||
|
@ -156,8 +155,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
else
|
||||
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(5);
|
||||
|
@ -171,16 +169,14 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
|
||||
pr_err("Pbias Voltage is not same as LDO\n");
|
||||
/* Caution : On VMODE_ERROR Power Down MMC IO */
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
} else {
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -137,9 +137,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
|
|||
musb_plat.mode = board_data->mode;
|
||||
musb_plat.extvbus = board_data->extvbus;
|
||||
|
||||
if (cpu_is_omap44xx())
|
||||
omap4430_phy_init(dev);
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505()) {
|
||||
oh_name = "am35x_otg_hs";
|
||||
name = "musb-am35x";
|
||||
|
|
|
@ -170,7 +170,9 @@ int __init s3c2410_init(void)
|
|||
{
|
||||
printk("S3C2410: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2410_sysdev);
|
||||
|
|
|
@ -245,7 +245,9 @@ int __init s3c2412_init(void)
|
|||
{
|
||||
printk("S3C2412: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2412_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2412_sysdev);
|
||||
|
|
|
@ -97,7 +97,9 @@ int __init s3c2416_init(void)
|
|||
|
||||
s3c_fb_setname("s3c2443-fb");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2416_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2416_sysdev);
|
||||
|
|
|
@ -55,7 +55,9 @@ int __init s3c2440_init(void)
|
|||
|
||||
/* register suspend/resume handlers */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
|
|
@ -169,7 +169,9 @@ int __init s3c2442_init(void)
|
|||
{
|
||||
printk("S3C2442: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
|
|
@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
|
|||
unsigned long clkcon0;
|
||||
|
||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||
clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
||||
}
|
||||
|
|
|
@ -262,45 +262,6 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
|
|||
.cols = 8,
|
||||
};
|
||||
|
||||
static int smdk6410_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S3C64XX_GPF(15), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
|
||||
s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdk6410_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S3C64XX_GPF(15));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdk6410_backlight_data = {
|
||||
.pwm_id = 1,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdk6410_backlight_init,
|
||||
.exit = smdk6410_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdk6410_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[1].dev,
|
||||
.platform_data = &smdk6410_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc smdk6410_iodesc[] = {};
|
||||
|
||||
static struct platform_device *smdk6410_devices[] __initdata = {
|
||||
|
|
|
@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "s5pv210-fimc.0",
|
||||
.name = "sclk_cam0",
|
||||
.enable = s5pv210_clk_mask0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
},
|
||||
|
@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "s5pv210-fimc.1",
|
||||
.name = "sclk_cam1",
|
||||
.enable = s5pv210_clk_mask0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
|
|
|
@ -32,7 +32,6 @@
|
|||
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/clk.h>
|
||||
|
||||
/* Frequency table index must be sequential starting at 0 */
|
||||
|
|
|
@ -6,6 +6,7 @@ config UX500_SOC_COMMON
|
|||
select ARM_GIC
|
||||
select HAS_MTU
|
||||
select ARM_ERRATA_753970
|
||||
select ARM_ERRATA_754322
|
||||
|
||||
menu "Ux500 SoC"
|
||||
|
||||
|
|
|
@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
|
|||
dcache_line_size r2, r3
|
||||
sub r3, r2, #1
|
||||
bic r12, r0, r3
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
ALT_SMP(W(dsb))
|
||||
ALT_UP(W(nop))
|
||||
#endif
|
||||
1:
|
||||
USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
|
||||
add r12, r12, r2
|
||||
|
@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
|
|||
add r1, r0, r1
|
||||
sub r3, r2, #1
|
||||
bic r0, r0, r3
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
ALT_SMP(W(dsb))
|
||||
ALT_UP(W(nop))
|
||||
#endif
|
||||
1:
|
||||
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
|
||||
add r0, r0, r2
|
||||
|
@ -247,6 +255,10 @@ v7_dma_inv_range:
|
|||
sub r3, r2, #1
|
||||
tst r0, r3
|
||||
bic r0, r0, r3
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
ALT_SMP(W(dsb))
|
||||
ALT_UP(W(nop))
|
||||
#endif
|
||||
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
|
||||
|
||||
tst r1, r3
|
||||
|
@ -270,6 +282,10 @@ v7_dma_clean_range:
|
|||
dcache_line_size r2, r3
|
||||
sub r3, r2, #1
|
||||
bic r0, r0, r3
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
ALT_SMP(W(dsb))
|
||||
ALT_UP(W(nop))
|
||||
#endif
|
||||
1:
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
|
||||
add r0, r0, r2
|
||||
|
@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
|
|||
dcache_line_size r2, r3
|
||||
sub r3, r2, #1
|
||||
bic r0, r0, r3
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
ALT_SMP(W(dsb))
|
||||
ALT_UP(W(nop))
|
||||
#endif
|
||||
1:
|
||||
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
|
||||
add r0, r0, r2
|
||||
|
|
|
@ -324,6 +324,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
|
|||
|
||||
if (addr)
|
||||
*handle = pfn_to_dma(dev, page_to_pfn(page));
|
||||
else
|
||||
__dma_free_buffer(page, size);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
|
|
@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi)
|
|||
*/
|
||||
bank_start = min(bank_start,
|
||||
ALIGN(prev_bank_end, PAGES_PER_SECTION));
|
||||
#else
|
||||
/*
|
||||
* Align down here since the VM subsystem insists that the
|
||||
* memmap entries are valid from the bank start aligned to
|
||||
* MAX_ORDER_NR_PAGES.
|
||||
*/
|
||||
bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
|
||||
#endif
|
||||
/*
|
||||
* If we had a previous bank, and there is a space
|
||||
|
|
|
@ -114,17 +114,18 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
|
|||
{
|
||||
static int used_gpioint_groups = 0;
|
||||
int group = chip->group;
|
||||
struct s5p_gpioint_bank *bank = NULL;
|
||||
struct s5p_gpioint_bank *b, *bank = NULL;
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
|
||||
if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
|
||||
return -ENOMEM;
|
||||
|
||||
list_for_each_entry(bank, &banks, list) {
|
||||
if (group >= bank->start &&
|
||||
group < bank->start + bank->nr_groups)
|
||||
list_for_each_entry(b, &banks, list) {
|
||||
if (group >= b->start && group < b->start + b->nr_groups) {
|
||||
bank = b;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!bank)
|
||||
return -EINVAL;
|
||||
|
@ -162,9 +163,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
|
|||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_set_type = s5p_gpioint_set_type,
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
|
||||
IRQ_GC_INIT_MASK_CACHE,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
||||
|
|
|
@ -64,6 +64,17 @@ static LIST_HEAD(clocks);
|
|||
*/
|
||||
DEFINE_SPINLOCK(clocks_lock);
|
||||
|
||||
/* Global watchdog clock used by arch_wtd_reset() callback */
|
||||
struct clk *s3c2410_wdtclk;
|
||||
static int __init s3c_wdt_reset_init(void)
|
||||
{
|
||||
s3c2410_wdtclk = clk_get(NULL, "watchdog");
|
||||
if (IS_ERR(s3c2410_wdtclk))
|
||||
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(s3c_wdt_reset_init);
|
||||
|
||||
/* enable and disable calls for use with the clk struct */
|
||||
|
||||
static int clk_null_enable(struct clk *clk, int enable)
|
||||
|
|
|
@ -9,6 +9,9 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_PLAT_CLOCK_H
|
||||
#define __ASM_PLAT_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
|
@ -121,3 +124,8 @@ extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
|
|||
|
||||
extern void s3c_pwmclk_init(void);
|
||||
|
||||
/* Global watchdog clock used by arch_wtd_reset() callback */
|
||||
|
||||
extern struct clk *s3c2410_wdtclk;
|
||||
|
||||
#endif /* __ASM_PLAT_CLOCK_H */
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <plat/clock.h>
|
||||
#include <plat/regs-watchdog.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
|
@ -19,17 +20,12 @@
|
|||
|
||||
static inline void arch_wdt_reset(void)
|
||||
{
|
||||
struct clk *wdtclk;
|
||||
|
||||
printk("arch_reset: attempting watchdog reset\n");
|
||||
|
||||
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
|
||||
|
||||
wdtclk = clk_get(NULL, "watchdog");
|
||||
if (!IS_ERR(wdtclk)) {
|
||||
clk_enable(wdtclk);
|
||||
} else
|
||||
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
|
||||
if (s3c2410_wdtclk)
|
||||
clk_enable(s3c2410_wdtclk);
|
||||
|
||||
/* put initial values into count and data */
|
||||
__raw_writel(0x80, S3C2410_WTCNT);
|
||||
|
|
|
@ -24,6 +24,7 @@ config MIPS
|
|||
select GENERIC_IRQ_PROBE
|
||||
select GENERIC_IRQ_SHOW
|
||||
select HAVE_ARCH_JUMP_LABEL
|
||||
select IRQ_FORCED_THREADING
|
||||
|
||||
menu "Machine selection"
|
||||
|
||||
|
@ -722,6 +723,7 @@ config CAVIUM_OCTEON_SIMULATOR
|
|||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_SUPPORTS_HOTPLUG_CPU
|
||||
select SYS_HAS_CPU_CAVIUM_OCTEON
|
||||
select HOLES_IN_ZONE
|
||||
help
|
||||
The Octeon simulator is software performance model of the Cavium
|
||||
Octeon Processor. It supports simulating Octeon processors on x86
|
||||
|
@ -744,6 +746,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
|
|||
select ZONE_DMA32
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select HOLES_IN_ZONE
|
||||
help
|
||||
This option supports all of the Octeon reference boards from Cavium
|
||||
Networks. It builds a kernel that dynamically determines the Octeon
|
||||
|
@ -973,6 +976,9 @@ config ISA_DMA_API
|
|||
config GENERIC_GPIO
|
||||
bool
|
||||
|
||||
config HOLES_IN_ZONE
|
||||
bool
|
||||
|
||||
#
|
||||
# Endianess selection. Sufficiently obscure so many users don't know what to
|
||||
# answer,so we try hard to limit the available choices. Also the use of a
|
||||
|
|
|
@ -492,7 +492,7 @@ static void __init alchemy_setup_macs(int ctype)
|
|||
memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
|
||||
|
||||
ret = platform_device_register(&au1xxx_eth0_device);
|
||||
if (!ret)
|
||||
if (ret)
|
||||
printk(KERN_INFO "Alchemy: failed to register MAC0\n");
|
||||
|
||||
|
||||
|
|
|
@ -158,15 +158,21 @@ static void restore_core_regs(void)
|
|||
|
||||
void au_sleep(void)
|
||||
{
|
||||
int cpuid = alchemy_get_cputype();
|
||||
if (cpuid != ALCHEMY_CPU_UNKNOWN) {
|
||||
save_core_regs();
|
||||
if (cpuid <= ALCHEMY_CPU_AU1500)
|
||||
alchemy_sleep_au1000();
|
||||
else if (cpuid <= ALCHEMY_CPU_AU1200)
|
||||
alchemy_sleep_au1550();
|
||||
restore_core_regs();
|
||||
save_core_regs();
|
||||
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000:
|
||||
case ALCHEMY_CPU_AU1500:
|
||||
case ALCHEMY_CPU_AU1100:
|
||||
alchemy_sleep_au1000();
|
||||
break;
|
||||
case ALCHEMY_CPU_AU1550:
|
||||
case ALCHEMY_CPU_AU1200:
|
||||
alchemy_sleep_au1550();
|
||||
break;
|
||||
}
|
||||
|
||||
restore_core_regs();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
|
|
@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
|
|||
{
|
||||
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
for ( ; bisr; bisr &= bisr - 1)
|
||||
generic_handle_irq(bcsr_csc_base + __ffs(bisr));
|
||||
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
/* NOTE: both the enable and mask bits must be cleared, otherwise the
|
||||
|
|
|
@ -23,13 +23,6 @@ void __init board_setup(void)
|
|||
unsigned long freq0, clksrc, div, pfc;
|
||||
unsigned short whoami;
|
||||
|
||||
/* Set Config[OD] (disable overlapping bus transaction):
|
||||
* This gets rid of a _lot_ of spurious interrupts (especially
|
||||
* wrt. IDE); but incurs ~10% performance hit in some
|
||||
* cpu-bound applications.
|
||||
*/
|
||||
set_c0_config(1 << 19);
|
||||
|
||||
bcsr_init(DB1200_BCSR_PHYS_ADDR,
|
||||
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
|
||||
|
||||
|
|
|
@ -98,7 +98,8 @@ static struct irq_chip ar7_sec_irq_type = {
|
|||
|
||||
static struct irqaction ar7_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "AR7 cascade interrupt"
|
||||
.name = "AR7 cascade interrupt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static void __init ar7_irq_init(int base)
|
||||
|
|
|
@ -222,6 +222,7 @@ static struct irq_chip bcm63xx_external_irq_chip = {
|
|||
static struct irqaction cpu_ip2_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade_ip2",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -48,6 +48,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -101,20 +101,24 @@ int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
|
|||
static struct irqaction ioirq = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
static struct irqaction fpuirq = {
|
||||
.handler = no_action,
|
||||
.name = "fpu",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction busirq = {
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "bus error",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction haltirq = {
|
||||
.handler = dec_intr_halt,
|
||||
.name = "halt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -169,7 +169,7 @@ void emma2rh_gpio_irq_init(void)
|
|||
|
||||
static struct irqaction irq_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = 0,
|
||||
.flags = IRQF_NO_THREAD,
|
||||
.name = "cascade",
|
||||
.dev_id = NULL,
|
||||
.next = NULL,
|
||||
|
|
|
@ -54,7 +54,6 @@
|
|||
#define cpu_has_mips_r2_exec_hazard 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
#define cpu_has_vint 0
|
||||
#define cpu_has_veic 0
|
||||
#define cpu_hwrena_impl_bits 0xc0000000
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/device.h>
|
||||
#include <asm/mach-powertv/asic.h>
|
||||
|
||||
|
|
|
@ -195,9 +195,9 @@
|
|||
* to cover the pipeline delay.
|
||||
*/
|
||||
.set mips32
|
||||
mfc0 v1, CP0_TCSTATUS
|
||||
mfc0 k0, CP0_TCSTATUS
|
||||
.set mips0
|
||||
LONG_S v1, PT_TCSTATUS(sp)
|
||||
LONG_S k0, PT_TCSTATUS(sp)
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
LONG_S $4, PT_R4(sp)
|
||||
LONG_S $5, PT_R5(sp)
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
#include <linux/init.h>
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
|
@ -86,7 +86,6 @@ struct jz_gpio_chip {
|
|||
spinlock_t lock;
|
||||
|
||||
struct gpio_chip gpio_chip;
|
||||
struct sys_device sysdev;
|
||||
};
|
||||
|
||||
static struct jz_gpio_chip jz4740_gpio_chips[];
|
||||
|
@ -459,49 +458,47 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = {
|
|||
JZ4740_GPIO_CHIP(D),
|
||||
};
|
||||
|
||||
static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
|
||||
static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
|
||||
{
|
||||
return container_of(dev, struct jz_gpio_chip, sysdev);
|
||||
}
|
||||
|
||||
static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
struct jz_gpio_chip *chip = sysdev_to_chip(dev);
|
||||
|
||||
chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
|
||||
writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
|
||||
writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
||||
}
|
||||
|
||||
static int jz4740_gpio_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
|
||||
jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_gpio_resume(struct sys_device *dev)
|
||||
static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
|
||||
{
|
||||
struct jz_gpio_chip *chip = sysdev_to_chip(dev);
|
||||
uint32_t mask = chip->suspend_mask;
|
||||
|
||||
writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
||||
writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_class jz4740_gpio_sysdev_class = {
|
||||
.name = "gpio",
|
||||
static void jz4740_gpio_resume(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
|
||||
jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
|
||||
}
|
||||
|
||||
static struct syscore_ops jz4740_gpio_syscore_ops = {
|
||||
.suspend = jz4740_gpio_suspend,
|
||||
.resume = jz4740_gpio_resume,
|
||||
};
|
||||
|
||||
static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
||||
static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
||||
{
|
||||
int ret, irq;
|
||||
|
||||
chip->sysdev.id = id;
|
||||
chip->sysdev.cls = &jz4740_gpio_sysdev_class;
|
||||
ret = sysdev_register(&chip->sysdev);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
int irq;
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
|
||||
|
@ -519,22 +516,17 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
|||
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init jz4740_gpio_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
|
||||
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
|
||||
|
||||
register_syscore_ops(&jz4740_gpio_syscore_ops);
|
||||
|
||||
printk(KERN_INFO "JZ4740 GPIO initialized\n");
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -19,6 +19,26 @@
|
|||
|
||||
#include <asm-generic/sections.h>
|
||||
|
||||
#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
|
||||
#define MCOUNT_OFFSET_INSNS 5
|
||||
#else
|
||||
#define MCOUNT_OFFSET_INSNS 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if the address is in kernel space
|
||||
*
|
||||
* Clone core_kernel_text() from kernel/extable.c, but doesn't call
|
||||
* init_kernel_text() for Ftrace doesn't trace functions in init sections.
|
||||
*/
|
||||
static inline int in_kernel_space(unsigned long ip)
|
||||
{
|
||||
if (ip >= (unsigned long)_stext &&
|
||||
ip <= (unsigned long)_etext)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
|
||||
#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
|
||||
|
@ -54,20 +74,6 @@ static inline void ftrace_dyn_arch_init_insns(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the address is in kernel space
|
||||
*
|
||||
* Clone core_kernel_text() from kernel/extable.c, but doesn't call
|
||||
* init_kernel_text() for Ftrace doesn't trace functions in init sections.
|
||||
*/
|
||||
static inline int in_kernel_space(unsigned long ip)
|
||||
{
|
||||
if (ip >= (unsigned long)_stext &&
|
||||
ip <= (unsigned long)_etext)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
|
||||
{
|
||||
int faulted;
|
||||
|
@ -112,11 +118,6 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
|
|||
* 1: offset = 4 instructions
|
||||
*/
|
||||
|
||||
#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
|
||||
#define MCOUNT_OFFSET_INSNS 5
|
||||
#else
|
||||
#define MCOUNT_OFFSET_INSNS 4
|
||||
#endif
|
||||
#define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)
|
||||
|
||||
int ftrace_make_nop(struct module *mod,
|
||||
|
|
|
@ -229,7 +229,7 @@ static void i8259A_shutdown(void)
|
|||
*/
|
||||
if (i8259A_auto_eoi >= 0) {
|
||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
|
||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -295,6 +295,7 @@ static void init_8259A(int auto_eoi)
|
|||
static struct irqaction irq2 = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct resource pic1_io_resource = {
|
||||
|
|
|
@ -349,3 +349,10 @@ SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
|
|||
return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
|
||||
dfd, pathname);
|
||||
}
|
||||
|
||||
SYSCALL_DEFINE6(32_futex, u32 __user *, uaddr, int, op, u32, val,
|
||||
struct compat_timespec __user *, utime, u32 __user *, uaddr2,
|
||||
u32, val3)
|
||||
{
|
||||
return compat_sys_futex(uaddr, op, val, utime, uaddr2, val3);
|
||||
}
|
||||
|
|
|
@ -315,7 +315,7 @@ EXPORT(sysn32_call_table)
|
|||
PTR sys_fremovexattr
|
||||
PTR sys_tkill
|
||||
PTR sys_ni_syscall
|
||||
PTR compat_sys_futex
|
||||
PTR sys_32_futex
|
||||
PTR compat_sys_sched_setaffinity /* 6195 */
|
||||
PTR compat_sys_sched_getaffinity
|
||||
PTR sys_cacheflush
|
||||
|
|
|
@ -441,7 +441,7 @@ sys_call_table:
|
|||
PTR sys_fremovexattr /* 4235 */
|
||||
PTR sys_tkill
|
||||
PTR sys_sendfile64
|
||||
PTR compat_sys_futex
|
||||
PTR sys_32_futex
|
||||
PTR compat_sys_sched_setaffinity
|
||||
PTR compat_sys_sched_getaffinity /* 4240 */
|
||||
PTR compat_sys_io_setup
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#include <linux/cache.h>
|
||||
#include <linux/irqflags.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/personality.h>
|
||||
|
@ -658,6 +659,8 @@ static void do_signal(struct pt_regs *regs)
|
|||
asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
|
||||
__u32 thread_info_flags)
|
||||
{
|
||||
local_irq_enable();
|
||||
|
||||
/* deal with pending signal delivery */
|
||||
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
|
||||
do_signal(regs);
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/bug.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
|
@ -364,21 +365,26 @@ static int regs_to_trapnr(struct pt_regs *regs)
|
|||
return (regs->cp0_cause >> 2) & 0x1f;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(die_lock);
|
||||
static DEFINE_RAW_SPINLOCK(die_lock);
|
||||
|
||||
void __noreturn die(const char *str, struct pt_regs *regs)
|
||||
{
|
||||
static int die_counter;
|
||||
int sig = SIGSEGV;
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
unsigned long dvpret = dvpe();
|
||||
unsigned long dvpret;
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
|
||||
oops_enter();
|
||||
|
||||
if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
|
||||
sig = 0;
|
||||
|
||||
console_verbose();
|
||||
spin_lock_irq(&die_lock);
|
||||
raw_spin_lock_irq(&die_lock);
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
dvpret = dvpe();
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
bust_spinlocks(1);
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
mips_mt_regdump(dvpret);
|
||||
|
@ -387,7 +393,9 @@ void __noreturn die(const char *str, struct pt_regs *regs)
|
|||
printk("%s[#%d]:\n", str, ++die_counter);
|
||||
show_registers(regs);
|
||||
add_taint(TAINT_DIE);
|
||||
spin_unlock_irq(&die_lock);
|
||||
raw_spin_unlock_irq(&die_lock);
|
||||
|
||||
oops_exit();
|
||||
|
||||
if (in_interrupt())
|
||||
panic("Fatal exception in interrupt");
|
||||
|
|
|
@ -192,7 +192,7 @@ static struct tc *get_tc(int index)
|
|||
}
|
||||
spin_unlock(&vpecontrol.tc_list_lock);
|
||||
|
||||
return NULL;
|
||||
return res;
|
||||
}
|
||||
|
||||
/* allocate a vpe and associate it with this minor (or index) */
|
||||
|
|
|
@ -123,11 +123,10 @@ void ltq_enable_irq(struct irq_data *d)
|
|||
static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_enable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
if (d->irq == ltq_eiu_irq[i]) {
|
||||
/* low level - we should really handle set_type */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
|
@ -147,11 +146,10 @@ static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
|||
static void ltq_shutdown_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_disable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
if (d->irq == ltq_eiu_irq[i]) {
|
||||
/* disable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
|
|
|
@ -10,7 +10,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
|
@ -105,6 +105,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -42,6 +42,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
|
|||
static struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init mach_init_irq(void)
|
||||
|
|
|
@ -96,12 +96,13 @@ static irqreturn_t ip6_action(int cpl, void *dev_id)
|
|||
struct irqaction ip6_irqaction = {
|
||||
.handler = ip6_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_SHARED,
|
||||
.flags = IRQF_SHARED | IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init mach_init_irq(void)
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
* Copyright (C) 2011 Wind River Systems,
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/mman.h>
|
||||
|
@ -15,12 +16,11 @@
|
|||
#include <linux/sched.h>
|
||||
|
||||
unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
|
||||
|
||||
EXPORT_SYMBOL(shm_align_mask);
|
||||
|
||||
/* gap between mmap and stack */
|
||||
#define MIN_GAP (128*1024*1024UL)
|
||||
#define MAX_GAP ((TASK_SIZE)/6*5)
|
||||
#define MAX_GAP ((TASK_SIZE)/6*5)
|
||||
|
||||
static int mmap_is_legacy(void)
|
||||
{
|
||||
|
@ -57,13 +57,13 @@ static inline unsigned long COLOUR_ALIGN_DOWN(unsigned long addr,
|
|||
return base - off;
|
||||
}
|
||||
|
||||
#define COLOUR_ALIGN(addr,pgoff) \
|
||||
#define COLOUR_ALIGN(addr, pgoff) \
|
||||
((((addr) + shm_align_mask) & ~shm_align_mask) + \
|
||||
(((pgoff) << PAGE_SHIFT) & shm_align_mask))
|
||||
|
||||
enum mmap_allocation_direction {UP, DOWN};
|
||||
|
||||
static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
||||
static unsigned long arch_get_unmapped_area_common(struct file *filp,
|
||||
unsigned long addr0, unsigned long len, unsigned long pgoff,
|
||||
unsigned long flags, enum mmap_allocation_direction dir)
|
||||
{
|
||||
|
@ -103,16 +103,16 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
|
||||
vma = find_vma(mm, addr);
|
||||
if (TASK_SIZE - len >= addr &&
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
return addr;
|
||||
}
|
||||
|
||||
if (dir == UP) {
|
||||
addr = mm->mmap_base;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
|
||||
for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {
|
||||
/* At this point: (!vma || addr < vma->vm_end). */
|
||||
|
@ -131,28 +131,30 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
mm->free_area_cache = mm->mmap_base;
|
||||
}
|
||||
|
||||
/* either no address requested or can't fit in requested address hole */
|
||||
/*
|
||||
* either no address requested, or the mapping can't fit into
|
||||
* the requested address hole
|
||||
*/
|
||||
addr = mm->free_area_cache;
|
||||
if (do_color_align) {
|
||||
unsigned long base =
|
||||
COLOUR_ALIGN_DOWN(addr - len, pgoff);
|
||||
|
||||
if (do_color_align) {
|
||||
unsigned long base =
|
||||
COLOUR_ALIGN_DOWN(addr - len, pgoff);
|
||||
addr = base + len;
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure it can fit in the remaining address space */
|
||||
if (likely(addr > len)) {
|
||||
vma = find_vma(mm, addr - len);
|
||||
if (!vma || addr <= vma->vm_start) {
|
||||
/* remember the address as a hint for next time */
|
||||
return mm->free_area_cache = addr-len;
|
||||
/* cache the address as a hint for next time */
|
||||
return mm->free_area_cache = addr - len;
|
||||
}
|
||||
}
|
||||
|
||||
if (unlikely(mm->mmap_base < len))
|
||||
goto bottomup;
|
||||
|
||||
addr = mm->mmap_base-len;
|
||||
addr = mm->mmap_base - len;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN_DOWN(addr, pgoff);
|
||||
|
||||
|
@ -163,8 +165,8 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
* return with success:
|
||||
*/
|
||||
vma = find_vma(mm, addr);
|
||||
if (likely(!vma || addr+len <= vma->vm_start)) {
|
||||
/* remember the address as a hint for next time */
|
||||
if (likely(!vma || addr + len <= vma->vm_start)) {
|
||||
/* cache the address as a hint for next time */
|
||||
return mm->free_area_cache = addr;
|
||||
}
|
||||
|
||||
|
@ -173,7 +175,7 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
mm->cached_hole_size = vma->vm_start - addr;
|
||||
|
||||
/* try just below the current vma->vm_start */
|
||||
addr = vma->vm_start-len;
|
||||
addr = vma->vm_start - len;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN_DOWN(addr, pgoff);
|
||||
} while (likely(len < vma->vm_start));
|
||||
|
@ -201,7 +203,7 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr0,
|
||||
unsigned long len, unsigned long pgoff, unsigned long flags)
|
||||
{
|
||||
return arch_get_unmapped_area_foo(filp,
|
||||
return arch_get_unmapped_area_common(filp,
|
||||
addr0, len, pgoff, flags, UP);
|
||||
}
|
||||
|
||||
|
@ -213,7 +215,7 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
|
|||
unsigned long addr0, unsigned long len, unsigned long pgoff,
|
||||
unsigned long flags)
|
||||
{
|
||||
return arch_get_unmapped_area_foo(filp,
|
||||
return arch_get_unmapped_area_common(filp,
|
||||
addr0, len, pgoff, flags, DOWN);
|
||||
}
|
||||
|
||||
|
|
|
@ -1759,14 +1759,13 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
|
|||
u32 *p = handle_tlbm;
|
||||
struct uasm_label *l = labels;
|
||||
struct uasm_reloc *r = relocs;
|
||||
struct work_registers wr;
|
||||
|
||||
memset(handle_tlbm, 0, sizeof(handle_tlbm));
|
||||
memset(labels, 0, sizeof(labels));
|
||||
memset(relocs, 0, sizeof(relocs));
|
||||
|
||||
build_r3000_tlbchange_handler_head(&p, K0, K1);
|
||||
build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
|
||||
build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
|
||||
uasm_i_nop(&p); /* load delay */
|
||||
build_make_write(&p, &r, K0, K1);
|
||||
build_r3000_pte_reload_tlbwi(&p, K0, K1);
|
||||
|
@ -1963,7 +1962,8 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
|
|||
uasm_i_andi(&p, wr.r3, wr.r3, 2);
|
||||
uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
|
||||
}
|
||||
|
||||
if (PM_DEFAULT_MASK == 0)
|
||||
uasm_i_nop(&p);
|
||||
/*
|
||||
* We clobbered C0_PAGEMASK, restore it. On the other branch
|
||||
* it is restored in build_huge_tlb_write_entry.
|
||||
|
|
|
@ -350,12 +350,14 @@ unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
|
|||
|
||||
static struct irqaction i8259irq = {
|
||||
.handler = no_action,
|
||||
.name = "XT-PIC cascade"
|
||||
.name = "XT-PIC cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction corehi_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "CoreHi"
|
||||
.name = "CoreHi",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static msc_irqmap_t __initdata msc_irqmap[] = {
|
||||
|
|
|
@ -2,4 +2,4 @@ obj-y += setup.o platform.o irq.o setup.o time.o
|
|||
obj-$(CONFIG_SMP) += smp.o smpboot.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
ccflags-y += -Werror
|
||||
|
|
|
@ -171,8 +171,13 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
|
|||
u32 temp_buffer;
|
||||
|
||||
/* set clock to 33Mhz */
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
|
||||
if (ltq_is_ar9()) {
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
|
||||
} else {
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
|
||||
}
|
||||
|
||||
/* external or internal clock ? */
|
||||
if (conf->clock) {
|
||||
|
|
|
@ -215,7 +215,7 @@ static int __init rc32434_pci_init(void)
|
|||
rc32434_pcibridge_init();
|
||||
|
||||
io_map_base = ioremap(rc32434_res_pci_io1.start,
|
||||
resource_size(&rcrc32434_res_pci_io1));
|
||||
resource_size(&rc32434_res_pci_io1));
|
||||
|
||||
if (!io_map_base)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -108,12 +108,14 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
static struct irqaction cic_cascade_msp = {
|
||||
.handler = no_action,
|
||||
.name = "MSP CIC cascade"
|
||||
.name = "MSP CIC cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction per_cascade_msp = {
|
||||
.handler = no_action,
|
||||
.name = "MSP PER cascade"
|
||||
.name = "MSP PER cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -167,7 +167,7 @@ static struct irq_chip level_irq_type = {
|
|||
|
||||
static struct irqaction gic_action = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "GIC",
|
||||
};
|
||||
|
||||
|
|
|
@ -155,32 +155,32 @@ static void __irq_entry indy_buserror_irq(void)
|
|||
|
||||
static struct irqaction local0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "local0 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction local1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "local1 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction buserr = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "Bus Error",
|
||||
};
|
||||
|
||||
static struct irqaction map0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "mapable0 cascade",
|
||||
};
|
||||
|
||||
#ifdef USE_LIO3_IRQ
|
||||
static struct irqaction map1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "mapable1 cascade",
|
||||
};
|
||||
#define SGI_INTERRUPTS SGINT_END
|
||||
|
|
|
@ -359,6 +359,7 @@ void sni_rm200_init_8259A(void)
|
|||
static struct irqaction sni_rm200_irq2 = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct resource sni_rm200_pic1_resource = {
|
||||
|
|
|
@ -34,6 +34,7 @@ static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
|
|||
static struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
|
||||
|
|
|
@ -561,6 +561,20 @@ static struct pci_ops u4_pcie_pci_ops =
|
|||
.write = u4_pcie_write_config,
|
||||
};
|
||||
|
||||
static void __devinit pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
|
||||
{
|
||||
/* Apple's device-tree "hides" the root complex virtual P2P bridge
|
||||
* on U4. However, Linux sees it, causing the PCI <-> OF matching
|
||||
* code to fail to properly match devices below it. This works around
|
||||
* it by setting the node of the bridge to point to the PHB node,
|
||||
* which is not entirely correct but fixes the matching code and
|
||||
* doesn't break anything else. It's also the simplest possible fix.
|
||||
*/
|
||||
if (dev->dev.of_node == NULL)
|
||||
dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
|
||||
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
#ifdef CONFIG_PPC32
|
||||
|
|
|
@ -188,7 +188,8 @@ extern char elf_platform[];
|
|||
#define SET_PERSONALITY(ex) \
|
||||
do { \
|
||||
if (personality(current->personality) != PER_LINUX32) \
|
||||
set_personality(PER_LINUX); \
|
||||
set_personality(PER_LINUX | \
|
||||
(current->personality & ~PER_MASK)); \
|
||||
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
|
||||
set_thread_flag(TIF_31BIT); \
|
||||
else \
|
||||
|
|
|
@ -658,12 +658,14 @@ static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste)
|
|||
* struct gmap_struct - guest address space
|
||||
* @mm: pointer to the parent mm_struct
|
||||
* @table: pointer to the page directory
|
||||
* @asce: address space control element for gmap page table
|
||||
* @crst_list: list of all crst tables used in the guest address space
|
||||
*/
|
||||
struct gmap {
|
||||
struct list_head list;
|
||||
struct mm_struct *mm;
|
||||
unsigned long *table;
|
||||
unsigned long asce;
|
||||
struct list_head crst_list;
|
||||
};
|
||||
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <asm/vdso.h>
|
||||
#include <asm/sigp.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
/*
|
||||
* Make sure that the compiler is new enough. We want a compiler that
|
||||
|
@ -126,6 +127,7 @@ int main(void)
|
|||
DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
|
||||
DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
|
||||
DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
|
||||
DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
|
||||
DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
|
||||
DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
|
||||
DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
|
||||
|
@ -151,6 +153,7 @@ int main(void)
|
|||
DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
|
||||
DEFINE(__LC_GMAP, offsetof(struct _lowcore, gmap));
|
||||
DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp));
|
||||
DEFINE(__GMAP_ASCE, offsetof(struct gmap, asce));
|
||||
#endif /* CONFIG_32BIT */
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1076,6 +1076,11 @@ sie_loop:
|
|||
lg %r14,__LC_THREAD_INFO # pointer thread_info struct
|
||||
tm __TI_flags+7(%r14),_TIF_EXIT_SIE
|
||||
jnz sie_exit
|
||||
lg %r14,__LC_GMAP # get gmap pointer
|
||||
ltgr %r14,%r14
|
||||
jz sie_gmap
|
||||
lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
|
||||
sie_gmap:
|
||||
lg %r14,__SF_EMPTY(%r15) # get control block pointer
|
||||
SPP __SF_EMPTY(%r15) # set guest id
|
||||
sie 0(%r14)
|
||||
|
@ -1083,6 +1088,7 @@ sie_done:
|
|||
SPP __LC_CMF_HPP # set host id
|
||||
lg %r14,__LC_THREAD_INFO # pointer thread_info struct
|
||||
sie_exit:
|
||||
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
|
||||
ni __TI_flags+6(%r14),255-(_TIF_SIE>>8)
|
||||
lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
|
||||
stmg %r0,%r13,0(%r14) # save guest gprs 0-13
|
||||
|
|
|
@ -123,6 +123,7 @@ int kvm_dev_ioctl_check_extension(long ext)
|
|||
|
||||
switch (ext) {
|
||||
case KVM_CAP_S390_PSW:
|
||||
case KVM_CAP_S390_GMAP:
|
||||
r = 1;
|
||||
break;
|
||||
default:
|
||||
|
@ -263,10 +264,12 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
vcpu->arch.guest_fpregs.fpc &= FPC_VALID_MASK;
|
||||
restore_fp_regs(&vcpu->arch.guest_fpregs);
|
||||
restore_access_regs(vcpu->arch.guest_acrs);
|
||||
gmap_enable(vcpu->arch.gmap);
|
||||
}
|
||||
|
||||
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
gmap_disable(vcpu->arch.gmap);
|
||||
save_fp_regs(&vcpu->arch.guest_fpregs);
|
||||
save_access_regs(vcpu->arch.guest_acrs);
|
||||
restore_fp_regs(&vcpu->arch.host_fpregs);
|
||||
|
@ -461,7 +464,6 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
|
|||
local_irq_disable();
|
||||
kvm_guest_enter();
|
||||
local_irq_enable();
|
||||
gmap_enable(vcpu->arch.gmap);
|
||||
VCPU_EVENT(vcpu, 6, "entering sie flags %x",
|
||||
atomic_read(&vcpu->arch.sie_block->cpuflags));
|
||||
if (sie64a(vcpu->arch.sie_block, vcpu->arch.guest_gprs)) {
|
||||
|
@ -470,7 +472,6 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
|
|||
}
|
||||
VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
|
||||
vcpu->arch.sie_block->icptcode);
|
||||
gmap_disable(vcpu->arch.gmap);
|
||||
local_irq_disable();
|
||||
kvm_guest_exit();
|
||||
local_irq_enable();
|
||||
|
|
|
@ -160,6 +160,8 @@ struct gmap *gmap_alloc(struct mm_struct *mm)
|
|||
table = (unsigned long *) page_to_phys(page);
|
||||
crst_table_init(table, _REGION1_ENTRY_EMPTY);
|
||||
gmap->table = table;
|
||||
gmap->asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | __pa(table);
|
||||
list_add(&gmap->list, &mm->context.gmap_list);
|
||||
return gmap;
|
||||
|
||||
|
@ -240,10 +242,6 @@ EXPORT_SYMBOL_GPL(gmap_free);
|
|||
*/
|
||||
void gmap_enable(struct gmap *gmap)
|
||||
{
|
||||
/* Load primary space page table origin. */
|
||||
S390_lowcore.user_asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
|
||||
_ASCE_USER_BITS | __pa(gmap->table);
|
||||
asm volatile("lctlg 1,1,%0\n" : : "m" (S390_lowcore.user_asce) );
|
||||
S390_lowcore.gmap = (unsigned long) gmap;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gmap_enable);
|
||||
|
@ -254,10 +252,6 @@ EXPORT_SYMBOL_GPL(gmap_enable);
|
|||
*/
|
||||
void gmap_disable(struct gmap *gmap)
|
||||
{
|
||||
/* Load primary space page table origin. */
|
||||
S390_lowcore.user_asce =
|
||||
gmap->mm->context.asce_bits | __pa(gmap->mm->pgd);
|
||||
asm volatile("lctlg 1,1,%0\n" : : "m" (S390_lowcore.user_asce) );
|
||||
S390_lowcore.gmap = 0UL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(gmap_disable);
|
||||
|
@ -309,15 +303,15 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
|
|||
/* Walk the guest addr space page table */
|
||||
table = gmap->table + (((to + off) >> 53) & 0x7ff);
|
||||
if (*table & _REGION_ENTRY_INV)
|
||||
return 0;
|
||||
goto out;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
table = table + (((to + off) >> 42) & 0x7ff);
|
||||
if (*table & _REGION_ENTRY_INV)
|
||||
return 0;
|
||||
goto out;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
table = table + (((to + off) >> 31) & 0x7ff);
|
||||
if (*table & _REGION_ENTRY_INV)
|
||||
return 0;
|
||||
goto out;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
table = table + (((to + off) >> 20) & 0x7ff);
|
||||
|
||||
|
@ -325,6 +319,7 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
|
|||
flush |= gmap_unlink_segment(gmap, table);
|
||||
*table = _SEGMENT_ENTRY_INV;
|
||||
}
|
||||
out:
|
||||
up_read(&gmap->mm->mmap_sem);
|
||||
if (flush)
|
||||
gmap_flush_tlb(gmap);
|
||||
|
|
|
@ -280,7 +280,7 @@ static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
|
|||
return retval;
|
||||
}
|
||||
#else
|
||||
#define srmmu_hwprobe(addr) (srmmu_swprobe(addr, 0) & SRMMU_PTE_PMASK)
|
||||
#define srmmu_hwprobe(addr) srmmu_swprobe(addr, 0)
|
||||
#endif
|
||||
|
||||
static inline int
|
||||
|
|
|
@ -43,6 +43,8 @@
|
|||
#define SUN4V_CHIP_NIAGARA1 0x01
|
||||
#define SUN4V_CHIP_NIAGARA2 0x02
|
||||
#define SUN4V_CHIP_NIAGARA3 0x03
|
||||
#define SUN4V_CHIP_NIAGARA4 0x04
|
||||
#define SUN4V_CHIP_NIAGARA5 0x05
|
||||
#define SUN4V_CHIP_UNKNOWN 0xff
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
|
@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = {
|
|||
((tlb_type == hypervisor && \
|
||||
(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
|
||||
&xor_block_niagara : \
|
||||
&xor_block_VIS)
|
||||
|
|
|
@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void)
|
|||
sparc_pmu_type = "niagara3";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA4:
|
||||
sparc_cpu_type = "UltraSparc T4 (Niagara4)";
|
||||
sparc_fpu_type = "UltraSparc T4 integrated FPU";
|
||||
sparc_pmu_type = "niagara4";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA5:
|
||||
sparc_cpu_type = "UltraSparc T5 (Niagara5)";
|
||||
sparc_fpu_type = "UltraSparc T5 integrated FPU";
|
||||
sparc_pmu_type = "niagara5";
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
|
||||
prom_cpu_compatible);
|
||||
|
|
|
@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
|
|||
case SUN4V_CHIP_NIAGARA1:
|
||||
case SUN4V_CHIP_NIAGARA2:
|
||||
case SUN4V_CHIP_NIAGARA3:
|
||||
case SUN4V_CHIP_NIAGARA4:
|
||||
case SUN4V_CHIP_NIAGARA5:
|
||||
rover_inc_table = niagara_iterate_method;
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -133,7 +133,7 @@ prom_sun4v_name:
|
|||
prom_niagara_prefix:
|
||||
.asciz "SUNW,UltraSPARC-T"
|
||||
prom_sparc_prefix:
|
||||
.asciz "SPARC-T"
|
||||
.asciz "SPARC-"
|
||||
.align 4
|
||||
prom_root_compatible:
|
||||
.skip 64
|
||||
|
@ -396,7 +396,7 @@ sun4v_chip_type:
|
|||
or %g1, %lo(prom_cpu_compatible), %g1
|
||||
sethi %hi(prom_sparc_prefix), %g7
|
||||
or %g7, %lo(prom_sparc_prefix), %g7
|
||||
mov 7, %g3
|
||||
mov 6, %g3
|
||||
90: ldub [%g7], %g2
|
||||
ldub [%g1], %g4
|
||||
cmp %g2, %g4
|
||||
|
@ -408,10 +408,23 @@ sun4v_chip_type:
|
|||
|
||||
sethi %hi(prom_cpu_compatible), %g1
|
||||
or %g1, %lo(prom_cpu_compatible), %g1
|
||||
ldub [%g1 + 7], %g2
|
||||
ldub [%g1 + 6], %g2
|
||||
cmp %g2, 'T'
|
||||
be,pt %xcc, 70f
|
||||
cmp %g2, 'M'
|
||||
bne,pn %xcc, 4f
|
||||
nop
|
||||
|
||||
70: ldub [%g1 + 7], %g2
|
||||
cmp %g2, '3'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_NIAGARA3, %g4
|
||||
cmp %g2, '4'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_NIAGARA4, %g4
|
||||
cmp %g2, '5'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_NIAGARA5, %g4
|
||||
ba,pt %xcc, 4f
|
||||
nop
|
||||
|
||||
|
@ -543,6 +556,12 @@ niagara_tlb_fixup:
|
|||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_NIAGARA3
|
||||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_NIAGARA4
|
||||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_NIAGARA5
|
||||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue