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phy: qcom-qmp: Add SM8150 QMP UFS PHY support
SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register defines and support for SM8150 QMP UFS PHY. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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2 changed files with 216 additions and 0 deletions
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@ -165,6 +165,11 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = {
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[QPHY_PCS_READY_STATUS] = 0x160,
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};
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static const unsigned int sm8150_ufsphy_regs_layout[] = {
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[QPHY_START_CTRL] = 0x00,
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[QPHY_PCS_READY_STATUS] = 0x180,
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};
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static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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@ -879,6 +884,93 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
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};
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static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
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/* Rate B */
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
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};
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static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
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};
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static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
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};
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static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6d),
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QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0a),
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QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02),
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QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43),
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QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1f),
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QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xff),
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QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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@ -1276,6 +1368,31 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
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.is_dual_lane_phy = true,
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};
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static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
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.type = PHY_TYPE_UFS,
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.nlanes = 2,
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.serdes_tbl = sm8150_ufsphy_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
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.tx_tbl = sm8150_ufsphy_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
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.rx_tbl = sm8150_ufsphy_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
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.pcs_tbl = sm8150_ufsphy_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm8150_ufsphy_regs_layout,
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.start_ctrl = SERDES_START,
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.pwrdn_ctrl = SW_PWRDN,
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.is_dual_lane_phy = true,
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.no_pcs_sw_reset = true,
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};
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static void qcom_qmp_phy_configure(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -1998,6 +2115,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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}, {
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.compatible = "qcom,msm8998-qmp-usb3-phy",
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.data = &msm8998_usb3phy_cfg,
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}, {
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.compatible = "qcom,sm8150-qmp-ufs-phy",
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.data = &sm8150_ufsphy_cfg,
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},
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{ },
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};
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@ -313,4 +313,100 @@
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#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
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#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
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/* Only for QMP V4 PHY - QSERDES COM registers */
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#define QSERDES_V4_COM_PLL_IVCO 0x058
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#define QSERDES_V4_COM_CMN_IPTRIM 0x060
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#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
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#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
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#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
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#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
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#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
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#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
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#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
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#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
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#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
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#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
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#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
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#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
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#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
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#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
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#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
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#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
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#define QSERDES_V4_COM_HSCLK_SEL 0x158
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#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
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#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
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#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
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#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
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#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
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#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
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/* Only for QMP V4 PHY - TX registers */
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#define QSERDES_V4_TX_LANE_MODE_1 0x84
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#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
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#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
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#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0
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#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4
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#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
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/* Only for QMP V4 PHY - RX registers */
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#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
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#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
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#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
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#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
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#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
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#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
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#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
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#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
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#define QSERDES_V4_RX_AC_JTAG_MODE 0x078
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#define QSERDES_V4_RX_RX_TERM_BW 0x080
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#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
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#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
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#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
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#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
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#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
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#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
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#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
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#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
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#define QSERDES_V4_RX_SIGDET_LVL 0x120
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#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
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#define QSERDES_V4_RX_RX_BAND 0x128
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#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
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#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
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#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
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#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
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#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
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#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
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#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
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#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
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#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
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#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
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#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
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#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
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#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
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#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
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#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
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#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
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/* Only for QMP V4 PHY - PCS registers */
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#define QPHY_V4_PHY_START 0x000
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#define QPHY_V4_POWER_DOWN_CONTROL 0x004
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#define QPHY_V4_SW_RESET 0x008
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#define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V4_PLL_CNTL 0x02c
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#define QPHY_V4_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V4_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V4_BIST_FIXED_PAT_CTRL 0x060
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#define QPHY_V4_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V4_RX_HSGEAR_CAPABILITY 0x0b4
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#define QPHY_V4_DEBUG_BUS_CLKSEL 0x124
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#define QPHY_V4_LINECFG_DISABLE 0x148
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#define QPHY_V4_RX_MIN_HIBERN8_TIME 0x150
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#define QPHY_V4_RX_SIGDET_CTRL2 0x158
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#define QPHY_V4_TX_PWM_GEAR_BAND 0x160
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#define QPHY_V4_TX_HS_GEAR_BAND 0x168
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#define QPHY_V4_PCS_READY_STATUS 0x180
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#define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8
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#define QPHY_V4_MULTI_LANE_CTRL1 0x1e0
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#endif
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