RISC-V: implement __lshrti3.

Signed-off-by: Alex Guo <xfguo@jlsemi.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Alex Guo 2018-07-29 01:14:47 +00:00 committed by Palmer Dabbelt
parent 4938c79bd0
commit a89757daf2
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3 changed files with 46 additions and 0 deletions

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@ -26,6 +26,9 @@ ifeq ($(CONFIG_ARCH_RV64I),y)
KBUILD_CFLAGS += -mabi=lp64
KBUILD_AFLAGS += -mabi=lp64
KBUILD_CFLAGS += $(call cc-ifversion, -ge, 0500, -DCONFIG_ARCH_SUPPORTS_INT128)
KBUILD_MARCH = rv64im
LDFLAGS += -melf64lriscv
else

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@ -2,5 +2,6 @@ lib-y += delay.o
lib-y += memcpy.o
lib-y += memset.o
lib-y += uaccess.o
lib-y += tishift.o
lib-$(CONFIG_32BIT) += udivdi3.o

42
arch/riscv/lib/tishift.S Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (C) 2018 Free Software Foundation, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
.globl __lshrti3
__lshrti3:
beqz a2, .L1
li a5,64
sub a5,a5,a2
addi sp,sp,-16
sext.w a4,a5
blez a5, .L2
sext.w a2,a2
sll a4,a1,a4
srl a0,a0,a2
srl a1,a1,a2
or a0,a0,a4
sd a1,8(sp)
sd a0,0(sp)
ld a0,0(sp)
ld a1,8(sp)
addi sp,sp,16
ret
.L1:
ret
.L2:
negw a4,a4
srl a1,a1,a4
sd a1,0(sp)
sd zero,8(sp)
ld a0,0(sp)
ld a1,8(sp)
addi sp,sp,16
ret