soc: imx: gpcv2: add support for i.MX8MP power domains
This adds driver support for all the GPC power domains found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Lucas Stach
Shawn Guo
parent
d9651b99dd
commit
a8a2c274dd
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@ -21,10 +21,12 @@
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#include <dt-bindings/power/imx8mq-power.h>
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/power/imx8mn-power.h>
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#include <dt-bindings/power/imx8mp-power.h>
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#define GPC_LPCR_A_CORE_BSC 0x000
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#define GPC_PGC_CPU_MAPPING 0x0ec
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#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
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#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
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#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
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@ -65,6 +67,29 @@
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#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
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#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
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#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
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#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
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#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
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#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
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#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
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#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
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#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
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#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
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#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
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#define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
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#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
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#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
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#define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
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#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
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#define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
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#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
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#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
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#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
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#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
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#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
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#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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@ -107,8 +132,30 @@
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#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
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#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
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#define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
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#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
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#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
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#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
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#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
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#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
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#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
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#define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
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#define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
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#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
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#define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
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#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
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#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
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#define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
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#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
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#define IMX8MP_MLMIX_Pxx_REQ BIT(4)
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#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
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#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
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#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
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#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
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#define GPC_M4_PU_PDN_FLG 0x1bc
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#define IMX8MP_GPC_PU_PWRHSK 0x190
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#define GPC_PU_PWRHSK 0x1fc
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#define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
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@ -118,7 +165,6 @@
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#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
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#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
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#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
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#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
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#define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
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@ -137,6 +183,21 @@
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#define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
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#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
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#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
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#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
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#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
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#define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
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#define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
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#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
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#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
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#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
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#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
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#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
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#define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
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#define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
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#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
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#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
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/*
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* The PGC offset values in Reference Manual
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* (Rev. 1, 01/2018 and the older ones) GPC chapter's
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@ -179,6 +240,28 @@
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#define IMX8MN_PGC_GPUMIX 23
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#define IMX8MN_PGC_DISPMIX 26
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#define IMX8MP_PGC_NOC 9
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#define IMX8MP_PGC_MIPI1 12
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#define IMX8MP_PGC_PCIE 13
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#define IMX8MP_PGC_USB1 14
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#define IMX8MP_PGC_USB2 15
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#define IMX8MP_PGC_MLMIX 16
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#define IMX8MP_PGC_AUDIOMIX 17
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#define IMX8MP_PGC_GPU2D 18
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#define IMX8MP_PGC_GPUMIX 19
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#define IMX8MP_PGC_VPUMIX 20
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#define IMX8MP_PGC_GPU3D 21
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#define IMX8MP_PGC_MEDIAMIX 22
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#define IMX8MP_PGC_VPU_G1 23
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#define IMX8MP_PGC_VPU_G2 24
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#define IMX8MP_PGC_VPU_VC8000E 25
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#define IMX8MP_PGC_HDMIMIX 26
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#define IMX8MP_PGC_HDMI 27
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#define IMX8MP_PGC_MIPI2 28
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#define IMX8MP_PGC_HSIOMIX 29
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#define IMX8MP_PGC_MEDIA_ISP_DWP 30
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#define IMX8MP_PGC_DDRMIX 31
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#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
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#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
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@ -212,6 +295,9 @@ struct imx_pgc_domain {
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const int voltage;
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const bool keep_clocks;
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struct device *dev;
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unsigned int pgc_sw_pup_reg;
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unsigned int pgc_sw_pdn_reg;
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};
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struct imx_pgc_domain_data {
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@ -825,6 +911,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
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.pgc_regs = &imx7_pgc_regs,
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};
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static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
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[IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
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.genpd = {
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.name = "mipi-phy1",
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},
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.bits = {
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.pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
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.map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_MIPI1),
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},
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[IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
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.genpd = {
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.name = "pcie-phy1",
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},
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.bits = {
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.pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
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.map = IMX8MP_PCIE_PHY_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_PCIE),
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},
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[IMX8MP_POWER_DOMAIN_USB1_PHY] = {
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.genpd = {
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.name = "usb-otg1",
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},
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.bits = {
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.pxx = IMX8MP_USB1_PHY_Pxx_REQ,
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.map = IMX8MP_USB1_PHY_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_USB1),
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},
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[IMX8MP_POWER_DOMAIN_USB2_PHY] = {
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.genpd = {
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.name = "usb-otg2",
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},
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.bits = {
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.pxx = IMX8MP_USB2_PHY_Pxx_REQ,
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.map = IMX8MP_USB2_PHY_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_USB2),
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},
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[IMX8MP_POWER_DOMAIN_MLMIX] = {
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.genpd = {
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.name = "mlmix",
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},
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.bits = {
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.pxx = IMX8MP_MLMIX_Pxx_REQ,
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.map = IMX8MP_MLMIX_A53_DOMAIN,
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.hskreq = IMX8MP_MLMIX_PWRDNREQN,
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.hskack = IMX8MP_MLMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_MLMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
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.genpd = {
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.name = "audiomix",
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},
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.bits = {
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.pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
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.map = IMX8MP_AUDIOMIX_A53_DOMAIN,
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.hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
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.hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_AUDIOMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_GPU2D] = {
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.genpd = {
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.name = "gpu2d",
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},
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.bits = {
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.pxx = IMX8MP_GPU_2D_Pxx_REQ,
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.map = IMX8MP_GPU2D_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_GPU2D),
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},
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[IMX8MP_POWER_DOMAIN_GPUMIX] = {
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.genpd = {
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.name = "gpumix",
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},
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.bits = {
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.pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
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.map = IMX8MP_GPUMIX_A53_DOMAIN,
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.hskreq = IMX8MP_GPUMIX_PWRDNREQN,
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.hskack = IMX8MP_GPUMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_GPUMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_VPUMIX] = {
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.genpd = {
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.name = "vpumix",
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},
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.bits = {
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.pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
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.map = IMX8MP_VPUMIX_A53_DOMAIN,
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.hskreq = IMX8MP_VPUMIX_PWRDNREQN,
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.hskack = IMX8MP_VPUMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_VPUMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_GPU3D] = {
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.genpd = {
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.name = "gpu3d",
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},
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.bits = {
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.pxx = IMX8MP_GPU_3D_Pxx_REQ,
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.map = IMX8MP_GPU3D_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_GPU3D),
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},
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[IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
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.genpd = {
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.name = "mediamix",
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},
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.bits = {
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.pxx = IMX8MP_MEDIMIX_Pxx_REQ,
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.map = IMX8MP_MEDIAMIX_A53_DOMAIN,
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.hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
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.hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_MEDIAMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_VPU_G1] = {
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.genpd = {
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.name = "vpu-g1",
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},
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.bits = {
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.pxx = IMX8MP_VPU_G1_Pxx_REQ,
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.map = IMX8MP_VPU_G1_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_VPU_G1),
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},
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[IMX8MP_POWER_DOMAIN_VPU_G2] = {
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.genpd = {
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.name = "vpu-g2",
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},
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.bits = {
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.pxx = IMX8MP_VPU_G2_Pxx_REQ,
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.map = IMX8MP_VPU_G2_A53_DOMAIN
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},
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.pgc = BIT(IMX8MP_PGC_VPU_G2),
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},
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[IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
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.genpd = {
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.name = "vpu-h1",
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},
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.bits = {
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.pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
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.map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
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},
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[IMX8MP_POWER_DOMAIN_HDMIMIX] = {
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.genpd = {
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.name = "hdmimix",
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},
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.bits = {
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.pxx = IMX8MP_HDMIMIX_Pxx_REQ,
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.map = IMX8MP_HDMIMIX_A53_DOMAIN,
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.hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
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.hskack = IMX8MP_HDMIMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_HDMIMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
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.genpd = {
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.name = "hdmi-phy",
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},
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.bits = {
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.pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
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.map = IMX8MP_HDMI_PHY_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_HDMI),
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},
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[IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
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.genpd = {
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.name = "mipi-phy2",
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},
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.bits = {
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.pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
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.map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_MIPI2),
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},
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[IMX8MP_POWER_DOMAIN_HSIOMIX] = {
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.genpd = {
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.name = "hsiomix",
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},
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.bits = {
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.pxx = IMX8MP_HSIOMIX_Pxx_REQ,
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.map = IMX8MP_HSIOMIX_A53_DOMAIN,
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.hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
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.hskack = IMX8MP_HSIOMIX_PWRDNACKN,
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},
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.pgc = BIT(IMX8MP_PGC_HSIOMIX),
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.keep_clocks = true,
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},
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[IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
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.genpd = {
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.name = "mediamix-isp-dwp",
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},
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.bits = {
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.pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
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.map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
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},
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.pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
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},
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};
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static const struct regmap_range imx8mp_yes_ranges[] = {
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regmap_reg_range(GPC_LPCR_A_CORE_BSC,
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IMX8MP_GPC_PGC_CPU_MAPPING),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
|
||||
GPC_PGC_SR(IMX8MP_PGC_NOC)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
|
||||
GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
|
||||
GPC_PGC_SR(IMX8MP_PGC_PCIE)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
|
||||
GPC_PGC_SR(IMX8MP_PGC_USB1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
|
||||
GPC_PGC_SR(IMX8MP_PGC_USB2)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
|
||||
GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
|
||||
GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
|
||||
GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
|
||||
GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
|
||||
GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
|
||||
GPC_PGC_SR(IMX8MP_PGC_HDMI)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
|
||||
GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
|
||||
GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
|
||||
regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
|
||||
GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table imx8mp_access_table = {
|
||||
.yes_ranges = imx8mp_yes_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
|
||||
};
|
||||
|
||||
static const struct imx_pgc_regs imx8mp_pgc_regs = {
|
||||
.map = IMX8MP_GPC_PGC_CPU_MAPPING,
|
||||
.pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
|
||||
.pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
|
||||
.hsk = IMX8MP_GPC_PU_PWRHSK,
|
||||
};
|
||||
static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
|
||||
.domains = imx8mp_pgc_domains,
|
||||
.domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
|
||||
.reg_access_table = &imx8mp_access_table,
|
||||
.pgc_regs = &imx8mp_pgc_regs,
|
||||
};
|
||||
|
||||
static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
|
||||
[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
|
||||
.genpd = {
|
||||
|
|
@ -1120,6 +1503,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
|
|||
domain = pd_pdev->dev.platform_data;
|
||||
domain->regmap = regmap;
|
||||
domain->regs = domain_data->pgc_regs;
|
||||
|
||||
domain->genpd.power_on = imx_pgc_power_up;
|
||||
domain->genpd.power_off = imx_pgc_power_down;
|
||||
|
||||
|
|
@ -1141,6 +1525,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
|
|||
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
|
||||
{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
|
||||
{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
|
||||
{ .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
|
||||
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue