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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-28 15:20:41 +00:00
Merge branch 'pci/enumeration'
- Work around IDT switch ACS Source Validation erratum (James Puthukattukaran) - Emit diagnostics for all cases of PCIe Link downtraining (Links operating slower than they're capable of) (Alexandru Gagniuc) - Skip VFs when configuring Max Payload Size (Myron Stowe) - Reduce Root Port Max Payload Size if necessary when hot-adding a device below it (Myron Stowe) * pci/enumeration: PCI: Match Root Port's MPS to endpoint's MPSS as necessary PCI: Skip MPS logic for Virtual Functions (VFs) PCI: Check for PCIe Link downtraining PCI: Workaround IDT switch ACS Source Validation erratum
This commit is contained in:
commit
a8bcb5e596
4 changed files with 135 additions and 11 deletions
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@ -5301,14 +5301,16 @@ u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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}
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}
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/**
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/**
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* pcie_print_link_status - Report the PCI device's link speed and width
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* __pcie_print_link_status - Report the PCI device's link speed and width
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* @dev: PCI device to query
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* @dev: PCI device to query
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* @verbose: Print info even when enough bandwidth is available
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*
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*
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* Report the available bandwidth at the device. If this is less than the
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* If the available bandwidth at the device is less than the device is
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* device is capable of, report the device's maximum possible bandwidth and
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* capable of, report the device's maximum possible bandwidth and the
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* the upstream link that limits its performance to less than that.
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* upstream link that limits its performance. If @verbose, always print
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* the available bandwidth, even if the device isn't constrained.
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*/
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*/
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void pcie_print_link_status(struct pci_dev *dev)
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void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
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{
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{
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enum pcie_link_width width, width_cap;
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enum pcie_link_width width, width_cap;
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enum pci_bus_speed speed, speed_cap;
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enum pci_bus_speed speed, speed_cap;
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@ -5318,11 +5320,11 @@ void pcie_print_link_status(struct pci_dev *dev)
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bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
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bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
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bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
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bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
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if (bw_avail >= bw_cap)
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if (bw_avail >= bw_cap && verbose)
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pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
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pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
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bw_cap / 1000, bw_cap % 1000,
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bw_cap / 1000, bw_cap % 1000,
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PCIE_SPEED2STR(speed_cap), width_cap);
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PCIE_SPEED2STR(speed_cap), width_cap);
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else
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else if (bw_avail < bw_cap)
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pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
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pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
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bw_avail / 1000, bw_avail % 1000,
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bw_avail / 1000, bw_avail % 1000,
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PCIE_SPEED2STR(speed), width,
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PCIE_SPEED2STR(speed), width,
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@ -5330,6 +5332,17 @@ void pcie_print_link_status(struct pci_dev *dev)
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bw_cap / 1000, bw_cap % 1000,
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bw_cap / 1000, bw_cap % 1000,
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PCIE_SPEED2STR(speed_cap), width_cap);
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PCIE_SPEED2STR(speed_cap), width_cap);
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}
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}
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/**
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* pcie_print_link_status - Report the PCI device's link speed and width
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* @dev: PCI device to query
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*
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* Report the available bandwidth at the device.
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*/
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void pcie_print_link_status(struct pci_dev *dev)
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{
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__pcie_print_link_status(dev, true);
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}
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EXPORT_SYMBOL(pcie_print_link_status);
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EXPORT_SYMBOL(pcie_print_link_status);
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/**
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/**
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@ -225,6 +225,10 @@ enum pci_bar_type {
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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int crs_timeout);
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bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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int pci_setup_device(struct pci_dev *dev);
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int reg);
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struct resource *res, unsigned int reg);
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@ -259,6 +263,7 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
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enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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enum pcie_link_width *width);
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enum pcie_link_width *width);
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void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
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/* Single Root I/O Virtualization */
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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struct pci_sriov {
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@ -1724,11 +1724,15 @@ int pci_setup_device(struct pci_dev *dev)
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static void pci_configure_mps(struct pci_dev *dev)
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static void pci_configure_mps(struct pci_dev *dev)
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{
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{
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struct pci_dev *bridge = pci_upstream_bridge(dev);
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struct pci_dev *bridge = pci_upstream_bridge(dev);
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int mps, p_mps, rc;
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int mps, mpss, p_mps, rc;
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if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
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if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
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return;
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return;
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/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
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if (dev->is_virtfn)
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return;
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mps = pcie_get_mps(dev);
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mps = pcie_get_mps(dev);
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p_mps = pcie_get_mps(bridge);
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p_mps = pcie_get_mps(bridge);
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@ -1748,6 +1752,14 @@ static void pci_configure_mps(struct pci_dev *dev)
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if (pcie_bus_config != PCIE_BUS_DEFAULT)
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if (pcie_bus_config != PCIE_BUS_DEFAULT)
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return;
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return;
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mpss = 128 << dev->pcie_mpss;
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if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
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pcie_set_mps(bridge, mpss);
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pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
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mpss, p_mps, 128 << bridge->pcie_mpss);
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p_mps = pcie_get_mps(bridge);
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}
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rc = pcie_set_mps(dev, p_mps);
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rc = pcie_set_mps(dev, p_mps);
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if (rc) {
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if (rc) {
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pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
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pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
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@ -1756,7 +1768,7 @@ static void pci_configure_mps(struct pci_dev *dev)
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}
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}
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pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
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pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
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p_mps, mps, 128 << dev->pcie_mpss);
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p_mps, mps, mpss);
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}
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}
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static struct hpp_type0 pci_default_type0 = {
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static struct hpp_type0 pci_default_type0 = {
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@ -2156,8 +2168,8 @@ static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
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return true;
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return true;
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}
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}
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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int timeout)
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int timeout)
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{
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{
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
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return false;
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return false;
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@ -2172,6 +2184,24 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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return true;
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return true;
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}
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}
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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int timeout)
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{
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#ifdef CONFIG_PCI_QUIRKS
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struct pci_dev *bridge = bus->self;
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/*
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* Certain IDT switches have an issue where they improperly trigger
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* ACS Source Validation errors on completions for config reads.
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*/
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if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
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bridge->device == 0x80b5)
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return pci_idt_bus_quirk(bus, devfn, l, timeout);
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#endif
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return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
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}
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EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
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EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
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/*
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/*
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@ -2205,6 +2235,25 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
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return dev;
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return dev;
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}
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}
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static void pcie_report_downtraining(struct pci_dev *dev)
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{
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if (!pci_is_pcie(dev))
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return;
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/* Look from the device up to avoid downstream ports with no devices */
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if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
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(pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
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(pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
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return;
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/* Multi-function PCIe devices share the same link/status */
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if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
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return;
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/* Print link status only if the device is constrained by the fabric */
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__pcie_print_link_status(dev, false);
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}
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static void pci_init_capabilities(struct pci_dev *dev)
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static void pci_init_capabilities(struct pci_dev *dev)
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{
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{
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/* Enhanced Allocation */
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/* Enhanced Allocation */
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@ -2240,6 +2289,8 @@ static void pci_init_capabilities(struct pci_dev *dev)
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/* Advanced Error Reporting */
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/* Advanced Error Reporting */
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pci_aer_init(dev);
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pci_aer_init(dev);
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pcie_report_downtraining(dev);
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if (pci_probe_reset_function(dev) == 0)
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if (pci_probe_reset_function(dev) == 0)
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dev->reset_fn = 1;
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dev->reset_fn = 1;
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}
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}
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@ -4753,3 +4753,58 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
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PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
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PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
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PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
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/*
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* Some IDT switches incorrectly flag an ACS Source Validation error on
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* completions for config read requests even though PCIe r4.0, sec
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* 6.12.1.1, says that completions are never affected by ACS Source
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* Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
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*
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* Item #36 - Downstream port applies ACS Source Validation to Completions
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* Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
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* completions are never affected by ACS Source Validation. However,
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* completions received by a downstream port of the PCIe switch from a
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* device that has not yet captured a PCIe bus number are incorrectly
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* dropped by ACS Source Validation by the switch downstream port.
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*
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* The workaround suggested by IDT is to issue a config write to the
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* downstream device before issuing the first config read. This allows the
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* downstream device to capture its bus and device numbers (see PCIe r4.0,
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* sec 2.2.9), thus avoiding the ACS error on the completion.
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*
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* However, we don't know when the device is ready to accept the config
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* write, so we do config reads until we receive a non-Config Request Retry
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* Status, then do the config write.
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*
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* To avoid hitting the erratum when doing the config reads, we disable ACS
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* SV around this process.
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*/
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int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
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{
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int pos;
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u16 ctrl = 0;
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bool found;
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struct pci_dev *bridge = bus->self;
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pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);
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/* Disable ACS SV before initial config reads */
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if (pos) {
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pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
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if (ctrl & PCI_ACS_SV)
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pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
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ctrl & ~PCI_ACS_SV);
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}
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found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
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/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
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if (found)
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pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
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/* Re-enable ACS_SV if it was previously enabled */
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if (ctrl & PCI_ACS_SV)
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pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
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return found;
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}
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