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iommu/io-pgtable: Remove non-strict quirk
IO_PGTABLE_QUIRK_NON_STRICT was never a very comfortable fit, since it's not a quirk of the pagetable format itself. Now that we have a more appropriate way to convey non-strict unmaps, though, this last of the non-quirk quirks can also go, and with the flush queue code also now enforcing its own ordering we can have a lovely cleanup all round. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/155b5c621cd8936472e273a8b07a182f62c6c20d.1628682049.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
parent
7a7c5badf8
commit
a8e5f04458
5 changed files with 4 additions and 31 deletions
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@ -2174,9 +2174,6 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain,
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.iommu_dev = smmu->dev,
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.iommu_dev = smmu->dev,
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};
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};
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if (!iommu_get_dma_strict(domain))
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pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
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pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
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pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
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if (!pgtbl_ops)
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if (!pgtbl_ops)
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return -ENOMEM;
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return -ENOMEM;
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@ -765,9 +765,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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.iommu_dev = smmu->dev,
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.iommu_dev = smmu->dev,
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};
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};
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if (!iommu_get_dma_strict(domain))
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pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
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if (smmu->impl && smmu->impl->init_context) {
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if (smmu->impl && smmu->impl->init_context) {
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ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev);
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ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev);
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if (ret)
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if (ret)
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@ -700,14 +700,7 @@ static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
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ARM_V7S_BLOCK_SIZE(lvl + 1));
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ARM_V7S_BLOCK_SIZE(lvl + 1));
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ptep = iopte_deref(pte[i], lvl, data);
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ptep = iopte_deref(pte[i], lvl, data);
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__arm_v7s_free_table(ptep, lvl + 1, data);
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__arm_v7s_free_table(ptep, lvl + 1, data);
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} else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
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} else if (!gather->queued) {
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/*
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* Order the PTE update against queueing the IOVA, to
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* guarantee that a flush callback from a different CPU
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* has observed it before the TLBIALL can be issued.
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*/
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smp_wmb();
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} else {
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io_pgtable_tlb_add_page(iop, gather, iova, blk_size);
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io_pgtable_tlb_add_page(iop, gather, iova, blk_size);
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}
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}
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iova += blk_size;
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iova += blk_size;
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@ -791,8 +784,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
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if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
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if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
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IO_PGTABLE_QUIRK_NO_PERMS |
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IO_PGTABLE_QUIRK_NO_PERMS |
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IO_PGTABLE_QUIRK_ARM_MTK_EXT |
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IO_PGTABLE_QUIRK_ARM_MTK_EXT))
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IO_PGTABLE_QUIRK_NON_STRICT))
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return NULL;
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return NULL;
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/* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
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/* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
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@ -638,14 +638,7 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
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io_pgtable_tlb_flush_walk(iop, iova + i * size, size,
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io_pgtable_tlb_flush_walk(iop, iova + i * size, size,
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ARM_LPAE_GRANULE(data));
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ARM_LPAE_GRANULE(data));
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__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
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__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
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} else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
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} else if (!gather->queued) {
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/*
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* Order the PTE update against queueing the IOVA, to
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* guarantee that a flush callback from a different CPU
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* has observed it before the TLBIALL can be issued.
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*/
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smp_wmb();
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} else {
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io_pgtable_tlb_add_page(iop, gather, iova + i * size, size);
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io_pgtable_tlb_add_page(iop, gather, iova + i * size, size);
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}
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}
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@ -825,7 +818,6 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
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bool tg1;
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bool tg1;
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if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
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if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
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IO_PGTABLE_QUIRK_NON_STRICT |
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IO_PGTABLE_QUIRK_ARM_TTBR1 |
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IO_PGTABLE_QUIRK_ARM_TTBR1 |
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IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
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IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
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return NULL;
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return NULL;
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@ -929,7 +921,7 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
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typeof(&cfg->arm_lpae_s2_cfg.vtcr) vtcr = &cfg->arm_lpae_s2_cfg.vtcr;
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typeof(&cfg->arm_lpae_s2_cfg.vtcr) vtcr = &cfg->arm_lpae_s2_cfg.vtcr;
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/* The NS quirk doesn't apply at stage 2 */
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/* The NS quirk doesn't apply at stage 2 */
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if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT))
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if (cfg->quirks)
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return NULL;
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return NULL;
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data = arm_lpae_alloc_pgtable(cfg);
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data = arm_lpae_alloc_pgtable(cfg);
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@ -73,10 +73,6 @@ struct io_pgtable_cfg {
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* to support up to 35 bits PA where the bit32, bit33 and bit34 are
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* to support up to 35 bits PA where the bit32, bit33 and bit34 are
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* encoded in the bit9, bit4 and bit5 of the PTE respectively.
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* encoded in the bit9, bit4 and bit5 of the PTE respectively.
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*
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*
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* IO_PGTABLE_QUIRK_NON_STRICT: Skip issuing synchronous leaf TLBIs
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* on unmap, for DMA domains using the flush queue mechanism for
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* delayed invalidation.
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*
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* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
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* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
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* for use in the upper half of a split address space.
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* for use in the upper half of a split address space.
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*
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*
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@ -86,7 +82,6 @@ struct io_pgtable_cfg {
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#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
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#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
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#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
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#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
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#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
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#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
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#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)
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#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
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#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
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#define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
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#define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
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unsigned long quirks;
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unsigned long quirks;
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